JP5509513B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a MOS field effect transistor (hereinafter referred to as MOSFET) having a gate structure of metal (M) -oxide film (O) -semiconductor layer (S), particularly between electrodes provided on both sides of a semiconductor substrate. The present invention relates to a vertical semiconductor device through which current flows.

In general, a vertical semiconductor device in which a current flows between electrodes provided on both surfaces of a semiconductor substrate is often used as a power semiconductor device.
FIG. 8 is a cross-sectional view of a main part of a conventional semiconductor device. This figure is a cross-sectional view of the main part of the active part of a planar type n-channel vertical MOSFET.
In this vertical MOSFET, a high resistance n ⁻ drift layer 2 serving as a voltage support layer is disposed on a low resistance n ⁺ drain layer 1 to which a drain electrode 10 is conductively bonded, and selectively on the n ⁻ drift layer 2. The p base region 3 is disposed on the surface of the p base region 3, and an n ⁺ source region 4 is selectively formed on the surface layer of the p base region 3. A gate electrode 7 a is provided on the surface of the p base region 3 sandwiched between the n ⁺ source region 4 and the n ⁻ drift layer 2 via the gate insulating film 6, and the n ⁺ source region 4 and the p base region 3 A source electrode 9 is provided in common contact with the surface.

Gate electrode 7 a is insulated from n ⁺ source region 4 and p base region 3 by interlayer insulating film 8. Reference numeral 7 in the drawing is a gate electrode (generic name) that collectively represents the individual gate electrodes 7a.
In some cases, the p ⁺ contact region 5 is provided on the surface of the p base region 3 in the device that contacts the source electrode 9 in order to reduce the contact resistance with the source electrode 9 or to improve the latch-up resistance. .

In order to reduce the on-resistance of the vertical MOSFET, the gate electrode length Lg0 and the contact opening length L0 are shortened to reduce the cell pitch W0, and the junction surface between the p base region 3 and the n ⁻ drift layer 2 is close to a planar junction. In this state, the tip of the depletion layer 12 is flattened so that a predetermined breakdown voltage can be obtained even if the impurity concentration of the n ⁻ drift layer 2 is increased. That is, the on-resistance is reduced by increasing the impurity concentration of the n ⁻ drift layer 2.

According to Patent Document 1, in a trench gate type IGBT (referred to as a trench gate type IEGT in Patent Document 1 but a kind of IGBT), an n emitter region is formed in a p base region sandwiched between trenches (Patent Document). 1 is provided with a portion where an n source region is to be formed and a portion where an n emitter region is not formed, thereby providing a p collector region (in Patent Literature 1, an n base region) below a location where an n emitter region is not formed. The holes injected from the (p emitter region) are accumulated to reduce the on-voltage, and the gate electrode not forming the n emitter region is connected to the emitter electrode, thereby improving the breakdown voltage and reducing the input capacitance (gate capacitance). Is disclosed.
Japanese Patent No. 3400348 FIG.

However, in FIG. 8, if the gate electrode length Lg0 and the contact opening length L0 are shortened and the cell pitch W0 is shortened (miniaturized), a low on-resistance can be ensured, but if the contact opening length L0 is shortened, the cell pitch The ratio of the gate electrode length Lg0 to W0 increases, and the input capacitance Ciss (gate-source capacitance Cgs + gate-drain capacitance Cgd) increases. When the cell pitch W0 is shortened, even if the surface layer 11 of the n ⁻ drift layer 2 sandwiched between the p base regions 3 is made high in concentration so that the JFET effect is less likely to appear, the JFET effect is somewhat present. The width of the surface layer 11 of the n ⁻ drift layer 2 cannot be reduced to the extent that the width of 11 is made shorter than the cell pitch W0. Therefore, the gate electrode length Lg0 cannot be shortened as much as the cell pitch W0 is shortened. When the cell pitch W0 is shortened, the ratio of the gate electrode length Lg0 to the cell pitch W0 is increased. As a result, the input capacitance Ciss increases.

When the input capacitance Ciss increases, the delay time (td (off) and td (on)) during the switching operation increases, which hinders high-frequency operation. This delay time is a delay time during the turn-off operation. In addition, drive loss (1/2 (Ciss · Vg ² )) and switching loss (turn-on loss and turn-off loss occurring during the delay period) increase. Since there is no minority carrier accumulation in the n ⁻ drift layer 2 in the MOSFET, the delay time strongly depends on the input capacitance.
In addition, when the chip size is reduced in order to reduce the input capacitance ciss, the on-resistance is naturally increased.

The semiconductor device described in Patent Document 1 is a trench gate type IGBT, and no mention is made of a planar gate type IGBT.
Further, in the IGBT, the delay time at the time of the switching operation is mainly dominated by the disappearance time of excess carriers stored in the n ⁻ drift layer 2, and the input capacitance ciss is less dependent. Even if it is reduced, the effect of shortening the delay time is small, and the effect of reducing the switching loss is also small.

  The object of the present invention is to solve the above-mentioned problems, to reduce the input capacitance while maintaining a low on-resistance, to reduce the switching loss by shortening the delay time, and to further reduce the drive loss. It is an object of the present invention to provide a semiconductor device capable of achieving the above.

To achieve the above objective,
A plurality of second-conductivity-type first semiconductor regions (base regions) formed in the surface layer on the first main surface side of the first-conductivity-type first semiconductor layer (drift layer);
A second semiconductor region (source region) of a first conductivity type selectively formed in a surface layer of the first semiconductor region;
A gate electrode formed via a gate insulating film so as to straddle the second semiconductor region and the first semiconductor region sandwiched between the first semiconductor layer and the first semiconductor layer;
An interlayer insulating film covering the gate electrode;
A first main electrode (source electrode) formed on the interlayer insulating film in contact with the first semiconductor region and the second semiconductor region;
A second semiconductor layer (drain layer) of a first conductivity type having a higher impurity concentration than the first semiconductor layer disposed on the second main surface side of the first semiconductor layer ;
In a semiconductor device having a second main electrode (drain electrode) formed on the back surface of the second semiconductor layer,
The gate electrode includes a first gate electrode that is insulated from the first main electrode by an interlayer insulating film covering the upper portion and receives a gate signal, and a second gate that is electrically isolated from the first gate electrode An electrode,
The first gate electrode and the second gate electrode are opposed in a comb shape ,
The second gate electrode is connected to the first main electrode .

Also, it may be separated from the said interlayer insulating film with the second gate electrode is a part of the first main electrode.
A plurality of second conductivity type first semiconductor regions formed in a surface layer on the first main surface side of the first conductivity type first semiconductor layer;
A second semiconductor region of a first conductivity type selectively formed on a surface layer of the first semiconductor region;
A gate electrode formed via a gate insulating film so as to straddle the second semiconductor region and the first semiconductor region sandwiched between the first semiconductor layer and the first semiconductor layer;
An interlayer insulating film covering the gate electrode;
A first main electrode formed on the interlayer insulating film in contact with the first semiconductor region and the second semiconductor region;
A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer disposed on the second main surface side of the first semiconductor layer;
In a semiconductor device having a second main electrode formed on the back surface of the second semiconductor layer,
The gate electrode includes a first gate electrode that is insulated from the first main electrode by an interlayer insulating film covering the upper portion and receives a gate signal, and a second gate that is electrically isolated from the first gate electrode An electrode,
The first gate electrode and the second gate electrode are opposed in a comb shape,
The second gate electrode is floated der Rutotomoni entirely be covered with the interlayer insulating film.
The number of unit cells having the first gate electrode is defined as a region sandwiched between the center line of the first semiconductor region and the center line of the first semiconductor region adjacent to the first semiconductor region. pieces respect, the second gate electrode number of poles shorted to the first main electrode may be any of 2-4.
The planar pattern of the gate electrode may be striped, and the gate electrode length of the first gate electrode may be equal to the gate electrode length of the second gate electrode.
Further, in the cell pitch W1 of the unit cell, if the width of the first semiconductor region is M and the width of the first semiconductor layer between the adjacent first semiconductor regions is N, M + N = W1, and M > N may be sufficient.
In the unit cell having the second gate electrode, the first semiconductor region may be directly under the second gate electrode end with the gate insulating film interposed therebetween.
The width of the first semiconductor region having at least one second gate electrode on the top may be shorter than the width of the first semiconductor region having only the first gate electrode on the top.
The breakdown voltage of the semiconductor device by a pn junction formed by the first semiconductor layer and the first semiconductor region may be 90% or more of an ideal breakdown voltage by a planar junction.
The first semiconductor layer may have a thickness of 30 μm or more.
The second semiconductor layer may be a semiconductor substrate, and the first semiconductor layer may be an epitaxial layer formed on the semiconductor substrate.

According to the present invention, the input capacitance is reduced while maintaining a low on-resistance by providing a region between the base regions where the gate electrode to which the gate signal is input is disposed and a region where the gate signal is not input between the base regions. Can be reduced.
By reducing the input capacitance, the delay time during the switching operation can be shortened, switching loss and drive loss can be reduced, and a vertical MOSFET capable of high-frequency operation can be provided.

  Embodiments will be described in the following examples. In the following description of the drawings, the first conductivity type is n-type and the second conductivity type is p-type. The same parts as those in FIG.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. This figure is a sectional view of the main part of the active part and the gate electrode of an n-channel vertical MOSFET of a planar type semiconductor.
This n-channel vertical MOSFET includes an n ⁺ drain layer 1, an n ⁻ drift layer 2 formed on the n ⁺ drain layer 1, a p base region 3 formed on a surface layer of the n ⁻ drift layer 2, An n ⁺ source region 4 formed in the surface layer of the p base region 3, a p base region 3 sandwiched between the n ⁺ source region 4 and the n ⁻ drift layer 2, and the n ⁻ drift layer 2. a gate insulating film 6 gate electrode 7 formed through the, and p ⁺ contact region 5 formed on the surface layer of the p base region 3 so as to be deeper than the overlapping n ⁺ source region 4 and the n ⁺ source region 4, An interlayer insulating film 8 formed so as to cover the surface of every other gate electrode 7a among the gate electrodes 7 so that a part of the n ⁺ source region and the p ⁺ contact region 5 are exposed; Gauge not covered by the interlayer insulating film 8 Gate electrode 7b (arranged next to gate electrode 7a), a portion of exposed n ⁺ source region 4 and source electrode 9 formed over p ⁺ contact region 5, n ⁺ drain layer 1 And the drain electrode 10 formed on the back surface of the substrate. The planar pattern of the p base region 3, the n ⁺ source region 4 and the gate electrode 7 (generic name consisting of the gate electrodes 7a and 7b) is striped, and the figure is perpendicular to the longitudinal direction of the pattern. It is principal part sectional drawing at the time of cut | disconnecting.

The gate electrode 7b not covered with the interlayer insulating film 8 is electrically separated from the gate electrode 7a covered with the interlayer insulating film 8 to which the gate signal is input, so that the gate signal does not enter. By connecting to the source electrode 9, the input capacitance Ciss generated in the gate electrode 7b is eliminated.
The source electrode 9 and the gate electrode 7b may be connected to the entire surface of the gate electrode 7b, or may be partially covered by covering the gate electrode 9b with the interlayer insulating film 8 and forming an opening in part of the interlayer insulating film 8. What is important is that the gate electrode 7a and the gate electrode 7b are electrically separated.

  A region sandwiched between the center line of the p base region 3 and the center line of the adjacent p base region 3 is the cell 14. The width of the cell is equal to the distance from the end of the p base region 3 to the end of the adjacent p base region 3, which is the cell pitch W1. The cell pitch W1 is about 15 μm. When the cell pitch W1 is as small as about 15 μm and the width of the p base region 3 (M in FIG. 5) is about 9 μm, the joint surface becomes close to planar junction, the tip of the depletion layer 12 is flattened, and close to the ideal breakdown voltage. A breakdown voltage (90% or more of the breakdown voltage in planar bonding) is obtained.

Further, the above n ⁺ drain layer 1 is a high-concentration of n semiconductor substrate, by laminating an n-type epitaxial layer of n thereon ^- may be formed drift layer 2. Other the n ^- drift layer 2 may be formed n ⁺ drain layer 1 by diffusing an n-type impurity at a high concentration on the rear surface as an n semiconductor substrate.
As described above, the interlayer insulating film 8 that insulates the gate electrode 7 from some of the many cells 13 (every other cell in FIG. 1) is eliminated, and the gate signal is transmitted to the gate electrode 7b. The gate electrode 7b is separated from the input external gate wiring (gate electrode 7a covered with the interlayer insulating film 8), and the gate electrode 7b without the interlayer insulating film 8 and the source electrode 9 are short-circuited. With such a structure, the junction surface between the p base region 3 and the n ⁻ drift layer 2 has a shape close to a planar junction, and a breakdown voltage close to the ideal breakdown voltage can be obtained as described above. The gate electrode 7a and the gate electrode 7b may be separated from each other, for example, in a comb shape.

  Also, the input capacitance Ciss can be reduced by short-circuiting the gate electrode 7b without the interlayer insulating film 8 with the source electrode 9. By reducing the input capacitance Ciss, the delay time during the switching operation can be shortened, the turn-off loss (part of the switching loss) occurring during this delay time can be reduced, and the drive loss can be further reduced. And can be operated at high frequency. In this embodiment, since the mask only needs to be changed so that the interlayer insulating film 8 remains only on the gate electrode 7a, the manufacture is also easy.

Further, in the cell 13 in which the gate electrode 7b is short-circuited to the source electrode 9 in this way, a channel is not formed and the channel resistance is increased. However, in an n-channel vertical MOSFET of 300 V to 500 V or more, the ratio of channel resistance to on-resistance is several percent, and the increase in on-resistance is slightly increased. Therefore, both low on-resistance and low input capacitance can be achieved. In the above-mentioned breakdown voltage range, the thickness of the n ⁻ drift layer is about 30 μm or more.
FIG. 2 is a diagram illustrating the relationship between the input capacitance Ciss and the on-resistance RDS (on). This figure shows the calculated input capacitance Ciss and on-resistance RDS (on) normalized. FIG. 2 also shows the conventional element of FIG. 8 for comparison. In the figure, a, b, c, d, and e are the number of gate electrodes to be short-circuited (the number of short-circuit electrodes) are 0, 1, 2, 3, and 4, respectively, a is a conventional element, and b to e are elements of the present invention. . Note that b is the first embodiment, and c to e are modifications not shown.
As can be seen from FIG. 2, by increasing the number of cells to be short-circuited, the on-resistance RDS (on) hardly changes and the input capacitance Ciss can be greatly reduced. However, the on-resistance RDS (on) was calculated on the assumption that only the channel resistance changed. Actually, if the number of cells to be short-circuited is increased, the ineffective region that does not function as a current path increases.
In addition, a dotted line D of 45 degrees in the drawing is a case where the chip size is changed without changing the cell pitch W1, and when the chip size is reduced, the input capacitance Ciss decreases and the on-resistance RDS (on) increases.
The entire surface of the gate electrode 7b may be covered with an interlayer insulating film, and the gate electrode 7b may be in a floating state where no connection is made. In this case, since the mask for forming the interlayer insulating film 8 may be the same as that of the prior art, the manufacturing is easy.

FIG. 3 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from FIG. 1 is that the gate electrode 7b is removed or not formed only by providing the gate insulating film 6. The effect is the same as in FIG. 1, and the region where the gate electrode 7b is removed or not formed. The input capacitance Ciss is reduced.
In this embodiment, by not providing the gate electrode 7b, the positional relationship is such that the arrangement interval of the gate electrodes 7a is widened, and the flatness of the surface of the source electrode 9 is increased. An interlayer insulating film 8 may be provided on the gate insulating film 6 in a region where the gate electrode 7b is not removed or formed.

FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The difference from FIG. 1 is that the n ⁺ source region 4 on the gate electrode 7 b side is removed from the n ⁺ source region 4 formed in the surface layer of the p base region 3. Also in this case, the effect is the same as in FIG.
FIGS. 5 and 6 show the surface portion of the p base region 3 in FIGS. 3 and 4 in an enlarged manner. In this figure, the p ⁺ contact region 5 and the source electrode 9 are omitted. In the figure, Lg is the gate electrode length, W1 is the cell pitch, Ls is the gate electrode length not covered with the interlayer insulating film, M is the p base region width, N is the distance between the p base regions, L1 is the contact opening length, and K is The distance from the gate electrode end to the interlayer insulating film end, T is the distance from the gate electrode end to the p base region end, J is the distance from the interlayer insulating film end to the p base region end, and H is the distance between the n source regions. is there. These dimensions are the same in FIG. 5 (enlarged view of FIG. 1) and FIG. 6 (enlarged view of FIG. 4).

Here, Lg = Ls = N + 2T, L1 = 2J + K + H, M = 2 (T + K + J) + H, and W1 = M + N = Lg + Ls + K.
Next, a method for shortening the cell pitch W1 shown in FIG. 6 will be described.

FIG. 7 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. The difference from FIG. 4 (FIG. 6) is that the gate electrode 7b not covered with the interlayer insulating film 8 is brought close to the covered gate electrode 7a. As a result, the contact opening length L2 in FIG. 7 is shorter than the contact opening length L1 in FIG. 6, and the p base region width Q in FIG. 7 is narrower than the p base region width M in FIG. Therefore, the cell pitch W2 in FIG. 7 is narrower than the cell pitch W1 in FIG. By reducing the cell pitch W2, the breakdown voltage can be ensured even when the junction becomes closer to a flat junction and the impurity concentration of the n ⁻ drift layer 2 is increased. By increasing the impurity concentration, the channel density can be increased as compared with FIG. 6 and the on-resistance RDS (on) can be reduced.

Although the first to fourth embodiments have been described using the n-channel vertical MOSFET, the present invention can naturally be applied to a p-channel vertical MOSFET, and the effect is the same as described above.
The present invention can also be applied to a planar gate type IGBT. The main effect at that time is reduction of drive loss and improvement of breakdown voltage because it is close to planar junction.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. The figure which shows the relationship between input capacitance Ciss and ON resistance RDS (on) Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention of this invention The figure which expanded and showed the surface part from p base area | region 3 of FIG. The figure which expanded and showed the surface part from p base area | region 3 of FIG. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Sectional view of the main part of a conventional semiconductor device

Explanation of symbols

1 n ⁺ drain layer 2 n ^- drift layer 3 p base region 4 n ⁺ source region 5 p + contact region 6 gate insulating film 7, 7a, 7b gate electrode 8 interlayer insulating film 9 source electrode 10 drain electrode 11 surface layer 12 depletion layer 13 Chuo Line 14 cells

Claims (11)

A plurality of second conductivity type first semiconductor regions formed in a surface layer on the first main surface side of the first conductivity type first semiconductor layer;
A second semiconductor region of a first conductivity type selectively formed on a surface layer of the first semiconductor region;
A gate electrode formed via a gate insulating film so as to straddle the second semiconductor region and the first semiconductor region sandwiched between the first semiconductor layer and the first semiconductor layer;
An interlayer insulating film covering the gate electrode;
A first main electrode formed on the interlayer insulating film in contact with the first semiconductor region and the second semiconductor region;
A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer disposed on the second main surface side of the first semiconductor layer ;
In a semiconductor device having a second main electrode formed on the back surface of the second semiconductor layer,
The gate electrode includes a first gate electrode that is insulated from the first main electrode by an interlayer insulating film covering the upper portion and receives a gate signal, and a second gate that is electrically isolated from the first gate electrode An electrode,
The first gate electrode and the second gate electrode are opposed in a comb-tooth shape ,
The semiconductor device, wherein the second gate electrode is connected to the first main electrode . The semiconductor device according to claim 1, wherein the second gate electrode is a part of the first main electrode and is separated from the interlayer insulating film . A plurality of second conductivity type first semiconductor regions formed in a surface layer on the first main surface side of the first conductivity type first semiconductor layer;
A second semiconductor region of a first conductivity type selectively formed on a surface layer of the first semiconductor region;
A gate electrode formed via a gate insulating film so as to straddle the second semiconductor region and the first semiconductor region sandwiched between the first semiconductor layer and the first semiconductor layer;
An interlayer insulating film covering the gate electrode;
A first main electrode formed on the interlayer insulating film in contact with the first semiconductor region and the second semiconductor region;
A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer disposed on the second main surface side of the first semiconductor layer;
In a semiconductor device having a second main electrode formed on the back surface of the second semiconductor layer,
The gate electrode includes a first gate electrode that is insulated from the first main electrode by an interlayer insulating film covering the upper portion and receives a gate signal, and a second gate that is electrically isolated from the first gate electrode An electrode,
The first gate electrode and the second gate electrode are opposed in a comb-tooth shape,
A semiconductor device, wherein the entire surface of the second gate electrode is covered with the interlayer insulating film and is in a floating state . A region sandwiched between the center line of the first semiconductor region and the center line of the first semiconductor region adjacent to the first semiconductor region is defined as a unit cell.
The number of the second gate electrodes short-circuited to the first main electrode is one of 2 to 4 for one unit cell having the first gate electrode. The semiconductor device according to any one of the above . The planar pattern of the gate electrode is striped, and the gate electrode length of the first gate electrode is equal to the gate electrode length of the second gate electrode. Semiconductor device . When the width of the first semiconductor region is M and the width of the first semiconductor layer between the adjacent first semiconductor regions is N in the cell pitch W1 of the unit cell, M + N = W1, and M> N The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device . 7. The unit cell having the second gate electrode, wherein the first semiconductor region is directly under the end of the second gate electrode across the gate insulating film. A semiconductor device according to 1 . The width of the first semiconductor region having at least one second gate electrode on the top is shorter than the width of the first semiconductor region having only the first gate electrode on the top. The semiconductor device described . 9. The breakdown voltage of the semiconductor device by a pn junction formed by the first semiconductor layer and the first semiconductor region is 90% or more of an ideal breakdown voltage by a planar junction. The semiconductor device according to item . The thickness of the said 1st semiconductor layer is 30 micrometers or more, The semiconductor device as described in any one of Claims 1-9 characterized by the above-mentioned . The semiconductor device according to claim 1, wherein the second semiconductor layer is a semiconductor substrate, and the first semiconductor layer is an epitaxial layer formed on the semiconductor substrate .

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