JP2001077357A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which is excellent in performance such as operation loss, breakdown strength, and an EMC level and high in reliability. SOLUTION: A lightly doped n--type semiconductor layer 19 is provided between a p+-type semiconductor substrate 10 and an n+-type semiconductor layer 11 in a conventional PT-type IGBT structure, and furthermore a low life time layer 20 is provided inside the N--type semiconductor layer 19. By this structure, a depletion layer between the layer 19 and the substrate 10 gets wider, the device of this constitution can be improved on an ECM level as highly as a device of NPT type. As a parasitic PNP transistor is enlarged in base width, the device can be more enhanced in breakdown strength than a device of conventional PT type. The base layer of this device is much smaller in substantial thickness than that of a device of NPT-type and nearly equal to than of device of PT-type, and the low life time layer 20 is provided, so that a semiconductor device having a low ON-state voltage and a low tail current can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a power semiconductor device which requires low loss, high reliability and low noise.

[0002]

2. Description of the Related Art In a power device, a vertical power MOSFET using polysilicon as a gate electrode material is used.
With the advent of T, its properties have been remarkably improved. However, in order to increase the withstand voltage, the thickness of the depletion layer delay region required for the high withstand voltage design must be increased, and there is a serious disadvantage that the on-resistance increases. IGB
T has a structure that reduces the decrease in the on-voltage characteristics, and is promising as an ideal high-voltage transistor having the same voltage drive as the power MOSFET and high-speed switching characteristics, and is being actively researched. .

Conventionally, generally used IGBTs will first be described by taking a PT (Punch-Through) type as an example. FIG. 7 shows a PT type IGBT
FIG. An n ⁺ -type semiconductor layer 11 is provided as a buffer layer on the p ⁺ -type semiconductor substrate 10, and an n ⁻ -type semiconductor layer 12 is provided as a base layer on the n ⁺ -type semiconductor layer 11. The surface region in the n ⁻ type semiconductor layer 12 has p
^{A +} type impurity diffusion layer 13 is provided, and an n ⁺ type impurity diffusion layer 14 is provided as an emitter layer in the p ⁺ type impurity diffusion layer 13. And the gate insulating film 1
5. By providing the gate electrode 16, a MOSFET is formed in which the n ⁺ -type impurity diffusion layer 14 is a source region, the n ⁻ -type semiconductor layer 12 is a drain region, and the vicinity of the surface of the p ⁺ -type impurity diffusion layer 13 is a channel region. ing. Then, an insulating film 22 is provided so as to surround the gate electrode 16,
An emitter electrode 17 is provided on the main surface of the device,
The collector electrode 18 is provided on the back surface of
GBT is formed.

For example, a PT type IG with a withstand voltage of 1200 V
To give an example of the thickness and impurity concentration of each layer when designing a BT, the thickness of the p ⁺ type semiconductor substrate 10 is about 100 μm.
m, the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ , the thickness of the n ⁺ type semiconductor layer 11 is about 10 μm, and the impurity concentration is 5 × 10 ¹⁷
cm ⁻³ , the thickness of the n ⁻ type semiconductor layer 12 is about 110 μm,
The impurity concentration becomes about 5 × 10 ¹³ cm ⁻³ .

When a reverse bias is applied to the PT-type IGBT, that is, a depletion layer formed at a pn junction between the n ⁻ -type semiconductor layer 12 and the p ⁺ -type impurity diffusion layer 13 in the off state, the impurity concentration of both of them is reduced. Most of them are n
^- is formed in the type semiconductor layer 12. Even if the depletion layer spreads over the entire region of the n ⁻ type semiconductor layer 12, the expansion is suppressed by the n ⁺ type semiconductor layer 11 to which the impurity is added at a high concentration, so that the p ⁺ type impurity diffusion layer 13 and the p ⁺ type Punch through with the semiconductor substrate 10 can be avoided. Therefore, the n ⁻ type semiconductor layer 12 as the base layer can have a minimum necessary thickness for obtaining a withstand voltage. Thereby, when a forward bias is applied, that is, the voltage drop in the n ⁻ type semiconductor layer 12 in the ON state can be minimized, and a low ON voltage characteristic can be obtained. At the time of turn-off, n ⁻
Residual carriers remaining in the type semiconductor layer 12 are discharged by the depletion layer, so that the tail current can be reduced.
It can be said that the PT type IGBT has a structure excellent in low loss.

However, in this PT type IGBT, the
When the entire region of the source layer 12 is depleted, p⁺Type semiconductor base
Plate 10, n⁺Type semiconductor layer 11 and n⁻Type semiconductor layer 12, and
And p ⁺Of the pnp junction of the p-type impurity diffusion layer 13
The base region of a raw pnp transistor is substantially n⁺Type
Only the semiconductor layer 11 is provided, and this parasitic pnp transistor
Current amplification factor α_pnpLatch-up
It has the property of being inferior to the breakdown strength such as the withstand capacity and short-circuit strength.
ing. In addition, p having a high impurity concentration⁺Type semiconductor base
Plate 10 and n having the same high impurity concentration.⁺Type semiconductor
Since the layer 11 is joined, a depletion layer formed at these boundaries
Is narrow, the capacitance is large, and the collector-emitter voltage
Feedback capacitance C in the relatively low region of_res(= C_gc)But
Become larger, EMC (Electromagnetic Compatibilit
y: electromagnetic compatibility) level.

Next, NPT (Non-Punch-Th)
(rough) type IGBT will be described. FIG. 8 is a sectional view of the NPT type IGBT. As shown, the NPT type has a structure in which the n ⁺ type semiconductor layer 11 is removed from the above-described PT type structure.

Similar to the above-mentioned PT type, when designing an NPT type IGBT with a withstand voltage of 1200 V, an example of the film thickness and impurity concentration of each layer is as follows. The thickness of the p ⁺ type semiconductor substrate 10 depends on the substrate used and the lifetime control. In relation to
About 0.1 to 100 μm, impurity concentration is 10 ¹⁴ to 10
It is designed to be about ¹⁹ cm ⁻³ , the thickness of the n ⁻ type semiconductor layer 12 is about 170 μm, which is sufficiently thicker than that of the PT type, and the impurity concentration is about 7 × 10 ¹³ cm ⁻³ .

In the NPT type IGBT, since the n ⁻ type semiconductor layer 12 is sufficiently thick, the current amplification rate α _pnp of the parasitic pnp transistor in the off state is smaller than that of the PT type, and destruction such as latch-up resistance and short-circuit resistance is performed. Excellent withstand capacity. Further, since the depletion region generated at the pn junction between the p ⁺ type semiconductor substrate 10 and the n ⁻ type semiconductor layer 12 is relatively large, the capacitance is small and the EMC level is relatively good.

However, in the NPT type, since there is no layer that suppresses the expansion of the depletion layer, the n ⁻ type semiconductor layer 12 as the base layer needs to be made extra thicker than the film thickness required to obtain the breakdown voltage. In general, the ON voltage is higher than that of the PT type. Furthermore, since electrons that are not discharged by the depletion layer at the time of turn-off remain at the bottom of the base layer 12, holes are re-injected from the p ⁺ -type semiconductor substrate 10, and these become tail currents, resulting in a large loss. .

As described above, conventionally, a PT type IGBT excellent in on-voltage and turn-off loss and an NPT type IGBT excellent in breakdown strength and EMC level have been selectively used according to required characteristics. . In order to achieve both advantages, studies have been made on miniaturization, trenching, local lifetime control, and the like in each structure, but they have not been realized yet.

[0012]

As described with reference to an IGBT as an example, a conventional semiconductor device, particularly a high breakdown voltage type semiconductor device, has a structure in which the on-voltage and the turn-off loss are excellent, the breakdown strength and the EMC level are deteriorated. And conversely,
A structure having an excellent EMC level has a problem that the on-voltage and the turn-off loss are inferior.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-performance and highly-reliable semiconductor device which is excellent in loss, breakdown strength and EMC level.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type and a high impurity concentration.
A semiconductor region, and the first semiconductor region,
A second semiconductor region of a second conductivity type with a low impurity concentration, a third semiconductor region of a second conductivity type with a high impurity concentration provided on the second semiconductor region, and a third semiconductor region of a second conductivity type with a high impurity concentration; A fourth semiconductor region of a second conductivity type and a low impurity concentration, and a fifth semiconductor of a first conductivity type and a high impurity concentration provided in a part of a surface region in the fourth semiconductor region. And the first semiconductor region functions as a collector region, and the third semiconductor region is formed by joining the fourth semiconductor region and the fifth semiconductor region to form the fourth semiconductor region. The semiconductor device is characterized in that it functions as a buffer layer that suppresses expansion of a depletion layer formed in the region, and that the fourth and fifth semiconductor regions function as base regions.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device is interposed between the first semiconductor region and the second semiconductor region and has a first conductivity type and a low impurity concentration. A sixth semiconductor region is further provided.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the second semiconductor region includes a low carrier lifetime layer.

According to a fourth aspect, in the semiconductor device according to any one of the first to third aspects, the third semiconductor region is provided with a low carrier lifetime layer.

According to a fifth aspect of the present invention, there is provided a semiconductor device, comprising: a first semiconductor region having a first conductivity type and a low impurity concentration; and a first semiconductor region provided on the first semiconductor region and having a second conductivity type. A second semiconductor region having a low impurity concentration, and a third semiconductor region provided on the second semiconductor region and having a second conductivity type and a high impurity concentration.
A semiconductor region, and a third semiconductor region,
A fourth semiconductor region of a second conductivity type having a low impurity concentration and a part of a surface region in the fourth semiconductor region;
A fifth semiconductor region having a conductivity type and a high impurity concentration;
The first semiconductor region functions as a collector region, and the third semiconductor region is formed in the fourth semiconductor region by joining the fourth semiconductor region and the fifth semiconductor region. The semiconductor device is characterized in that it functions as a buffer layer that suppresses expansion of a depletion layer, and that the fourth and fifth semiconductor regions function as base regions.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the first semiconductor region is 1 μm.
m or less.

Further, as described in claim 7, in the semiconductor device according to any one of claims 1 to 6, the fourth semiconductor region is partially formed in a surface region in the fifth semiconductor region. A second conductivity type impurity diffusion layer provided in isolation with the gate insulating film provided on at least a surface of the fifth semiconductor region between the fourth semiconductor region and the impurity diffusion layer; A gate electrode provided on the gate insulating film, wherein the impurity diffusion layer is a source region;
A MOS transistor having a surface region of the fifth semiconductor region between the fourth semiconductor region and the impurity diffusion layer as a channel region and a drain region as the fourth semiconductor region is formed. .

According to the first aspect, when a reverse bias is applied between the fourth semiconductor region and the fifth semiconductor region, the depletion layer formed in the fourth semiconductor region expands. Can be stopped by the third semiconductor region (buffer layer), so that punch-through between the fourth semiconductor region and the fifth semiconductor region can be avoided, and the thickness of the base layer can be reduced with a withstand voltage. Can be minimized. As a result, a voltage drop in the base layer when a forward bias is applied can be minimized, and a low on-voltage operation can be performed. Also, the second
By providing the semiconductor region described above, the thickness of the base layer is substantially increased, and the breakdown strength can be improved. Furthermore, since the second semiconductor region has a low impurity concentration, the width of the depletion layer formed between the second semiconductor region and the first semiconductor region (collector region) is increased, so that the capacitance is reduced and the EMC level can be improved. I can do it.

According to a second aspect of the present invention, by providing the sixth semiconductor region having a low impurity concentration on the collector region,
The width of the depletion layer with the second semiconductor region having a low impurity concentration can be further increased, and the EMC level can be improved.

According to the third and fourth aspects of the present invention, by providing a low lifetime layer in the second semiconductor region, the third semiconductor region, or these two layers, the tail current at the time of turning off the semiconductor device is reduced. I can do it.

According to the fifth aspect, when a reverse bias is applied between the fourth semiconductor region and the fifth semiconductor region, the depletion layer formed in the fourth semiconductor region. Can be stopped by the third semiconductor region (buffer layer), which is a buffer layer, so that punch-through between the fourth semiconductor region and the fifth semiconductor region can be avoided, and the thickness of the base layer can be reduced. Can be minimized to obtain a withstand voltage. As a result, a voltage drop in the base layer when a forward bias is applied can be minimized, and a low on-voltage operation can be performed. In addition, by providing the second semiconductor region, the thickness of the base layer is substantially increased, and the breakdown strength can be improved. Furthermore, since the second semiconductor region has a low impurity concentration, the width of a depletion layer formed between the second semiconductor region and the first semiconductor region (collector region) is increased, so that the capacitance is reduced.
C level can be improved. And, by lowering the impurity concentration of the collector region, injection of carriers from the collector region can be suppressed, and the tail current at the time of turning off the semiconductor device can be reduced.

By reducing the thickness of the collector region to 1 μm or less, the injection of carriers from the collector region can be suppressed and the tail current at the time of turning off the semiconductor device can be reduced. I can do it.

As described in claim 7, the present invention can be applied to an IGBT by forming a MOS transistor in the fifth semiconductor region.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

FIGS. 1A and 1B are views for explaining a semiconductor device according to a first embodiment of the present invention. FIG.
A cross-sectional view of the BT, and (b) is a plan view (stripe pattern) corresponding to line AA ′ in (a). This structure is a conventional PT type IGBT in which an n ⁻ -type semiconductor layer 19 to which an impurity is added at a low concentration is interposed between a p ⁺ -type semiconductor substrate 10 and an n ⁺ -type semiconductor layer 11.

That is, p⁺N on the type semiconductor substrate 10
⁻Type semiconductor layer 19 is provided.⁻Type semiconductor layer 19
N on⁺Type semiconductor layer 11 is provided as a buffer layer,
On this buffer layer 11, n⁻Type semiconductor layer 12 is a base layer
It is provided as. Surface area in this base layer 12
Has p⁺Type impurity diffusion layer 13 is provided.
⁺N-type impurity diffusion layer 13 has n⁺Type
An impurity diffusion layer 14 is provided. And the gate
By providing the edge film 15 and the gate electrode 16, n ⁺Mold impurity
The material diffusion layer 14 as a source region, n⁻Drain the semiconductor layer 12
In region, p⁺Channel near the surface of the impurity diffusion layer 13
A MOSFET is formed as a control region. And
An insulating film 22 is provided so as to surround the gate electrode 16.
And an emitter electrode 17 is provided on the main surface of the device.
A collector electrode 18 is provided on the back of the plate 10.
Thus, the IGBT is formed.

According to this embodiment, an IGBT with a withstand voltage of 1200 V is used.
Examples of the film thickness and impurity concentration of each layer when designing the p ⁺ type semiconductor substrate 10, n ⁺ type semiconductor layer 11, n ^+
- the design value type semiconductor layer 12 is conventional PT type IGBT
That is, each layer has a thickness of about 100 μm.
m, 10 μm, and 110 μm, and the impurity concentration is 1
0 ¹⁹ cm ⁻³ , 5 × 10 ¹⁷ cm ⁻³ , 5 × 10 ¹³
cm ⁻³ . Then, the p ⁺ type semiconductor substrate 10 and n ⁺
The thickness of the n ⁻ type semiconductor layer 19 provided between the type semiconductor layers 11 is about 10 μm, and may be smaller than about 10 μm. The impurity concentration is designed at a value of about 7 × 10 ¹³ cm ⁻³ .

According to this structure, the p ⁺ type semiconductor substrate 10
By providing the n ⁻ type semiconductor layer 19 between the n ⁺ type semiconductor layer 11 and the n ⁺ type semiconductor layer 11, the depletion layer generated between the n ⁻ type semiconductor layer 19 and the p ⁺ type semiconductor substrate 10 is wide, and the capacitance is , The EMC level can be improved to the level of the NPT type.

In order to increase the base width of the parasitic pnp transistor by the amount of the n ⁻ type semiconductor layer 19,
The current amplification factor of the parasitic transistor is reduced, and the breakdown strength such as the latch-up withstand capacity and the short-circuit withstand capacity can be improved as compared with the conventional PT type.

Further, since the thickness of the base layer of the parasitic pnp transistor is sufficiently thinner than that of the NPT type and is comparable to that of the PT, the low on-voltage characteristic which is an advantage of the PT type can be maintained.

In order to further increase the breakdown strength, this n ⁻
Can be dealt with by increasing the thickness of the semiconductor layer 19,
If the film thickness is too large, the base layer of the parasitic pnp transistor becomes large, which may lead to deterioration of the low on-voltage characteristic which is an advantage of the PT type. It is important to design the thickness of the n ⁻ type semiconductor layer.

Of course, an n ⁺ -type semiconductor layer to which an impurity is added at a high concentration may be formed in the n ⁻ -type semiconductor layer 12 in the NPT type structure.

In the IGBT of this structure having a withstand voltage of 1200 V, an example of the film thickness and impurity concentration of each layer is as follows.
Each film thickness of the ⁺ type semiconductor substrate 10, the n ⁻ type semiconductor layer 19, the n ⁺ type semiconductor layer 11, and the n ⁻ type semiconductor layer 12 is about 0.1 to 100 μm, about 100 μm or less, respectively.
In the range of about 10 μm or less and about 100 to 200 μm, the impurity concentration is also 10 ¹⁴ to 10 ¹⁹ c, respectively.
m ⁻³ , 7 × 10 ¹³ cm ⁻³ , 5 × 10 ¹⁷ c
m ⁻³ , designed to be about 7 × 10 ¹³ cm ⁻³ .

In this case, the base width of the parasitic pnp transistor (n ⁻ type semiconductor layer 12, n ⁺ type semiconductor layer 11, n ⁻
The sum of the film thicknesses of the semiconductor layer 19 does not change.
In addition to the n ⁻ type semiconductor layer 19, the design of the film thickness and the impurity concentration becomes more important for each of the other layers, but the thickness of the n ⁻ type semiconductor layer 12 can be designed to be smaller than that of the conventional NPT type. Therefore, an IGBT excellent in low on-voltage characteristics as compared with the conventional NPT type can be realized.

However, if anything, NPT type I
It is more preferable to apply this structure to the PT type than to apply this structure to the GBT, and it can be said that this is a desirable structure.

FIG. 2 shows, as a modification, an IGBT having the structure shown in FIG.
FIG. This structure is such that a low lifetime layer 20 is provided in the n ⁻ type semiconductor layer 19 in the structure of FIG.

Proton irradiation into type semiconductor layer 19, n ^{- -} [0040] The low lifetime layer 20 is n -type semiconductor layer 19
This is performed so that a crystal defect is formed only in a part of the region. This step may be performed by an electron beam. However, in this case, a defect may be formed in the entire semiconductor layer.

The low lifetime layer 20 is n as shown in FIG. 2 ^- is not limited to the form type semiconductor layer 19 may be formed on the n ⁺ -type semiconductor layer 11, n ^- -type semiconductor layer 19, n
It may be formed on both of the ⁺ type semiconductor layers 11.

As described above, if the low lifetime layer 20 is further provided, the lifetime of the holes injected from the p ⁺ type semiconductor substrate 10 can be shortened. We can prepare.

FIG. 3 shows a MOS on the surface of a trench type IGBT.
3A shows a transistor region, and FIG.
(B) is a plan view (stripe pattern) corresponding to line AA ′ in (a). Trench type IGBT
MOS transistor region on the surface of n ^- type semiconductor layer 1
2 and the n ^- along the p ⁺ -type impurity trench inner wall formed in the diffusion layer 13 on the type semiconductor layer 12 is formed with a gate insulating film 15 over a part of the p ⁺ -type impurity diffusion layer 14 A gate electrode 16 is formed on gate insulating film 15 so as to fill the trench. Then, an insulating film 22 is formed on the gate electrode 16 and on the gate insulating film 15 on the p ⁺ -type impurity diffusion layer 14, and a surface electrode as the emitter electrode 17 is formed over the entire device.

The structure of this embodiment can be applied not only to the planar IGBT described above but also to this trench IGBT as another modified example, and similar effects can be obtained.

According to the above configuration, the conventional PT
In the structure of the ip IGBT, p⁺Type semiconductor substrate and n⁺
N between the semiconductor layers⁻By providing a mold semiconductor layer,
Improve EMC level to NPT type IGBT
Can be done. In addition, the base layer of the parasitic pnp transistor
Increased film thickness reduces current amplification and increases breakdown strength
And the thickness of the base layer is smaller than that of the NPT type.
Low on-voltage characteristics comparable to PT-type IGBTs
Can also be maintained at the same time. Furthermore, this n ⁻Mold semiconductive
If a low lifetime layer is provided in the body layer,
, Loss, breakdown strength, and EM
The C level and the advantages of the NPT type despite the PT type
It is possible to realize an excellent IGBT. Also,
Even in NPT type IGBT, n⁻Type semiconductor layer
n⁺Similar effects can be obtained by providing a mold semiconductor layer.
I can do it.

FIG. 4 is a schematic view showing a half of the second embodiment of the present invention.
This is for explaining the conductor device, and is used to cut the IGBT.
FIG. This structure is similar to the structure of the first embodiment.
P ⁺Type semiconductor substrate 10 and n⁻Between the semiconductor layer 19
And p with a low concentration of impurities⁻Type semiconductor layer 21
It is provided in.

IGB with a withstand voltage of 1200 V in this structure
The design of T may be the same as that of the first embodiment regardless of whether it is applied to the PT type or the NPT type. However, for the p ⁻ type semiconductor layer 21, for example, the film thickness is 10 μm and the impurity concentration is 10 μm. Is designed to be about 7 × 10 ¹³ cm ⁻³ .

According to the present embodiment, a high breakdown voltage and a low on-state voltage can be realized at the same time as in the first embodiment, and there is no pn junction formed by a layer doped with a high concentration of impurities. EMC level can be improved more than NPT type.

FIG. 5 is a cross-sectional view of a IGBT in which a low lifetime layer is further provided on the IGBT having the structure of FIG. 4 as a modification. In this structure, a low lifetime layer 20 is provided in the n ⁻ type semiconductor layer 19 in the structure of FIG.

As in the first embodiment, the low lifetime layer is not the n ⁻ type semiconductor layer 19 as shown in FIG.
may be formed on the n ⁺ -type semiconductor layer 11, n ^- -type semiconductor layer 19, ^{n +} -type semiconductor layer 11 may be formed on both.

If the low lifetime layer is further provided as described above, the life of holes injected from the p ⁻ type semiconductor substrate can be shortened, so that a low tail current characteristic which is an advantage of the PT type is provided. Can be done.

According to this embodiment, the same effects as those of the first embodiment can be obtained, and the EMC level can be improved as compared with the structure according to the first embodiment.

As a matter of course, the structure of the present embodiment can be applied to a trench type IGBT as another modification as in the first embodiment.

FIG. 6 is a sectional view of an IGBT for describing a semiconductor device according to a third embodiment of the present invention. This structure has a structure in which the thickness of the lowermost p ⁺ -type region in the structure of the first embodiment is reduced and the impurity concentration is reduced.

That is, the p ⁺ -type impurity diffusion layer 13 is provided in the surface region of the n ⁻ -type semiconductor substrate 23, and the n ⁺ -type impurity diffusion layer 14 is provided in the p ⁺ -type impurity diffusion layer 13 as an emitter layer. ing. And the gate insulating film 1
5. By providing the gate electrode 16, a MOSFET is formed in which the n ⁺ -type impurity diffusion layer 14 is a source region, the n ⁻ -type semiconductor layer 12 is a drain region, and the vicinity of the surface of the p ⁺ -type impurity diffusion layer 13 is a channel region. ing. Then, an insulating film 22 is formed so as to surround the gate electrode 16,
An emitter electrode 17 is provided on the main surface of the device. Further, an n ⁺ type semiconductor layer 11 as a buffer layer is provided on the back surface of the n ⁻ type semiconductor substrate 23 by impurity diffusion, and an n ⁻ type semiconductor layer 19 is provided on the back surface of the n ⁺ type semiconductor layer 11. I have. Further on the back surface of the n ⁻ type semiconductor layer 19,
A p ⁻ type semiconductor layer 24 is provided as a collector layer, and an IGBT is formed by providing a collector electrode 18 on the back surface of the p ⁻ type semiconductor layer 24.

IGB with a withstand voltage of 1200 V in this structure
T designs also, PT type, the NPT type both but may under the same conditions as in the first embodiment, p ^- -type semiconductor layer 2
4 has a film thickness of 1 μm or less and an impurity concentration of 1 ×
It is designed to be about 10 ¹⁷ cm ⁻³ .

According to this embodiment, in addition to the advantages of the structure of FIG. 1 described in the first embodiment, the p ^- type semiconductor layer corresponding to the collector layer of the first embodiment has a small thickness. Further, since the impurity concentration is low, injection of holes into the n ⁻ -type semiconductor layer can be suppressed low. Thereby, low tail current characteristics can be obtained by the low lifetime layer without requiring carrier lifetime control.

As a matter of course, the structure of the present embodiment can be applied to a trench type IGBT as a modification, similarly to the first embodiment.

According to the first to third embodiments as described above, in the NPT type and the PT type IGBT,
It is possible to realize an excellent IGBT having both advantages of loss, breakdown strength, and EMC level. Further, the structure of the present invention is not limited to the IGBT, but can be applied to other semiconductor devices, in particular, a high breakdown voltage type semiconductor element, and can provide a high-performance and highly reliable semiconductor device. Of course, the values of the film thickness and the impurity concentration mentioned in the present embodiment are variously changed depending on the design of a desired withstand voltage, on-voltage and the like, and are appropriately modified without departing from the gist of the present invention. I can do it.

[0060]

As described above, according to the present invention, it is possible to provide a high-performance and high-reliability semiconductor device which is excellent in terms of loss, breakdown strength and EMC level.

[Brief description of the drawings]

FIGS. 1A and 1B are views for explaining a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view of an IGBT, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. The corresponding plan view.

FIG. 2 is a sectional view of an IGBT provided with a low lifetime layer for describing a modification of the semiconductor device according to the first embodiment of the present invention;

FIGS. 3A and 3B are views for explaining another modification example of the semiconductor device according to the first embodiment of the present invention, in which FIG. 3A is a cross-sectional view of a surface MOS transistor region of a trench IGBT, and FIG. (A) The top view corresponding to the AA 'line in a figure.

FIG. 4 is a cross-sectional view of an IGBT for describing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of an IGBT provided with a low lifetime layer for describing a modification of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view of an IGBT for describing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view of a PT type IGBT for describing a conventional semiconductor device.

FIG. 8 is a cross-sectional view of an NPT type IGBT for describing a conventional semiconductor device.

[Explanation of symbols]

10 ... p ⁺ type semiconductor substrate (first semiconductor region) 11 ... n ⁺ type semiconductor layer (third semiconductor region) 12 ... n ⁻ type semiconductor layer (fourth semiconductor region) 13 ... p ⁺ type impurity diffusion layer (Fifth semiconductor region) 14 n ⁺ type impurity diffusion layer 15 gate insulating film 16 gate electrode 17 emitter electrode 18 collector electrode 19 n ^- type semiconductor layer (second semiconductor region) 20 low carrier Lifetime layer 21 p ^- type semiconductor layer (sixth semiconductor region) 22 insulating film 23 n ^- type semiconductor substrate (fourth semiconductor region) 24 p ^- type semiconductor layer (first semiconductor region)

Claims (7)

[Claims] A first semiconductor region having a first conductivity type and a high impurity concentration; a second semiconductor region provided on the first semiconductor region and having a second conductivity type and a low impurity concentration; A third semiconductor region provided on the second semiconductor region and having a second conductivity type and a high impurity concentration; and a fourth semiconductor region provided on the third semiconductor region and having a second conductivity type and a low impurity concentration. A portion of the surface region in the fourth semiconductor region;
A fifth semiconductor region having a first conductivity type and a high impurity concentration, wherein the first semiconductor region functions as a collector region, and the third semiconductor region includes the fourth semiconductor region and the fifth semiconductor region. The semiconductor region functions as a buffer layer that suppresses expansion of a depletion layer formed in the fourth semiconductor region, and the fourth and fifth semiconductor regions function as base regions. Semiconductor device. 2. The semiconductor device according to claim 1, further comprising a sixth semiconductor region having a first conductivity type and a low impurity concentration, interposed between said first semiconductor region and said second semiconductor region. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the second semiconductor region includes a low carrier lifetime layer. 4. The semiconductor device according to claim 1, wherein the third semiconductor region includes a low carrier lifetime layer.
The semiconductor device according to claim 1. 5. A first semiconductor region having a first conductivity type and a low impurity concentration; a second semiconductor region provided on the first semiconductor region and having a second conductivity type and a low impurity concentration; A third semiconductor region provided on the second semiconductor region and having a second conductivity type and a high impurity concentration; and a fourth semiconductor region provided on the third semiconductor region and having a second conductivity type and a low impurity concentration. A portion of the surface region in the fourth semiconductor region;
A fifth semiconductor region having a first conductivity type and a high impurity concentration, wherein the first semiconductor region functions as a collector region, and the third semiconductor region includes the fourth semiconductor region and the fifth semiconductor region. The semiconductor region functions as a buffer layer that suppresses expansion of a depletion layer formed in the fourth semiconductor region, and the fourth and fifth semiconductor regions function as base regions. Semiconductor device. 6. The semiconductor device according to claim 5, wherein said first semiconductor region has a thickness of 1 μm or less. 7. A second semiconductor device provided in a part of a surface region in the fifth semiconductor region and separated from the fourth semiconductor region.
A conductive type impurity diffusion layer; a gate insulating film provided on at least a surface of the fifth semiconductor region between the fourth semiconductor region and the impurity diffusion layer; and a gate insulating film provided on the gate insulating film. A gate electrode, wherein the impurity diffusion layer is a source region, a surface region of the fifth semiconductor region between the fourth semiconductor region and the impurity diffusion layer is a channel region, and the fourth semiconductor region is a drain. 7. The semiconductor device according to claim 1, wherein a MOS transistor as a region is formed.