CN109904225A - A kind of high reliability IGBT and its manufacturing method - Google Patents
A kind of high reliability IGBT and its manufacturing method Download PDFInfo
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- CN109904225A CN109904225A CN201910248514.1A CN201910248514A CN109904225A CN 109904225 A CN109904225 A CN 109904225A CN 201910248514 A CN201910248514 A CN 201910248514A CN 109904225 A CN109904225 A CN 109904225A
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Abstract
The present invention relates to semiconductor technology, in particular to a kind of high reliability IGBT and its manufacturing method.Major programme of the invention is improved to the collector structure at the conventional back side FS-IGBT, one layer of lightly doped n type layer is introduced between the N+ buffer layer and the collector area P+ of conventional FS-IGBT, forms the collector area P+-N- layers-N+ buffer layer collector sandwich structure.Due to the presence of lightly doped n type layer so that in the present invention internal PNP transistor common-base current gain αPNPIt is smaller, so whether leakage current of the device under forward blocking mode is all significantly reduced under room temperature or hot environment.Especially in an environment of high temperature, the leakage current for reducing device helps to improve the reliability of device.Meanwhile the forward conduction characteristic and turn-off characteristic of device are suitable with conventional FS-IGBT.
Description
Technical field
The present invention relates to semiconductor technology, in particular to a kind of high reliability IGBT and its manufacturing method.
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, referred to as: IGBT), because
The device had both had the small feature of driving power of MOSFET element, but also with BJT device electric current is big, conductivity modulation effect band
The advantages such as conduction voltage drop is small come, are widely used in the various aspects of mesohigh field of power electronics, this is a kind of normally-off device
Part, structure is simple, manufacturing process mature and reliable.
In the parameters of IGBT, IGBT collector leakage stream this can be used for reflecting the forward blocking energy of IGBT
Power, usual collector leakage stream is smaller closer to ideal off state, so block performance better, especially when device is applied
When in hot environment, the size of leakage current directly affects the reliability of device.This is because semiconductor power device is to temperature
Degree is very sensitive, and with the rising of temperature, the warm-up movement of carrier aggravates, and high-power IGBT device bears external high blocking voltage
When, the Joule heat that the increase of collector leakage stream generates be can not ignore, if the heat generated cannot be spread out of in time, will lead to knot
Temperature increases, and collector leakage stream can increase with the raising of junction temperature, forms thermoelectric positive feedback, thermal breakdown eventually occurs
Failure.Therefore, in applying in a high temperauture environment, the more enough reliabilities for effectively improving device of collector leakage stream of IGBT are reduced
Summary of the invention
The purpose of the present invention proposes a kind of with low drain aiming at the larger phenomenon of current routine FS-IGBT leakage current
The high reliability IGBT and its manufacturing method of electric current.
To achieve the above object, the present invention adopts the following technical scheme:
A kind of high reliability IGBT, as shown in Fig. 2, including collector structure, drift region structure, emitter structure and plane
Grid structure；The collector structure includes the collector area P+ 10 and the metallization collector positioned at 10 lower surface of the collector area P+
11；The drift region structure includes N- layer 9 and the N+ buffer layer 8 positioned at 9 upper surface of N- layer, and is located at table on N+ buffer layer 8
The N- drift region layer 1 in face, the N- layer 9 are located at the upper surface of the collector area P+ 10；The emitter structure is located at the drift region N-
The side on 1 upper layer of layer, emitter include p-type base area 3, the contact zone P+ 2, N+ emitter region 7 and metallization emitter 4；The p-type base
The side at the top of the drift region N- is arranged in area 3, and the N+ emitter region 7 is located in p-type base area 3；The contact zone P+ 2 and p-type base
Area 3 connects, and connect with N+ emitter region 7；The contact zone P+ 2 and N+ emitter region 7 are located at device cellular upper surface side by side；The metal
Change the upper surface that emitter 4 is located at the contact zone P+ 2 and N+ emitter region 7, metallize the only covering part N+ emitter region 7 of emitter 4；Institute
State the other side that planar gate structure is located at N- drift 1 upper layer of region layer, including gate oxide 6 and polygate electrodes 5；The grid oxygen
Change the side that layer 6 is located at 1 top of N- drift region layer, the polygate electrodes 5 are located at the top of gate oxide 6.
Major programme of the invention relates generally to backside collector structure, in the N+ buffer layer 8 and P of conventional FS-IGBT
One layer of lightly doped n type layer 9 is introduced between+collector area 10, so that reducing on the basis of not influencing device forward conduction characteristic
Leakage current of the device under forward blocking mode, improves the reliability of device.
The part high reliability IGBT provided by the invention, MOS may be configured as plane grid or groove-shaped grid.
The invention also provides the manufacturing methods of two kinds of reliability IGBT:
The manufacturing method of the first IGBT, by epitaxy technique formed N- layer 9 method the following steps are included:
Step 1: choosing boron doping concentration is 1e17cm-3P-type wafer as substrate, pass through extension on silicon substrate
Growth forms N- layer 9, and thickness is about 2~3um；
Step 2: using two step epitaxy techniques, it is then slow in N+ first in 9 upper surface epitaxial growth N+ buffer layer 8 of N- layer
It rushes 8 upper surface of layer and passes through the drift region epitaxial growth N- 1；
Step 3: one end in 1 upper surface of the drift region N- generates gate oxide 6 by hot oxygen, form sediment on 6 surface of gate oxide
Product polysilicon etches to form gate electrode 5 again；
Step 4: the other end injecting p-type impurity and knot in 1 upper surface of N-type semiconductor drift region form p-type base area 3；
Step 5: injecting N-type impurity in p-type base area 3 forms N+ emitter region 7；
Step 6: injecting p-type impurity and the knot formation contact zone P+ 2 in p-type base area 3；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal forming 7 upper surface of N+ emitter region, cathodic metal 4 is formed；Cathodic metal 4 covers simultaneously
On the contact zone P+ 2；
Step 9: deposit passivation layer；
Step 10: backing substrate is thinned；
Step 11: back metal, forms metallization collector 11 in 10 bottom of the collector area P+.
Second of reliability IGBT manufacturing method carries out impurity compensation by ion implanting and diffusion technique to form N- layers
9 method the following steps are included:
Step 1: choosing doping concentration is 5e13cm-3N-type silicon chip as silicon substrate, i.e. N-type semiconductor in structure
Drift region 1 passes through phosphonium ion injection and knot formation N+ buffer layer 8 at 1 back side of the drift region N- first；
Step 2: 8 surface of N+ buffer layer inject boron ion after be diffused technique again, to part N+ buffer layer 8 into
Row impurity compensation forms N- layer 9；
Step 3: one end in 1 upper surface of N-type semiconductor drift region generates gate oxide 6 by hot oxygen, in gate oxide
6 surface deposition polysilicons etch to form gate electrode 5 again；
Step 4: the other end injecting p-type impurity and knot in 1 upper surface of N-type semiconductor drift region form p-type base area 3；
Step 5: injecting N-type impurity in p-type base area 3 forms N+ emitter region 7；
Step 6: injecting p-type impurity and the knot formation contact zone P+ 2 in p-type base area 3；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal forming 7 upper surface of N+ emitter region, cathodic metal 4 is formed；Cathodic metal 4 covers simultaneously
On the contact zone P+ 2；
Step 9: deposit passivation layer；
Step 10: to injecting p-type impurity in back portion N- layer 9 and carrying out ion-activated, the formation collector area P+ 10；
Step 11: back metal, forms metallization collector 11 in 10 lower surface of the collector area P+.
Above two scheme be gate structure be plane grid when device architecture.
The total technical solution of the present invention, mainly there is at 3 points, first is that the collector structure of routine FS-IGBT shown in FIG. 1
It improves, as described in manufacturing method 1, N- layer 9, N+ buffer layer 8 and the drift region N- 1 is formed by three step epitaxy technique,
After organic semiconductor device, the collector sandwich structure of 10-N- layer 9-N+ buffer layer 8 in the collector area P+ as shown in Figure 2 is formed.Two
It is as described in manufacturing method 2, at 1 back side of the drift region N-, by phosphonium ion injection, simultaneously knot forms N+ buffer layer 8 first, with
Afterwards to spreading after injecting boron ion in N+ buffer layer 8, N- layer 9 is formed by impurity compensation, after the completion of positive technique, finally by
Boron ion is injected to form the collector area P+ 10, obtains the collector sandwich knot of 9-N+ buffer layer 8 of the collector area P+ 10-N- layer
Structure.Third is that the part high reliability IGBT provided by the invention, MOS may be configured as plane grid or groove-shaped grid.
Beneficial effects of the present invention are to propose a kind of high reliability IGBT and its manufacturing method, reduce the electric leakage of device
Stream, improves the reliability of device.
Detailed description of the invention
Fig. 1 is conventional plane grid-type FS-IGBT structure cell schematic diagram；
Fig. 2 is high reliability plane grid-type IGBT structure cell schematic diagram of the invention；
Fig. 3 is conventional groove gate type FS-IGBT structure cell schematic diagram；
Fig. 4 is high reliability trench gate IGBT structure cell schematic diagram of the invention；
Fig. 5 is the forward conduction characteristic curve schematic diagram of conventional FS-IGBT He high reliability IGBT of the present invention；
Fig. 6 is conventional FS-IGBT and electric leakage of the high reliability IGBT of the present invention under forward blocking mode under room temperature
Stream；
Under the conditions of Fig. 7 is high temperature (100 DEG C), conventional FS-IGBT and high reliability IGBT of the present invention are in forward blocking mode
Under leakage current；
Fig. 8 is that under room temperature, conventional FS-IGBT and device creepage of the present invention are with lightly doped n type layer thickness variation
Curve；
Under the conditions of Fig. 9 is high temperature (100 DEG C), conventional FS-IGBT and device creepage of the present invention are with lightly doped n type thickness degree
The curve of variation；
Figure 10 is that under room temperature, conventional FS-IGBT and device forward blocking voltage of the present invention are adulterated with lightly doped n type layer
The curve of concentration variation；
Figure 11 be forward blocking voltage be 800V when, the field distribution of conventional FS-IGBT and high reliability IGBT of the present invention
Schematic diagram；
Figure 12 is the artificial circuit figure of IGBT turn-off characteristic and obtained turn-off characteristic curve under mixed load mode；
Figure 13 is the process flow chart of manufacturing method 1；
Figure 14 is the process flow chart of manufacturing method 2.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing
A kind of high reliability IGBT proposed by the present invention, structure chart such as Fig. 2, including collector structure, drift region structure,
Emitter structure and planar gate structure；The collector structure include the collector area P+ 10 and be located at 10 lower surface of the collector area P+
Metallization collector 11；The drift region structure includes N- layer 9 and the N+ buffer layer 8 positioned at 9 upper surface of N- layer, and is located at
The N- drift region layer 1 of 8 upper surface of N+ buffer layer, the N- layer 9 are located at the upper surface of the collector area P+ 10；The emitter structure
Positioned at the side on the upper layer of N- drift region layer 1, emitter includes p-type base area 3, the contact zone P+ 2, N+ emitter region 7 and metallization hair
Emitter-base bandgap grading 4；The side at the top of the drift region N- is arranged in the p-type base area 3, and the N+ emitter region 7 is located in p-type base area 3；The P+
Contact zone 2 is connect with p-type base area 3, and is connect with N+ emitter region 7；The contact zone P+ 2 and N+ emitter region 7 are located at device cellular side by side
Upper surface；The metallization emitter 4 is located at the upper surface of the contact zone P+ 2 and N+ emitter region 7, and metallization emitter 4 only covers
The part contact zone P+ 2；The planar gate structure is located at the other side of N- drift region layer 1, including gate oxide 6 and polysilicon gate electricity
Pole 5；The gate oxide 6 is located at the side at 1 top of N- drift region layer, and the polygate electrodes 5 are located at the top of gate oxide 6
Portion.
The part a kind of high reliability IGBT proposed by the present invention, MOS may be configured as plane grid or groove-shaped grid, have
The high reliability IGBT structure cell of plane grid is as shown in Fig. 2, have the high reliability IGBT structure cell of groove-shaped grid such as
Shown in Fig. 4.
High reliability IGBT provided by the invention, its working principles are as follows:
In structure cell as shown in Figure 2, when gate electrode 5 plus positive potential, electronics just accumulates under the gate, and channel occurs
Transoid forms the N-type electron channel of connection N+ emitter region 7 and N- drift region layer 1, and on collector 11 plus positive pressure, emitter 4 add
Zero potential.Electronic current flows into N- drift region layer 1 from N+ emitter region 7 by N-type electron channel, is the p-type base area drift region 3-N-
The PNP transistor that the 1-collector area P+ 10 of layer is constituted provides ideal base drive current, after PNP transistor is opened, N+ emitter region 7
A large amount of hole is injected into N- drift region layer 1, conductivity modulation effect makes device have lower conduction voltage drop.Device is positive
Forward conduction voltage drop when conducting is suitable with conventional FS-IGBT, as shown in Figure 5.
When adding positive pressure on collector 11, when emitter 4 and gate electrode 5 are shorted, IGBT works under forward blocking mode, collection
Electrode voltage is supported by the PN junction between the collector area P+ 10 and N- drift region layer 1.The collector area P+ 10 of reverse bias and N-
The space charge at PN junction between drift region layer 1, which generates electric current, to be amplified by the gain of internal PNP transistor, which is
The leakage current of device, the size of leakage current depend on the gain that space charge generates current density and internal PNP transistor.Normal
In the FS-IGBT of rule and high reliability IGBT provided by the invention, when collector voltage is identical, depletion region it is of same size, because
It is identical that this space charge generates current density.Fig. 6 is shown under room temperature, conventional FS-IGBT and provided by the invention highly reliable
Leakage current of the property IGBT under forward blocking mode, when forward blocking voltage is identical, in high reliability IGBT provided by the invention
Leakage current is smaller, this is because there are one layer of N- layers 9 between the collector area P+ 10 and N+ buffer layer 8 in the present invention, so that this hair
The common-base current gain α of bright middle internal PNP transistorPNPIn contain the base transport factor of a N- layer less than 1, therefore
And in the present invention internal PNP transistor common-base current gain αPNPLess than PNP transistor internal in conventional FS-IGBT
Common-base current gain αPNP, therefore in the identical situation of forward blocking voltage, the present invention has lower leakage current.With
Collector voltage increases, common-base current gain αPNPIncrease, breakdown, which occurs, for device need to meet αPNP1 is leveled off to, due to the present invention
αPNPSmaller therefore of the invention breakdown voltage is higher, as shown in Figure 8.
High reliability IGBT provided by the invention, by taking plane grid structure cell shown in Fig. 2 as an example.
Manufacturing method 1 forms N- layer 9 by epitaxy technique, and manufacturing step is as follows:
Step 1: choosing boron doping concentration is 1e17cm-3P-type wafer as substrate, pass through extension on silicon substrate
Growth forms N- layer 9, and thickness is about 2~3um；
Step 2: using two step epitaxy techniques, it is then slow in N+ first in 9 upper surface epitaxial growth N+ buffer layer 8 of N- layer
It rushes 8 upper surface of layer and passes through the drift region epitaxial growth N- 1；
Step 3: one end in 1 upper surface of N-type semiconductor drift region generates gate oxide 6 by hot oxygen, in gate oxide
6 surface deposition polysilicons etch to form gate electrode 5 again；
Step 4: the other end injecting p-type impurity and knot in 1 upper surface of N-type semiconductor drift region form p-type base area 3；
Step 5: injecting N-type impurity in p-type base area 3 forms N+ emitter region 7；
Step 6: injecting p-type impurity and the knot formation contact zone P+ 2 in p-type base area 3；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal forming 7 upper surface of N+ emitter region, cathodic metal 4 is formed；Cathodic metal 4 covers simultaneously
On the contact zone P+ 2；
Step 9: deposit passivation layer；
Step 10: backing substrate is thinned；
Step 11: back metal, forms metallization collector 11 in 10 bottom of the collector area P+.
Manufacturing method 2 carries out impurity compensation by ion implanting and diffusion technique to form N- layer 9, and manufacturing step is such as
Under:
Step 1: choosing doping concentration is 5e13cm-3N-type silicon chip as silicon substrate, i.e. N-type semiconductor in structure
Drift region 1 passes through phosphonium ion injection and knot formation N+ buffer layer 8 at 1 back side of the drift region N- first；
Step 2: being diffused technique again in 8 surface of N+ buffer layer injection boron ion, part N+ buffer layer 8 is carried out miscellaneous
Matter compensation, forms N- layer 9；
Step 3: one end in 1 upper surface of N-type semiconductor drift region generates gate oxide 6 by hot oxygen, in gate oxide
6 surface deposition polysilicons etch to form gate electrode 5 again；
Step 4: the other end injecting p-type impurity and knot in 1 upper surface of N-type semiconductor drift region form p-type base area 3；
Step 5: injecting N-type impurity in p-type base area 3 forms N+ emitter region 7；
Step 6: injecting p-type impurity and the knot formation contact zone P+ 2 in p-type base area 3；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal forming 7 upper surface of N+ emitter region, cathodic metal 4 is formed；Cathodic metal 4 covers simultaneously
On the contact zone P+ 2；
Step 9: deposit passivation layer；
Step 10: to injecting p-type impurity in back portion N- layer 9 and carrying out ion-activated, the formation collector area P+ 10；
Step 11: back metal, forms metallization collector 11 in 10 lower surface of the collector area P+.
The part high reliability IGBT provided by the invention, MOS may be alternatively provided as groove-shaped grid, as shown in Figure 4.
Simulation comparison is carried out to high reliability IGBT provided by the invention and routine FS-IGBT structure, is further demonstrated
The superiority of this structure.Conventional FS-IGBT structure is as shown in Figure 1, high reliability IGBT structure such as Fig. 2 provided by the invention institute
Show, the cellular width of device is identical with length, has chosen the case where N- layer 9 is 0.5um, 1um, 2um and 3um respectively and is imitated
Very.Device forward conduction, when electric current is 100A/cm2When, the forward conduction voltage drop of high reliability IGBT and routine FS-IGBT are several
It is the same, about 1.74V.
At room temperature, device work under forward blocking mode when, leakage current with forward blocking voltage change curve such as
Shown in Fig. 6, by the curve it is found that under identical forward blocking voltage, IGBT provided by the invention has lower leakage current.It is positive
When blocking voltage is 800V, the leakage current of conventional FS-IGBT is 7.7e-2mA/cm2, and in N- layer 9 provided by the invention
Corresponding leakage current is respectively 3.52e-2mA/ in the respectively high reliability IGBT of 0.5um, 1um, 2um and 3um
cm2(the 0.46 of conventional FS-IGBT leakage current), 1.82e-2mA/cm2(the 0.24 of conventional FS-IGBT leakage current), 7.14e-3mA/
cm2(the 0.093 of conventional FS-IGBT leakage current) and 4.54e-3mA/cm2(the 0.059 of conventional FS-IGBT leakage current).100℃
Under, the leakage current of device with the change curve of forward blocking voltage as shown in fig. 7, when forward blocking voltage is 800V, conventional FS-
The leakage current of IGBT is 22.7mA/cm2, and be respectively 0.5um, 1um, 2um and 3um in N- layer 9 provided by the invention
Corresponding leakage current is respectively 17.5mA/cm in high reliability IGBT2(the 0.77 of conventional FS-IGBT leakage current),
13.2mA/cm2(the 0.58 of conventional FS-IGBT leakage current), 7.16mA/cm2(the 0.32 of conventional FS-IGBT leakage current) and
4.11mA/cm2(the 0.18 of conventional FS-IGBT leakage current).Smaller leakage current of the present invention is because the collector area P+ 10 and N+ are slow
It rushes between layer 8 there are one layer of N- layer 9, is the common-base current gain α of internal PNP transistorPNPIn introduce one less than 1
N- layers of base transport factor αT,N--layer, so that the α in the internal PNP transistor of the present inventionPNPIt is smaller, therefore identical positive resistance
Power-off pressure, the leakage current of device are smaller.
Smaller common-base current gain αPNPBut also the forward blocking voltage of device improves.At room temperature, such as Fig. 8 institute
Show, the forward blocking voltage of conventional FS-IGBT is 1100V, and in N- layer 9 provided by the invention is respectively the height of 2um and 3um
Corresponding forward blocking voltage is respectively 1210V (improving 10%), 1265 (improving 15%) in reliability IGBT.100
Under conditions of DEG C, as shown in figure 9, the forward blocking voltage of high reliability IGBT provided by the invention is also above conventional FS-IGBT
Forward blocking voltage.
The turn-off characteristic of high reliability IGBT provided by the invention and routine FS-IGBT under mixed load mode is carried out
Emulation, circuit used in emulation is as shown in figure 11, and simulation result is as shown in figure 12, forward conduction electric current is 40A/cm2
Under conditions of when turning off, compared to conventional FS-IGBT, N- layer 9 reduces with a thickness of the turn-off time of the high reliability IGBT of 3um
555ns (14.2%), N- layer 9 with a thickness of the high reliability IGBT and routine FS-IGBT of 3um turn-off power loss almost without difference
It is different, so the current tail effect of device will not be aggravated by introducing N- layer 9.
By to high reliability IGBT of the present invention and forward direction of the routine FS-IGBT under two kinds of room temperature, high temperature varying environments
The comparison of leakage current under blocking mode, intuitively illustrating structure of the invention has the characteristics that smaller leakage current, has higher
Reliability.
Claims (3)
1. a kind of high reliability IGBT, including collector structure, drift region structure, emitter structure and planar gate structure；
The collector structure includes the collector area P+ (10) and the metallization collector for being located at the collector area P+ (10) lower surface
(11)；
The drift region structure includes N- layers (9) and the N+ buffer layer (8) for being located at N- layers of (9) upper surface, and is located at N+ and buffers
The drift region N- (1) of layer (8) upper surface, N- layers described (9) are located at the upper surface of the collector area P+ (10)；
The emitter structure is located at the side on the drift region N- (1) upper layer, and emitter structure includes p-type base area (3), the contact zone P+
(2), N+ emitter region (7) and metallization emitter (4)；P-type base area (3) insertion is arranged the one of the drift region N- (1) upper layer
Side；The N+ emitter region (7) is located at p-type base area (3) upper layer, and the contact zone P+ (2) is set side by side with N+ emitter region (7), and
The contact zone P+ (2) is located at device edge, and the junction depth of the contact zone P+ (2) is greater than the junction depth of p-type base area (3)；The metallization
Emitter (4) is located at the upper surface of the contact zone P+ (2) and N+ emitter region (7), and emitter (4) the only covering part N+ hair that metallizes
Penetrate area (7)；
The planar gate structure is located at side of the drift region N- (1) upper surface far from metallization emitter (4), including gate oxide
(6) and polygate electrodes (5)；The gate oxide (6) contacts with the drift region N- (1) upper surface, polygate electrodes (5) position
In the top of gate oxide (6).
2. a kind of manufacturing method of high reliability IGBT, which comprises the following steps:
Step 1: choosing boron doping concentration is 1e17cm-3P-type wafer as substrate, pass through epitaxial growth on silicon substrate
Formed N- layers (9), N- layers (9) with a thickness of 2~3um；
Step 2: using two step epitaxy techniques, it is then slow in N+ first in N- layers of (9) upper surface epitaxial growth N+ buffer layer (8)
It rushes layer (8) upper surface and passes through the drift region epitaxial growth N- (1)；
Step 3: one end in N-type semiconductor drift region (1) upper surface generates gate oxide (6) by hot oxygen, in gate oxide
(6) surface deposition polysilicon etches to form gate electrode (5) again；
Step 4: the other end injecting p-type impurity and knot in 1 upper surface of N-type semiconductor drift region form p-type base area (3)；
Step 5: injection N-type impurity forms N+ emitter region (7) in p-type base area (3)；The upper surface and part of N+ emitter region (7)
Gate oxide (6) contact；
Step 6: injecting p-type impurity and the knot formation contact zone P+ (2) in p-type base area (3)；The contact zone P+ (2) and N+ emit
Area (7) is set side by side, and the junction depth of the contact zone P+ (2) is greater than the junction depth of p-type base area (3)；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal in the portion of upper surface for forming N+ emitter region (7), metallization emitter (4) is formed；Metallization hair
The contact zone P+ (2) upper surface is completely covered in emitter-base bandgap grading (4) simultaneously；
Step 9: deposit passivation layer；
Step 10: backing substrate is thinned；
Step 11: back metal, forms metallization collector (11) in the collector area P+ (10) bottom.
3. a kind of manufacturing method of high reliability IGBT, which comprises the following steps:
Step 1: choosing doping concentration is 5e13cm-3N-type silicon chip as silicon substrate, i.e., the drift of N-type semiconductor in structure
Area (1) passes through phosphonium ion injection and knot formation N+ buffer layer (8) at the drift region N- (1) back side first；
Step 2: N+ buffer layer (8) surface injection boron ion after be diffused technique again, to part N+ buffer layer (8) into
Row impurity compensation forms N- layers (9)；
Step 3: one end in N-type semiconductor drift region (1) upper surface generates gate oxide (6) by hot oxygen, in gate oxide
(6) surface deposition polysilicon etches to form gate electrode (5) again；
Step 4: the other end injecting p-type impurity and knot in N-type semiconductor drift region (1) upper surface form p-type base area (3)；
Step 5: injection N-type impurity forms N+ emitter region (7) in p-type base area (3)；The upper surface and part of N+ emitter region (7)
Gate oxide (6) contact；
Step 6: injecting p-type impurity and the knot formation contact zone P+ (2) in p-type base area (3)；The contact zone P+ (2) and N+ emit
Area (7) is set side by side, and the junction depth of the contact zone P+ (2) is greater than the junction depth of p-type base area (3)；
Step 7: depositing BPSG insulating medium layer in device upper surface, ohmic contact hole is etched；
Step 8: depositing metal forming N+ emitter region (7) upper surface, metallization emitter (4) is formed；Metallize emitter
(4) contact zone P+ (2) upper surface is completely covered simultaneously；
Step 9: deposit passivation layer；
Step 10: to injecting p-type impurity in N- layers of back portion (9) and carrying out ion-activated, the formation collector area P+ (10)；
Step 11: back metal, forms metallization collector (11) in the collector area P+ (10) lower surface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400834A (en) * | 2019-08-15 | 2019-11-01 | 电子科技大学 | A kind of no Snapback effect is inverse to lead IGBT and its manufacturing method |
| CN111725312A (en) * | 2020-06-05 | 2020-09-29 | 安徽瑞迪微电子有限公司 | High-performance semiconductor power device and manufacturing method thereof |
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