CN111697078A - VDMOS device with high avalanche tolerance and preparation method thereof - Google Patents

VDMOS device with high avalanche tolerance and preparation method thereof Download PDF

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CN111697078A
CN111697078A CN202010605524.9A CN202010605524A CN111697078A CN 111697078 A CN111697078 A CN 111697078A CN 202010605524 A CN202010605524 A CN 202010605524A CN 111697078 A CN111697078 A CN 111697078A
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type semiconductor
doped
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oxide layer
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任敏
李吕强
蓝瑶瑶
郭乔
李泽宏
张波
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University of Electronic Science and Technology of China
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Abstract

The invention relates to the technical field of power semiconductor devices, in particular to a VDMOS (vertical double-diffused metal oxide semiconductor) capable of improving avalanche tolerance and a preparation method thereof.A second polysilicon gate electrode is introduced into the device to replace a body region below a source region of a traditional VDMOS structure, and a JEFT (vertical double-diffused metal oxide semiconductor) region is subjected to medium doping with the same impurity type as a drift region, when the device is conducted in the forward direction, a double-inversion layer channel can be formed in the body region at the side part of the source region by the first polysilicon gate electrode and the second polysilicon gate electrode, and an accumulation layer of most current carriers is formed in the JEFT region, so that the forward conduction characteristic of the VDMOS is improved; when the device is in an avalanche breakdown state, a parasitic triode is not arranged below the source region, the breakdown position can be fixed to an interface between the ohmic contact region and the drift region on the side of the source region, avalanche current can only flow out of the source electrode through the ohmic contact region, and avalanche tolerance of the VDMOS is improved.

Description

VDMOS device with high avalanche tolerance and preparation method thereof
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a VDMOS with high avalanche tolerance and a preparation method thereof.
Background
An insulated gate field effect transistor (MOSFET) is widely used in various power systems because of its advantages of fast switching speed, low power consumption, easy gate driving, low driving power, high input impedance, good frequency response, etc. In various high electrical stress systems, in addition to requiring lower conduction losses, power MOSFETs are also required to have higher reliability. In general, power MOSFETs are often subject to failure in a dynamic process, unlike failure in a static process, where the probability of device failure in a dynamic process is higher and the failure principle is more complex. Unclamped Inductive Switching (UIS) is generally considered to be the most extreme electrical stress situation that a power MOSFET can face in a system. Since the energy stored in the unclamped inductive inductor must be discharged entirely through the power MOSFET at the moment of turn-off when the loop changes from on to off, the high voltage and large current applied to the power MOSFET are very likely to cause device failure. Therefore, the UIS failure resistance of the device is usually an important index for measuring the reliability of the power device, and the avalanche tolerance is an important parameter for measuring the UIS resistance.
Research shows that the turn-on of a parasitic Bipolar Junction Transistor (BJT) inside a MOSFET is one of the important causes of UIS failure of the device. As shown in fig. 1, a source region 3, a body region 4, and a drift region 9 in a power MOSFET device form a parasitic BJT, when avalanche breakdown occurs in the power MOSFET, current generated by avalanche flows to source metal through the body region below the source region, and the very large avalanche current generates a very large voltage drop on a body region resistor below the source region.
Generally, the reduction of the resistance of the body region is often adopted in the industry to inhibit the starting of the parasitic BJT, however, the method cannot completely prevent the starting of the parasitic BJT, and the device still faces various failure problems caused by avalanche breakdown; meanwhile, implantation or deep diffusion using high-energy boron ions also leads to only a limited reduction in base resistance under the limitation of causing an increase in threshold voltage.
Disclosure of Invention
The invention provides a VDMOS device with high avalanche tolerance aiming at the problems, which can eliminate a parasitic BJT (bipolar junction transistor) below a source region and greatly improve the avalanche tolerance of the device
In order to achieve the purpose, the technical scheme of the invention is as follows:
a VDMOS device with high avalanche tolerance comprises a drain electrode structure, a drift region structure, a JEFT region structure, a source electrode structure and a grid electrode structure;
the drain structure comprises a drain metal layer 11 and a heavily doped second conductivity type semiconductor drain region 10 above the drain metal layer 11, wherein the lower surface of the heavily doped second conductivity type semiconductor drain region 10 is in direct contact with the drain metal layer 11;
the drift region structure comprises a lightly doped second conductivity type semiconductor drift region 9 above a second conductivity type semiconductor drain region 10; the lower surface of the lightly doped second conductivity type semiconductor drift region 9 is directly contacted with the heavily doped second conductivity type semiconductor drain region 10, and the lightly doped second conductivity type semiconductor drift region 9 is positioned below the source structure, the gate structure and the JEFT structure and is isolated from the second polysilicon gate electrode 52 through a gate insulating medium layer 62;
the JEFT region structure is positioned on the upper surface of the lightly doped second type conductivity semiconductor drift region 9 and comprises a medium doped second type conductivity semiconductor JEFT region 7 positioned between the second gate insulation layers 62;
the source electrode structure comprises a source electrode metal layer 1, a heavily doped first conduction type semiconductor ohmic contact region 2, a heavily doped second conduction type semiconductor source region 3 and a moderately doped first conduction type semiconductor body region 4; two sides of a heavily doped second conduction type semiconductor source region 3 of the source electrode structure are a heavily doped first conduction type semiconductor ohmic contact region 2 and a moderately doped first conduction type semiconductor body region 4 respectively, wherein the moderately doped first conduction type semiconductor body region 4 is positioned at one side close to the JEFT region structure, the heavily doped first conduction type semiconductor ohmic contact region 2 is positioned at one side far away from the JEFT region structure, and the upper surfaces of the heavily doped first conduction type semiconductor ohmic contact region 2 and the heavily doped second conduction type semiconductor source region 3 are directly contacted with a source electrode metal layer 1;
the gate structure comprises a first polysilicon gate electrode 51, a second polysilicon gate electrode 52, a first gate insulating medium layer 61 and a second gate insulating medium layer 62; the first polysilicon gate electrode 51 of the gate structure is positioned right above the first-type conductivity-type semiconductor body region 4 and spans the whole JEFT region structure, the first polysilicon gate electrode 51 is isolated from the first-type conductivity-type semiconductor body region 4 by a first gate insulating medium layer 61, and the second polysilicon gate electrode 52 is positioned right below the heavily-doped second-type conductivity-type semiconductor source region 3 and the moderately-doped first-type conductivity-type semiconductor body region 4 and isolated from the second-type conductivity-type semiconductor source region 3 and the first-type conductivity-type semiconductor body region 4 by a gate insulating medium layer 62.
Preferably, the drift region structure is formed by alternately arranging lightly doped first conductivity type semiconductor regions 8 and lightly doped second conductivity type semiconductor regions 9 having the same width and doping concentration.
Preferably, the depth of the gate insulating dielectric layer 62 surrounding the second polysilicon gate 52 is the same as the depth of the heavily doped first conductivity type semiconductor ohmic contact region 2.
Preferably, the material of the VDMOS device is silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor material.
Preferably, the first conductivity type semiconductor is doped to be a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first type conductivity type semiconductor is doped into an N-type semiconductor, and the second type conductivity type semiconductor is a P-type semiconductor.
Preferably, the light doping is performed in the order of the impurity concentration of 1e16cm-3And a medium doping of an impurity concentration order of 1e16cm-3To 1e18cm-3Doped to an impurity concentration order of greater than 1e18cm-3Doping of (3).
Preferably, the VDMOS device is obtained by a preparation method including the steps of:
step 1: selecting an N-type silicon substrate slice, and growing a lightly doped N-type monocrystalline silicon epitaxial layer on the substrate slice;
step 2: growing an oxide layer, coating photoresist and etching the grooves above the epitaxial layer to form a plurality of grooves, oxidizing again, growing an oxide layer in the grooves, and depositing polycrystalline silicon;
and step 3: etching to remove all the polysilicon and the oxide layer material outside the groove and the redundant part inside the groove;
and 4, step 4: growing or depositing an oxide layer again, etching away redundant oxide layer materials outside the groove, and only keeping part of the oxide layer above the polycrystalline silicon inside the groove;
and 5: carrying out epitaxial growth of monocrystalline silicon on the upper surface of the epitaxial layer again, and growing the epitaxial layer of the monocrystalline silicon above the oxide layer in the groove by utilizing the monocrystalline silicon material on the side wall according to the characteristic that the bonding energy of the side surface of the groove is lower;
step 6: after the groove is completely filled with the epitaxial growth monocrystalline silicon, carrying out chemical mechanical polishing to ensure that the surface of the whole epitaxial monocrystalline silicon layer is smooth;
and 7: carrying out N-type impurity moderate doping on the JEFT region between the grooves;
and 8: growing an oxide layer on the upper surface of the epitaxial layer, depositing polycrystalline silicon, and etching to manufacture a gate oxide layer and gate polycrystalline silicon on the surface;
and step 9: doping and annealing the body region and the source region above the epitaxial layer by using a self-alignment process to form a medium-doped P-type body region and a heavily-doped N-type source region;
step 10: oxidizing the surface of the epitaxial layer, photoetching a source electrode contact hole, doping and annealing the source electrode contact hole to form a heavily doped P-type ohmic contact region, and depositing a metal layer on the oxide layer to form source electrode metal;
step 11: and thinning the back of the substrate piece to the required thickness, then carrying out heavy doping on N-type impurities to form a drain region, and finally carrying out metal deposition on the back to form drain metal.
In order to achieve the above object, the present invention further provides a method for manufacturing a VDMOS device with high avalanche tolerance, including the following steps:
step 1: selecting an N-type silicon substrate slice, and growing a lightly doped N-type monocrystalline silicon epitaxial layer on the substrate slice;
step 2: growing an oxide layer, coating photoresist and etching the grooves above the epitaxial layer to form a plurality of grooves, oxidizing again, growing an oxide layer in the grooves, and depositing polycrystalline silicon;
and step 3: etching to remove all the polysilicon and the oxide layer material outside the groove and the redundant part inside the groove;
and 4, step 4: growing or depositing an oxide layer again, etching away redundant oxide layer materials outside the groove, and only keeping part of the oxide layer above the polycrystalline silicon inside the groove;
and 5: carrying out epitaxial growth of monocrystalline silicon on the upper surface of the epitaxial layer again, and growing the epitaxial layer of the monocrystalline silicon above the oxide layer in the groove by utilizing the monocrystalline silicon material on the side wall according to the characteristic that the bonding energy of the side surface of the groove is lower;
step 6: after the groove is completely filled with the epitaxial growth monocrystalline silicon, carrying out chemical mechanical polishing to ensure that the surface of the whole epitaxial monocrystalline silicon layer is smooth;
and 7: carrying out N-type impurity moderate doping on the JEFT region between the grooves;
and 8: growing an oxide layer on the upper surface of the epitaxial layer, depositing polycrystalline silicon, and etching to manufacture a gate oxide layer and gate polycrystalline silicon on the surface;
and step 9: doping and annealing the body region and the source region above the epitaxial layer by using a self-alignment process to form a medium-doped P-type body region and a heavily-doped N-type source region;
step 10: oxidizing the surface of the epitaxial layer, photoetching a source electrode contact hole, doping and annealing the source electrode contact hole to form a heavily doped P-type ohmic contact region, and depositing a metal layer on the oxide layer to form source electrode metal;
step 11: and thinning the back of the substrate piece to the required thickness, then carrying out heavy doping on N-type impurities to form a drain region, and finally carrying out metal deposition on the back to form drain metal.
The invention has the beneficial effects that: the second polysilicon gate electrode is introduced to replace a body region below a source region of a traditional VDMOS structure, the JEFT region is subjected to medium doping with the same impurity type as that of a drift region, when the device is conducted in the forward direction, the first polysilicon gate electrode and the second polysilicon gate electrode can form a double-inversion layer channel in the body region on the side portion of the source region, and an accumulation layer of majority carriers is formed in the JEFT region, so that the forward conduction characteristic of the VDMOS is greatly improved; when the device is in an avalanche breakdown state, a parasitic triode is not arranged below the source region, the breakdown position is fixed to an interface between the ohmic contact region and the drift region on the side of the source region, avalanche current can only flow out of the source electrode through the ohmic contact region, and therefore the UIS resistance of the VDMOS can be greatly improved.
Drawings
Fig. 1 is a schematic diagram of a device structure of a conventional VDMOS and its parasitic BJT and avalanche breakdown current path.
Fig. 2 is a device of a VDMOS with high avalanche tolerance provided in embodiment 1.
Fig. 3 is a device structure of a VDMOS with high avalanche resistance provided in embodiment 1 and an avalanche breakdown current path thereof.
Fig. 4 is a device of a super junction VDMOS with high avalanche tolerance provided in embodiment 2.
Fig. 5 is a schematic flow chart of a manufacturing process of a super junction VDMOS with high avalanche tolerance provided in embodiment 1 of the present invention.
The structure of the avalanche breakdown current path comprises a source metal layer 1, a heavily doped first-type conductivity semiconductor ohmic contact region 2, a heavily doped second-type conductivity semiconductor source region 3, a moderately doped first-type conductivity semiconductor body region 4, a polysilicon gate electrode 5, a first polysilicon gate electrode 51, a second polysilicon gate electrode 52, a gate insulating dielectric layer 6, a first gate insulating dielectric layer 61, a second gate insulating dielectric layer 62, a moderately doped second-type conductivity semiconductor JEFT region 7, a lightly doped first-type conductivity semiconductor drift region 8, a lightly doped second-type conductivity semiconductor drift region 9, a heavily doped second-type conductivity semiconductor drain region 10, a drain metal layer 11 and an avalanche breakdown current path 12.
Detailed Description
Example 1
A VDMOS device with high avalanche tolerance is structurally shown in figure 2 and comprises a drain electrode structure, a drift region structure, a JEFT region structure, a source electrode structure and a grid electrode structure;
the drain structure comprises a drain metal layer 11 and a heavily doped second conductivity type semiconductor drain region 10 above the drain metal layer 11, wherein the lower surface of the heavily doped second conductivity type semiconductor drain region 10 is in direct contact with the drain metal layer 11;
the drift region structure comprises a lightly doped second conductivity type semiconductor drift region 9 above a second conductivity type semiconductor drain region 10; the lower surface of the lightly doped second conductivity type semiconductor drift region 9 is directly contacted with the heavily doped second conductivity type semiconductor drain region 10, and the lightly doped second conductivity type semiconductor drift region 9 is positioned below the source structure, the gate structure and the JEFT structure and is isolated from the second polysilicon gate electrode 52 through a gate insulating medium layer 62;
the JEFT region structure is positioned on the upper surface of the lightly doped second type conductivity semiconductor drift region 9 and comprises a medium doped second type conductivity semiconductor JEFT region 7 positioned between the second gate insulation layers 62;
the source electrode structure comprises a source electrode metal layer 1, a heavily doped first conduction type semiconductor ohmic contact region 2, a heavily doped second conduction type semiconductor source region 3 and a moderately doped first conduction type semiconductor body region 4; two sides of a heavily doped second conduction type semiconductor source region 3 of the source electrode structure are a heavily doped first conduction type semiconductor ohmic contact region 2 and a moderately doped first conduction type semiconductor body region 4 respectively, wherein the moderately doped first conduction type semiconductor body region 4 is positioned at one side close to the JEFT region structure, the heavily doped first conduction type semiconductor ohmic contact region 2 is positioned at one side far away from the JEFT region structure, and the upper surfaces of the heavily doped first conduction type semiconductor ohmic contact region 2 and the heavily doped second conduction type semiconductor source region 3 are directly contacted with a source electrode metal layer 1;
the gate structure comprises a first polysilicon gate electrode 51, a second polysilicon gate electrode 52, a first gate insulating medium layer 61 and a second gate insulating medium layer 62; the first polysilicon gate electrode 51 of the gate structure is positioned right above the first-type conductivity-type semiconductor body region 4 and spans the whole JEFT region structure, the first polysilicon gate electrode 51 is isolated from the first-type conductivity-type semiconductor body region 4 by a first gate insulating medium layer 61, and the second polysilicon gate electrode 52 is positioned right below the heavily-doped second-type conductivity-type semiconductor source region 3 and the moderately-doped first-type conductivity-type semiconductor body region 4 and isolated from the second-type conductivity-type semiconductor source region 3 and the first-type conductivity-type semiconductor body region 4 by a gate insulating medium layer 62.
In this embodiment, the depth of the gate insulating dielectric layer 62 surrounding the second polysilicon gate 52 is the same as the depth of the heavily doped first conductivity type semiconductor ohmic contact region 2.
The VDMOS device is made of silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor materials.
The light doping is carried out in the way that the impurity concentration is 1e16cm-3And a medium doping of an impurity concentration order of 1e16cm-3To 1e18cm-3Doped to an impurity concentration order of greater than 1e18cm-3Doping of (3).
According to the scheme, when the first type of conductive semiconductor is doped into a P-type semiconductor and the second type of conductive semiconductor is an N-type semiconductor, the device is an N-type double-channel VDMOS; when the first type of conductivity type semiconductor is doped into an N-type semiconductor and the second type of conductivity type semiconductor is a P-type semiconductor, the device is a P-type double-channel VDMOS.
The working principle of the present invention is described in detail below with reference to this embodiment 1 (taking N-type VDMOS as an example):
in the forward conducting state, the connection mode of the electrodes in example 1 is: the source metal layer 1 is connected to a low potential, the first polysilicon gate electrode 51 and the second polysilicon gate electrode 52 are connected to a high potential, and the drain metal layer 11 is connected to a high potential. At this time, a double inversion layer channel is formed in the moderately doped first conductivity type semiconductor body region 4 when the first polysilicon gate electrode 51 and the second polysilicon gate electrode 52 are connected with high potential, meanwhile, an electron accumulation layer is formed above the moderately doped second conductivity type semiconductor JEFT region 7 when the first polysilicon gate electrode 51 is connected with high potential, an electron accumulation layer is formed on the side of the moderately doped second conductivity type semiconductor JEFT region 7 when the second polysilicon gate electrode 52 is connected with high potential, the on-resistance of the device is reduced, and the forward on-state characteristic is improved.
In the off blocking state, the electrodes in example 1 were connected in the following manner: the source metal layer 1 is connected to a low potential, the first polysilicon gate electrode 51 and the second polysilicon gate electrode 52 are connected to a low potential, and the drain metal layer 11 is connected to a high potential. At this time, the first polysilicon gate electrode 51 and the second polysilicon gate electrode 52 can laterally deplete the first conductivity type semiconductor body 4, which also allows for a higher degree of doping of the JEFT region. In addition, because the doping concentration of the heavily doped first-type conductivity type semiconductor ohmic contact region 2 is greater than that of the moderately doped first-type conductivity type semiconductor body region 4, the electric field peak value can appear at the interface of the heavily doped first-type conductivity type semiconductor ohmic contact region 2 and the lightly doped second-type conductivity type semiconductor drift region 9, if avalanche breakdown occurs, a breakdown point can be fixed below the heavily doped first-type conductivity type semiconductor ohmic contact region 2, avalanche current can only flow through the heavily doped first-type conductivity type semiconductor ohmic contact region 2 and then flow out of a source electrode, as shown in fig. 3, the parasitic triode is effectively prevented from being turned on, and the UIS resistance of the device can be greatly enhanced.
The embodiment also provides a method for manufacturing a VDMOS device with high avalanche tolerance, which takes an N-type VDMOS as an example, and specifically includes the following steps:
step 1: selecting an N-type silicon substrate slice, and growing a lightly doped N-type monocrystalline silicon epitaxial layer on the substrate slice, as shown in (a) of fig. 5;
step 2: growing an oxide layer, coating photoresist and etching the grooves above the epitaxial layer to form a plurality of grooves, oxidizing again to grow the oxide layer in the grooves, and depositing polycrystalline silicon, as shown in (b) of fig. 5;
and step 3: etching away all the polysilicon and oxide layer material outside the trench and the internal excess portion, as shown in fig. 5 (c);
and 4, step 4: growing or depositing an oxide layer again, and etching away the redundant oxide layer material outside the trench, and only keeping a part of the oxide layer above the polysilicon inside the trench, as shown in (d) in fig. 5;
and 5: performing epitaxial growth of the monocrystalline silicon again on the upper surface of the epitaxial layer, and growing the monocrystalline silicon epitaxial layer above the oxide layer in the trench by using the monocrystalline silicon material on the side wall according to the characteristic that the bonding energy of the side surface of the trench is lower, as shown in fig. 5 (e);
step 6: after the epitaxially grown single crystal silicon completely fills the trench, performing chemical mechanical polishing to flatten the surface of the entire epitaxial single crystal silicon layer, as shown in fig. 5 (f);
and 7: carrying out N-type impurity moderate doping on the JEFT region between the grooves, as shown in (g) in FIG. 5;
and 8: growing an oxide layer on the upper surface of the epitaxial layer, depositing polycrystalline silicon, and etching to manufacture a gate oxide layer and gate polycrystalline silicon on the surface, as shown in (h) of fig. 5;
and step 9: doping and annealing the body region and the source region above the epitaxial layer by using a self-alignment process to form a medium doped P-type body region and a heavily doped N-type source region, as shown in (i) of fig. 5;
step 10: oxidizing the surface of the epitaxial layer, photoetching a source contact hole, doping and annealing the source contact hole to form a heavily doped P-type ohmic contact region, and depositing a metal layer on the oxide layer to form source metal, as shown in (j) in fig. 5;
step 11: the back of the substrate sheet is thinned to a required thickness, then heavy doping of N-type impurities is carried out to form a drain region, and finally metal deposition of the back is carried out to form drain metal, as shown in fig. 5 (k).
Example 2
In the structure of this example, on the basis of embodiment 1, the lightly doped second conductivity type semiconductor drift region structure is replaced with the super junction structure, and as shown in fig. 4, the drift regions are the lightly doped first conductivity type semiconductor drift region 8 and the lightly doped second conductivity type semiconductor region 9 which are alternately arranged and have the same width and doping concentration, so that a double-channel super junction VDMOS with high avalanche tolerance can be manufactured, which can further reduce the on-resistance of the device and obtain a higher blocking voltage compared with embodiment 1.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A VDMOS device with high avalanche tolerance is characterized in that: the transistor comprises a drain electrode structure, a drift region structure, a JEFT region structure, a source electrode structure and a grid electrode structure;
the drain structure comprises a drain metal layer (11) and a heavily doped second conductivity type semiconductor drain region (10) above the drain metal layer (11), wherein the lower surface of the heavily doped second conductivity type semiconductor drain region (10) is directly contacted with the drain metal layer (11);
the drift region structure comprises a lightly doped second conductivity type semiconductor drift region (9) above a second conductivity type semiconductor drain region (10); the lower surface of the lightly doped second conduction type semiconductor drift region (9) is directly contacted with the heavily doped second conduction type semiconductor drain region (10), and the lightly doped second conduction type semiconductor drift region (9) is positioned below the source structure, the gate structure and the JEFT structure and is isolated from the second polysilicon gate electrode (52) through a gate insulating medium layer (62);
the JEFT region structure is positioned on the upper surface of the lightly doped second-type conductivity semiconductor drift region (9) and comprises a medium-doped second-type conductivity semiconductor JEFT region (7) positioned between the second gate insulating layers (62);
the source electrode structure comprises a source electrode metal layer (1), a heavily doped first conduction type semiconductor ohmic contact region (2), a heavily doped second conduction type semiconductor source region (3) and a moderately doped first conduction type semiconductor body region (4); two sides of a heavily doped second conduction type semiconductor source region (3) of the source structure are a heavily doped first conduction type semiconductor ohmic contact region (2) and a moderately doped first conduction type semiconductor body region (4) respectively, wherein the moderately doped first conduction type semiconductor body region (4) is positioned on one side close to the JEFT region structure, the heavily doped first conduction type semiconductor ohmic contact region (2) is positioned on one side far away from the JEFT region structure, and the upper surfaces of the heavily doped first conduction type semiconductor ohmic contact region (2) and the heavily doped second conduction type semiconductor source region (3) are directly contacted with the source metal layer (1);
the gate structure comprises a first polycrystalline silicon gate electrode (51), a second polycrystalline silicon gate electrode (52), a first gate insulating medium layer (61) and a second gate insulating medium layer (62); a first polycrystalline silicon gate electrode (51) of the gate structure is located right above a first-type conduction type semiconductor body region (4) and spans the whole JEFT region structure, the first polycrystalline silicon gate electrode (51) is isolated from the first-type conduction type semiconductor body region (4) through a first gate insulating medium layer (61), and a second polycrystalline silicon gate electrode (52) is located right below a heavily-doped second-type conduction type semiconductor source region (3) and a moderately-doped first-type conduction type semiconductor body region (4) and isolated from the second-type conduction type semiconductor source region (3) and the first-type conduction type semiconductor body region (4) through a gate insulating medium layer (62).
2. The VDMOS device with high avalanche tolerance according to claim 1, wherein: the drift region structure is formed by alternately arranging lightly doped first-type conductivity type semiconductor regions (8) and lightly doped second-type conductivity type semiconductor regions (9) with the same width and doping concentration.
3. A VDMOS device with high avalanche tolerance according to claim 1 or 2, wherein: the depth of the gate insulating dielectric layer (62) surrounding the second polysilicon gate (52) is the same as the depth of the heavily doped first conductivity type semiconductor ohmic contact region (2).
4. A VDMOS device with high avalanche tolerance according to any one of claims 1 to 3, wherein: the VDMOS device is made of silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor materials.
5. A VDMOS device with high avalanche tolerance according to any one of claims 1 to 4, wherein: the first type of conductive semiconductor is doped into a P-type semiconductor, and the second type of conductive semiconductor is an N-type semiconductor; or the first type conductivity type semiconductor is doped into an N-type semiconductor, and the second type conductivity type semiconductor is a P-type semiconductor.
6. A VDMOS device with high avalanche tolerance according to any one of claims 1 to 5, wherein: the light doping is carried out in the way that the impurity concentration is 1e16cm-3And a medium doping of an impurity concentration order of 1e16cm-3To 1e18cm-3Doped to an impurity concentration order of greater than 1e18cm-3Doping of (3).
7. The VDMOS device with high avalanche tolerance according to any one of claims 1 to 6, which is prepared by the following steps:
step 1: selecting an N-type silicon substrate slice, and growing a lightly doped N-type monocrystalline silicon epitaxial layer on the substrate slice;
step 2: growing an oxide layer, coating photoresist and etching the grooves above the epitaxial layer to form a plurality of grooves, oxidizing again, growing an oxide layer in the grooves, and depositing polycrystalline silicon;
and step 3: etching to remove all the polysilicon and the oxide layer material outside the groove and the redundant part inside the groove;
and 4, step 4: growing or depositing an oxide layer again, etching away redundant oxide layer materials outside the groove, and only keeping part of the oxide layer above the polycrystalline silicon inside the groove;
and 5: carrying out epitaxial growth of monocrystalline silicon on the upper surface of the epitaxial layer again, and growing the epitaxial layer of the monocrystalline silicon above the oxide layer in the groove by utilizing the monocrystalline silicon material on the side wall according to the characteristic that the bonding energy of the side surface of the groove is lower;
step 6: after the groove is completely filled with the epitaxial growth monocrystalline silicon, carrying out chemical mechanical polishing to ensure that the surface of the whole epitaxial monocrystalline silicon layer is smooth;
and 7: carrying out N-type impurity moderate doping on the JEFT region between the grooves;
and 8: growing an oxide layer on the upper surface of the epitaxial layer, depositing polycrystalline silicon, and etching to manufacture a gate oxide layer and gate polycrystalline silicon on the surface;
and step 9: doping and annealing the body region and the source region above the epitaxial layer by using a self-alignment process to form a medium-doped P-type body region and a heavily-doped N-type source region;
step 10: oxidizing the surface of the epitaxial layer, photoetching a source electrode contact hole, doping and annealing the source electrode contact hole to form a heavily doped P-type ohmic contact region, and depositing a metal layer on the oxide layer to form source electrode metal;
step 11: and thinning the back of the substrate piece to the required thickness, then carrying out heavy doping on N-type impurities to form a drain region, and finally carrying out metal deposition on the back to form drain metal.
8. A preparation method of a VDMOS device with high avalanche tolerance is characterized by comprising the following steps:
step 1: selecting an N-type silicon substrate slice, and growing a lightly doped N-type monocrystalline silicon epitaxial layer on the substrate slice;
step 2: growing an oxide layer, coating photoresist and etching the grooves above the epitaxial layer to form a plurality of grooves, oxidizing again, growing an oxide layer in the grooves, and depositing polycrystalline silicon;
and step 3: etching to remove all the polysilicon and the oxide layer material outside the groove and the redundant part inside the groove;
and 4, step 4: growing or depositing an oxide layer again, etching away redundant oxide layer materials outside the groove, and only keeping part of the oxide layer above the polycrystalline silicon inside the groove;
and 5: carrying out epitaxial growth of monocrystalline silicon on the upper surface of the epitaxial layer again, and growing the epitaxial layer of the monocrystalline silicon above the oxide layer in the groove by utilizing the monocrystalline silicon material on the side wall according to the characteristic that the bonding energy of the side surface of the groove is lower;
step 6: after the groove is completely filled with the epitaxial growth monocrystalline silicon, carrying out chemical mechanical polishing to ensure that the surface of the whole epitaxial monocrystalline silicon layer is smooth;
and 7: carrying out N-type impurity moderate doping on the JEFT region between the grooves;
and 8: growing an oxide layer on the upper surface of the epitaxial layer, depositing polycrystalline silicon, and etching to manufacture a gate oxide layer and gate polycrystalline silicon on the surface;
and step 9: doping and annealing the body region and the source region above the epitaxial layer by using a self-alignment process to form a medium-doped P-type body region and a heavily-doped N-type source region;
step 10: oxidizing the surface of the epitaxial layer, photoetching a source electrode contact hole, doping and annealing the source electrode contact hole to form a heavily doped P-type ohmic contact region, and depositing a metal layer on the oxide layer to form source electrode metal;
step 11: and thinning the back of the substrate piece to the required thickness, then carrying out heavy doping on N-type impurities to form a drain region, and finally carrying out metal deposition on the back to form drain metal.
CN202010605524.9A 2020-06-29 2020-06-29 VDMOS device with high avalanche tolerance and preparation method thereof Pending CN111697078A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114628496A (en) * 2022-05-13 2022-06-14 江苏游隼微电子有限公司 Multi-groove power MOSFET structure and manufacturing method thereof
CN115332338A (en) * 2022-08-08 2022-11-11 上海功成半导体科技有限公司 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN117219660A (en) * 2023-11-08 2023-12-12 深圳天狼芯半导体有限公司 MOSFET device based on gate burying and preparation method
CN117637897A (en) * 2024-01-25 2024-03-01 北京中科海芯科技有限公司 Avalanche photodiode, manufacturing method thereof and photoelectric detector

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0281476A (en) * 1988-09-17 1990-03-22 Fuji Electric Co Ltd Mos type semiconductor device
US5703384A (en) * 1995-06-19 1997-12-30 Siemens Aktiengesellschaft MOS semiconductor component having improved transmission properties
US5708286A (en) * 1995-03-31 1998-01-13 Kabushiki Kaisha Toyota Chuo Kenkyusho Insulated gate semiconductor device and fabrication method therefor
JP2000208757A (en) * 1999-01-08 2000-07-28 Nippon Telegr & Teleph Corp <Ntt> Insulating gate type semiconductor device and its manufacture
US20050032291A1 (en) * 2001-04-11 2005-02-10 Baliga Bantval Jayant Methods of forming power semiconductor devices having laterally extending base shielding regions
CN107431090A (en) * 2015-03-18 2017-12-01 三菱电机株式会社 Power semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0281476A (en) * 1988-09-17 1990-03-22 Fuji Electric Co Ltd Mos type semiconductor device
US5708286A (en) * 1995-03-31 1998-01-13 Kabushiki Kaisha Toyota Chuo Kenkyusho Insulated gate semiconductor device and fabrication method therefor
US5703384A (en) * 1995-06-19 1997-12-30 Siemens Aktiengesellschaft MOS semiconductor component having improved transmission properties
JP2000208757A (en) * 1999-01-08 2000-07-28 Nippon Telegr & Teleph Corp <Ntt> Insulating gate type semiconductor device and its manufacture
US20050032291A1 (en) * 2001-04-11 2005-02-10 Baliga Bantval Jayant Methods of forming power semiconductor devices having laterally extending base shielding regions
CN107431090A (en) * 2015-03-18 2017-12-01 三菱电机株式会社 Power semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114628496A (en) * 2022-05-13 2022-06-14 江苏游隼微电子有限公司 Multi-groove power MOSFET structure and manufacturing method thereof
CN115332338A (en) * 2022-08-08 2022-11-11 上海功成半导体科技有限公司 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN117219660A (en) * 2023-11-08 2023-12-12 深圳天狼芯半导体有限公司 MOSFET device based on gate burying and preparation method
CN117637897A (en) * 2024-01-25 2024-03-01 北京中科海芯科技有限公司 Avalanche photodiode, manufacturing method thereof and photoelectric detector

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Application publication date: 20200922