JPH0281476A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPH0281476A JPH0281476A JP63233110A JP23311088A JPH0281476A JP H0281476 A JPH0281476 A JP H0281476A JP 63233110 A JP63233110 A JP 63233110A JP 23311088 A JP23311088 A JP 23311088A JP H0281476 A JPH0281476 A JP H0281476A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- impurity concentration
- type
- abnormality
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000010410 layer Substances 0.000 claims abstract description 55
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000002344 surface layer Substances 0.000 claims abstract description 7
- 230000005856 abnormality Effects 0.000 abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000009466 transformation Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、第−導電形のドレイン領域の表面部に第二導
電形のベース層を有し、ベース層にはドレイン領域との
間にチャネル形成領域をはさむ高不純物濃度の第−導電
形のソース層およびそのソース層のドレイン領域より遠
い側に高不純物濃度のベース層を有し、チャネル形成領
域上にはゲート絶縁膜を介してゲート電極とソース層お
よび高不純物濃度ベース層に接触するソース電極とを備
えた電力用縦型ＭＯＳ Ｆ ＥＴや絶縁ゲート型バイポ
ーラトランジスタなどのＭＯ３Ｏ３型半導体装置する。Detailed Description of the Invention [Industrial Field of Application] The present invention has a base layer of a second conductivity type on the surface of a drain region of a first conductivity type, and the base layer has a base layer between it and the drain region. A source layer of the first conductivity type with a high impurity concentration sandwiching a channel formation region and a base layer with a high impurity concentration on the side farther from the drain region of the source layer. MO3O3 type semiconductor devices, such as vertical power MOSFETs and insulated gate bipolar transistors, include an electrode, a source layer, and a source electrode in contact with a high impurity concentration base layer.
ご従来の技術〕
ＭＯ３型半導体装置には、単一キャリアのみを利用する
電力用ＭＯ３ＦＥＴと、電子と正孔の２種のキャリアに
よる電導度変調を利用する絶縁ゲート型バイポーラトラ
ンジスタ （ＩＧＢＴ）がある。Conventional technology] MO3 type semiconductor devices include power MO3FETs that use only a single carrier, and insulated gate bipolar transistors (IGBTs) that use conductivity modulation by two types of carriers, electrons and holes. .
１！１ｍゲート型バイポーラトランジスタは、低いオン
抵抗と電力用ＭＯＳ Ｆ ＥＴの高速性を結び付けたも
のとして着目されているが、その基本構成は第２図に示
すとおりで、構造的には縦型ＭＯ３ＦＥＴのドレイン領
域となるＮ゛層をＰ゛層に置き換えたものということが
できる。すなわち、Ｐ゛基板１ （ドレイン）の上に低
不純物濃度のＮ−層２ （ベース）を形成し、この表面
部に選択的に２層３を、さらにこの表面部に選択的にＮ
″眉４ソース）を形成し、ＰＩｌ１３のＮ−層２とＮ゛
層４挟まれた表面領域をチャネル領域として、この上に
ゲート絶縁ＷＡ５を介してゲート９１６を形成する。そ
して、ＰＩ！Ｉ （チャネル！ｌ）３とＮ゛層４また
がってソース１を極７を設け、ドレイン側にドレイン電
極８を設ける。ソース電極７の接触する部分にはｐＨ３
より深いＰ°ベース層９を形成する。The 1!1m gate type bipolar transistor is attracting attention as it combines low on-resistance with the high speed of power MOSFETs, but its basic configuration is shown in Figure 2, and its structure is vertical. It can be said that the N' layer, which becomes the drain region of the MO3FET, is replaced with a P' layer. That is, an N- layer 2 (base) with a low impurity concentration is formed on a P substrate 1 (drain), a 2 layer 3 is selectively formed on this surface area, and an N layer 3 is selectively formed on this surface area.
The surface region sandwiched between the N- layer 2 and the N-layer 4 of the PIl 13 is used as a channel region, and a gate 916 is formed thereon via the gate insulating WA5. (Channel!l) 3 and the N layer 4, a source 1 is provided with a pole 7, and a drain electrode 8 is provided on the drain side.The part in contact with the source electrode 7 has a pH of 3
A deeper P° base layer 9 is formed.
この素子はスイッチングスピードを速めるために通常の
ライフタイムキラーを導入するが、金のようにシリコン
原子と置換してアクセプタとして働くキラーの場合、絶
縁膜付近に偏析してＮ−基板２のドナー濃度を下げるた
めに、ドレイン電圧■。が一定値に達するまではオンし
なかったり、オン電圧が極端に大きくなるなどの異常を
ひき起こす、第３図＋ａｌ、（ｂｌはこの状態を示し、
（ｂｌはｆ８＋のＸ−Ｘ線に沿っての断面における電位
分布を示す。This element introduces a normal lifetime killer to increase the switching speed. However, in the case of a killer such as gold, which works as an acceptor by replacing silicon atoms, it segregates near the insulating film and increases the donor concentration of the N-substrate 2. ■ To lower the drain voltage. This can cause abnormalities such as not turning on until the voltage reaches a certain value, or the on-voltage becoming extremely large.
(bl indicates the potential distribution in the cross section along the X-X line of f8+.
図ｔａ＋のように低不純物濃度のＰ−層２１が形成され
ているために、図（ｂｌに線３１によって示すようにＢ
点付近に電位の井戸が生じ、■、が上昇してもＡ点の電
位はＭ１３２へとわずかしか上昇せずチャネル電流が流
れないからである。また隣り合うセル間の間隔が狭くな
るとＮ基板と隣り合う二つのＰ層で構成するＪＦＥＴ
（接合型ＦＥＴ）が容易にピンチオフしてしまうため
オン電圧が極端に大きくなる。同様な問題は縦型ＭＯ３
ＦＥＴにおいても生ずる。Since the P- layer 21 with a low impurity concentration is formed as shown in figure ta+, B
This is because a potential well is generated near the point, and even if . In addition, when the distance between adjacent cells becomes narrower, a JFET consisting of an N substrate and two adjacent P layers
Since the (junction type FET) easily pinches off, the on-voltage becomes extremely large. Similar problem is vertical MO3
This also occurs in FETs.
本発明の課題は、上記のように金などのライフタイムキ
ラーを導入した場合のＮヘース層のチャネル領域に接す
る表面層がＰ転することによるターンオン異常１オン電
圧異常を防止したＭＯ３型半導体装置を提供することに
ある。The object of the present invention is to prevent the turn-on abnormality 1-on voltage abnormality caused by the P conversion of the surface layer in contact with the channel region of the N hese layer when a lifetime killer such as gold is introduced as described above. Our goal is to provide the following.
上記の課題の解決のために、本発明は、少なくとも、低
不純物濃度のＮ形の第−領域と、第一領域表面部に選択
的に形成されたＰ形の第三領域と、第二領域表面部に選
択的に形成された高不純物１廣でＮ形の第三領域とを有
し、第三領域と第一領域の間の第二領域をチャネル領域
として対向するチャネル領域上にわたって絶ｔ！ Ｍを
介してゲート電極が設けられ、一つの主電橋が第二領域
および第三領域の表面に共通に接触するＭＯ３型半導体
装置において、対向するチャネル領域の間の第一領域の
表面層がその層より下の第一？ｉｎ城の不純物濃度より
高く、５×１０”’／ｃｃ以下の不純物濃度をもつＮ形
の層であるものとする。In order to solve the above problems, the present invention provides at least an N-type first region with a low impurity concentration, a P-type third region selectively formed on the surface of the first region, and a second region. It has an N-type third region with a high impurity concentration selectively formed on the surface portion, and a second region between the third region and the first region is used as a channel region, and an absolute T region is formed over the opposing channel region. ! In an MO3 type semiconductor device in which a gate electrode is provided through M and one main bridge commonly contacts the surfaces of the second region and the third region, the surface layer of the first region between the opposing channel regions is The first one below that layer? It is assumed that the layer is an N-type layer having an impurity concentration higher than that of the inner layer and less than or equal to 5×10''/cc.
Ｎ形第−領域の表面層が高い不純物２１度をもつことに
より、アクセプタ的なライフタイムキラーにより表面に
Ｐ−Ｊｉが形成されるのを防ぐ、ごの作用は絶縁ゲート
型バイポーラ１ランジスタでも縦型ＭＯ３ＦＥＴでも同
様で、ターンオフ異心オン電圧異常を防ぐことができる
。なお５ Ｘ Ｉ Ｑ Ｉ Ｌ／ｃｃ以上のＮＮとする
と、Ｎ層形成の際不純物の横方向拡散によりチャネル領
域が狭くなるので望ましくない。The surface layer of the N-type region has a high impurity concentration of 21 degrees, which prevents the formation of P-Ji on the surface due to an acceptor-like lifetime killer. The same applies to the type MO3FET, and it is possible to prevent turn-off abnormality and on-voltage abnormality. Note that an NN of 5 X I Q I L/cc or more is not desirable because the channel region becomes narrower due to lateral diffusion of impurities during formation of the N layer.
第１図は絶縁ゲート型バイポーラトランジスタにおける
本発明の一実施例を示し、第２図と共通の部分には同一
の符号が付されている０図から明らかなように、ゲート
電極６の下のゲート絶縁膜５の下には、Ｎ−ベース層２
の表面部にＮ層１０が付加されている。このＮ層１０は
Ｎ−層２より不純物１度が高く、５ Ｘ １０■３／
ｃｃの濃度を有する。この層はＮ−Ｎ２の表面部に選択
的に形成してもよいが、例えばＰ″基板上にエピタキシ
ャル法で形成されたＮ−層２の上に不純物を濃くしたエ
ピタキシャル層として形成するか、あるいはＮ−Ｊｌの
表面部に全面に拡散により形成してもよい、Ｐ゛層１２
層３．Ｎ゛層４そのあとから形成する際には、このＮ層
１０の不純物濃度が著しく高くないため特に支障はない
。FIG. 1 shows an embodiment of the present invention in an insulated gate bipolar transistor. As is clear from FIG. 0, in which parts common to FIG. Under the gate insulating film 5, an N-base layer 2 is formed.
An N layer 10 is added to the surface portion of the substrate. This N layer 10 has a higher degree of impurity than the N− layer 2, and has an impurity ratio of 5×10■3/
It has a concentration of cc. This layer may be formed selectively on the surface of the N-N2 layer, but for example, it may be formed as an epitaxial layer with concentrated impurities on the N- layer 2 formed on the P'' substrate by an epitaxial method, or Alternatively, the P layer 12 may be formed on the entire surface of the N-Jl by diffusion.
Layer 3. When forming the N layer 4 thereafter, there is no particular problem since the impurity concentration of the N layer 10 is not extremely high.
第４図は縦型ＭＯ３ＦＥＴにおける本発明の別の実施例
を示し、第１図におけるＰ゛基板１の代わりにＮ・基板
１１を用いた他は絶縁ゲート型バイポーラトランジスタ
と同様である。FIG. 4 shows another embodiment of the present invention in a vertical MO3FET, which is similar to the insulated gate bipolar transistor except that an N substrate 11 is used instead of the P substrate 1 in FIG.
本発明によれば、絶縁ゲート型バイポーラトランジスタ
や縦型Ｍ ＯＳ Ｉｉ’ Ｅ ＴのようなＭＯ３型半導
体装！の高速化のために金などのライフタイムキラーを
導入するとき、ライフタイムキラーがアクセプタとして
働き、Ｎ−ベース層あるいはＮ−ドレイン層の表面層を
Ｐ転するのを防止するため、対向するチャネル領域間の
絶縁膜下の表面層を予めＮ−層より不純物濃度の高い層
としておく。これにより、Ｐ転によるターンオン異常、
オン電圧異常を防止することができる。According to the present invention, MO3 type semiconductor devices such as insulated gate bipolar transistors and vertical MOS Ii'ET! When a lifetime killer such as gold is introduced to increase the speed of The surface layer under the insulating film between the regions is made in advance to be a layer having a higher impurity concentration than the N- layer. As a result, turn-on abnormality due to P rotation,
On-voltage abnormalities can be prevented.
第１図は本発明の一実施例の絶縁ゲート型バイポーラト
ランジスタの要部断面図、第２図は従来の絶縁ゲート型
バイポーラトランジスタの要部断面図、第３図は第２図
のトランジスタにおける問題点の説明図で、ｆａｔは要
部断面図、ｌ′ｂ）は（ａｌのＸ−ＸｖＡに沿った断面
での電位分布図、第４図は本発明の別の実施例の縦型Ｍ
ＯＳ Ｆ Ｅ Ｔの要部断面図である。
１：Ｐｏ ドレイン層、ｌｌ：Ｎ” ドレイン層、２
：ベース層、３：チャネル層、４：ソース層、５：ゲー
トへ色録膜、６：ゲート電極、７：ソース第１１
（Ｑ）
（ｂ）
第３図
第４因
第２図FIG. 1 is a sectional view of a main part of an insulated gate bipolar transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of a main part of a conventional insulated gate bipolar transistor, and FIG. 3 is a problem with the transistor of FIG. 2. In the diagram, fat is a sectional view of the main part, l'b) is a potential distribution diagram in a cross section along X-XvA of (al), and FIG. 4 is a vertical type M of another embodiment of the present invention.
It is a sectional view of the main part of OS FET. 1: Po drain layer, ll: N” drain layer, 2
: Base layer, 3: Channel layer, 4: Source layer, 5: Color recording film to gate, 6: Gate electrode, 7: Source 11 (Q) (b) Figure 3, Factor 4, Figure 2
Claims (1)
一領域表面部に選択的に形成されたＰ形の第二領域と、
第二領域表面部に選択的に形成された高不純物濃度でＮ
形の第三領域とを有し、第三領域と第一領域の間の第二
領域をチャネル領域として対向するチャネル領域上にわ
たって絶縁膜を介してゲート電極が設けられ、一つの主
電極が第二領域および第三領域の表面に共通に接触する
ものにおいて、対向するチャネル領域の間の第一領域の
表面層がその層より下の第一領域の不純物濃度より高く
、５×１０＾１＾４／ｃｃ以下の不純物濃度をもつＮ形
の層であることを特徴とするＭＯＳ型半導体装置。1) at least an N-type first region with a low impurity concentration and a P-type second region selectively formed on the surface of the first region;
High impurity concentration selectively formed on the surface of the second region
a second region between the third region and the first region as a channel region, and a gate electrode is provided over the opposing channel regions with an insulating film interposed therebetween; In the case where the surface layer of the first region between the opposing channel regions is in common contact with the surfaces of the two regions and the third region, the impurity concentration is higher than the impurity concentration of the first region below that layer, and the impurity concentration is 5×10^1^ A MOS type semiconductor device characterized by being an N-type layer having an impurity concentration of 4/cc or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63233110A JP2768362B2 (en) | 1988-09-17 | 1988-09-17 | MOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63233110A JP2768362B2 (en) | 1988-09-17 | 1988-09-17 | MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0281476A true JPH0281476A (en) | 1990-03-22 |
| JP2768362B2 JP2768362B2 (en) | 1998-06-25 |
Family
ID=16949927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63233110A Expired - Lifetime JP2768362B2 (en) | 1988-09-17 | 1988-09-17 | MOS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2768362B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993012545A1 (en) * | 1991-12-09 | 1993-06-24 | Nippondenso Co. Ltd. | Vertical insulated gate semiconductor device and method for its manufacture |
| EP0615292A1 (en) * | 1993-03-10 | 1994-09-14 | Hitachi, Ltd. | Insulated gate bipolar transistor |
| JP2006237553A (en) * | 2004-09-02 | 2006-09-07 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| CN111697078A (en) * | 2020-06-29 | 2020-09-22 | 电子科技大学 | VDMOS device with high avalanche tolerance and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122175A (en) * | 1986-08-22 | 1987-06-03 | Nec Corp | Semiconductor device |
-
1988
- 1988-09-17 JP JP63233110A patent/JP2768362B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122175A (en) * | 1986-08-22 | 1987-06-03 | Nec Corp | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993012545A1 (en) * | 1991-12-09 | 1993-06-24 | Nippondenso Co. Ltd. | Vertical insulated gate semiconductor device and method for its manufacture |
| US5545908A (en) * | 1991-12-09 | 1996-08-13 | Nippondenso Co., Ltd. | Vertical type insulated-gate semiconductor device |
| EP0615292A1 (en) * | 1993-03-10 | 1994-09-14 | Hitachi, Ltd. | Insulated gate bipolar transistor |
| JP2006237553A (en) * | 2004-09-02 | 2006-09-07 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| CN111697078A (en) * | 2020-06-29 | 2020-09-22 | 电子科技大学 | VDMOS device with high avalanche tolerance and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2768362B2 (en) | 1998-06-25 |
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