JP2724204B2 - Conduction modulation type MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a lateral conductive modulation type MOSFET in which a drain, a source, and a gate are formed on one surface of a semiconductor wafer.

(Prior Art) FIG. 15 shows a main structure of a conventional lateral conductivity modulation type MOSFET. Semiconductor wafer, p to p ⁺ -type silicon substrate 1 ^- is used as a type layer 2 was epitaxially formed. A p-type base layer 7 is formed on the surface of the wafer, and an n ⁺ -type source layer 9 is selectively formed therein. An n ⁻ -type high-resistance base layer (drift layer) 4 and an n-type low-resistance base layer (buffer layer) 3 are formed adjacent to the p-type base layer 7. A p ⁺ -type drain layer 8 is formed on the surface of the n-type buffer layer 3. A region between the n ⁺ -type source layer 9 and the n ⁻ -type drift layer 4 of the p-type base layer 7 is used as a channel region, on which a gate electrode 6 is formed via a gate insulating film 5. The source electrode 10 is provided so as to contact the source layer 9 and the p-type base layer 7 at the same time.
Are in contact with the p ⁺ -type drain layer 8.

In this conductive modulation type MOSFET, when a positive bias is applied to the gate electrode 6 with respect to the source electrode 10, the surface (channel region) of the p-type base layer 7 below the gate electrode 6 is inverted and n ^{− −} Electrons are injected into the mold drift layer 4. When this electron current enters the drain layer 8 via the n-type buffer layer 3, the pn junction is forward-biased, so that holes from the drain layer 8 pass through the n-type buffer layer 3 and the n ⁻ -type drift layer 4 Is injected into. In this way, electrons and holes are accumulated in n ⁻ -type drift layer 4, and conductivity modulation occurs. Due to the effect of the conductivity modulation, the resistance of the n ⁻ -type drift layer 4 becomes substantially small at the time of ON, and a small ON voltage can be obtained.

When the gate electrode 6 is biased negative or zero with respect to the source electrode 10, the inversion layer in the channel region disappears and turns off.

In such a lateral conductive modulation type MOSFET, it is necessary to quickly eliminate carriers accumulated in the n-type base layer in order to increase the switching speed at the time of turn-off. If the electrons accumulated in the n-type base layer do not escape to the drain layer 8 side promptly, the pnp transistor composed of the p-type drain layer 8-n-type base layer 3, 4-p-type base layer 7 operates, and the large tail Current flows and the turn-off time becomes longer. One way to speed up the turn-off operation is to use n
The purpose is to shorten the carrier life in the mold base layer.
However, while this method improves the turn-off characteristics, it has a drawback that it increases the on-voltage of the device.

On the other hand, when the conduction modulation type MOSFET is used in the inverter circuit head of the motor drive circuit, diodes are connected in anti-parallel as shown in FIG. This is to regenerate the energy stored in the inductance component of the motor. However, the necessity of connecting the diode in this way causes an increase in the size of the device and an increase in cost.

To solve these problems, as shown in Figure 17,
The drain electrode 11 is partially formed by the n ⁺ -type layer 12 into the n-type buffer layer 3.
Has been proposed. This is called an anode short structure.

By employing this structure, at the time of turn-off, carriers accumulated in the n-type base layer are effectively discharged from the anode short-circuit portion, so that high-speed switching characteristics can be obtained. In addition, the introduction of the anode-should portion results in the parallel diode shown in FIG. 16 being built in the conduction modulation type MOSFET equivalently, eliminating the need to externally connect a diode.

However, when this anode short structure is adopted, the injection of holes from the p-type drain layer 8 to the n ⁻ -type base layer 1 is suppressed, so that the effect of conductivity modulation cannot be sufficiently obtained, and the ON voltage increases. I will. In order to cause conductivity modulation, it is necessary to sufficiently increase the lateral resistance of the n-type base layer of the drain layer. Specifically, it is conceivable to increase the width of the p ⁺ -type drain layer up to the short-circuit portion, reduce the impurity concentration of the n-type base layer, or reduce the thickness of the n-type base layer below the p-type drain layer. . However, this method increases the element area. In the methods (1) and (2), the breakdown voltage of the element is set low.

(Problems to be Solved by the Invention) As described above, in the conventional conduction modulation type MOSFET, in order to improve the switching characteristics at the time of turn-off, the ON voltage becomes high, and the conduction modulation type MOSFET employs an anode short circuit. If the effect of the above is to be made sufficient, there are problems such as an increase in the size of the element and a decrease in the withstand voltage.

The present invention solves such a problem by using a conductive modulation type MOSFET.
The purpose is to provide.

[Constitution of the Invention] (Means for Solving the Problems) The present invention firstly provides a lateral conductivity modulation type MOSFET which is adjacent to a second conductivity type base layer on which a first conductivity type drain layer is formed. In addition, a second conductivity type cathode layer provided with a pn junction separated from the second conductivity type base layer is provided, and a cathode electrode set to the same potential as the drain electrode is brought into contact with the cathode layer.

Secondly, the present invention employs an anode-short structure in which a drain electrode is partially contacted with a second conductivity type base layer in a lateral conductivity modulation type MOSFE, and a second conductivity type MOSFE sandwiched between the drain layer and the wafer region. A second gate electrode is provided on the surface of the conductive type base layer via a gate insulating film.

(Operation) According to the first invention, a substantial anode short-circuit structure is obtained only when a large current flows. For example, consider a case where the first conductivity type is p-type and the second conductivity type is n-type, and an n-type cathode layer is formed adjacent to the n-type base layer. When the device is turned on, electrons injected from the n-type source layer into the n-type base layer are absorbed by the p-type drain layer in a low injection state.
At this time, holes are injected from the drain layer to the n-type base layer, so that conduction modulation occurs. When the current increases and the state is increased, holes injected from the p-type drain layer into the n-type base layer run off the n-type base layer and are accumulated in the wafer. When the amount of accumulated holes in the wafer increases, electrons are injected from the n-type base layer into the wafer. At the time of turn-off, these electrons are easily discharged to the cathode layer set to the same potential as the drain layer. In this way, a substantial anode short structure is realized in the high injection state.

In addition, since the n-type base layer and the n-type cathode layer are separated from each other by a pn junction, there is no accompanying increase in the size of the element and a decrease in the breakdown voltage, unlike the conventional case of employing the anode short structure. Further, since the pn junction diode between the n-type cathode layer and the p-type base layer is equivalently anti-parallel to the conduction modulation MOSFET, it also has a reverse conduction function.

According to the second aspect, the anode-short structure is adopted on the drain side. However, when a bias is applied to the second gate electrode at the time of ON to form a channel on the surface of the second base layer, the drain layer is formed. Carrier injection into the wafer region from the substrate. Therefore, the disadvantage that the carrier injection efficiency from the drain layer at the time of ON is reduced due to the adoption of the anode short structure and the ON voltage is increased due to this is solved.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a cross-sectional view showing a main structure of a conduction modulation type MOSFET according to one embodiment. Parts corresponding to FIG. 15 which is a conventional example are denoted by the same reference numerals as in FIG. A wafer in which ap ⁺ (or n ⁺ or n ⁻ ) type silicon layer 1 is used as a substrate and a p ⁻ type layer 2 is epitaxially grown thereon is used. In this embodiment, a p type An n-type cathode layer 13 is provided on the surface of the p ⁻ -type layer 2 in a region facing the base layer 7, and a cathode electrode 15 is brought into ohmic contact with the surface of the n-type cathode layer 13 via the n ⁺ -type layer 14. I have. The cathode electrode 15 is connected to the drain electrode 11 so as to be given the same potential as the drain electrode.

The basic operation of this conduction modulation type MOSFET is the same as that of the conventional one. Turn-on is performed by applying a positive bias to the gate electrode 6 with respect to the source electrode 10, inverting the channel region on the surface of the p-type base layer 7, and injecting electrons from the source layer 9 into the n ⁻ drift layer 4. This electron current is n
When injected into the p-type drain layer 8 through the p-type buffer layer 3, the pn junction is forward-biased, resulting in holes from the p-type drain layer 8 to the n ⁻ -type drift layer 4 through the n-type buffer layer 3. Is injected. Thereby, conductivity modulation occurs in n ⁻ type drift layer 4. Due to the effect of the conductivity modulation, the resistance of the n ⁻ -type drift layer 4 can be substantially reduced, and a low on-state voltage can be obtained. When a large current flows, holes injected from p-type drain layer 8 run off n-type buffer layer 3 and n ⁻ -type drift layer 4 and are accumulated in p ⁻ -type layer 2. This gives n
Electronic type buffer layer 3 p ^- is poured into a mold layer 2, p ^- -type layer even conductive modulation occurs within 2.

When the gate electrode 6 is set to a negative bias or a zero bias with respect to the source electrode 10, the channel inversion layer below the gate electrode 6 disappears, and the electron injection from the source layer 9 stops. This turns off the device. In this case the device of this embodiment, p ^- the n-type cathode layer 13 on the surface of the mold layer 2 is provided, p ^- electrons accumulated in the mold layer 2 is rapidly from the n-type cathode layer 13 Is discharged. That is, substantially the same operation as in the anode short structure is performed, and the switching speed at the time of turn-off is high.

Thus, according to this embodiment, at the time of turn-on, the device operates in the same manner as the conventional device, and a low on-voltage characteristic can be obtained without increasing the device area or lowering the withstand voltage when the anode-short structure is adopted. . Moreover, at the time of turn-off, the n-type cathode layer substantially functions as an anode short circuit, and as a result, a high-speed turn-off characteristic is obtained. In the device of this embodiment, the p-type base layer 7-p ^- type layer 2-n
Since the diode composed of the mold cathode layer 13 enters the device in anti-parallel, it has a reverse conduction function without connecting an external diode.

Several other embodiments of the present invention will be described. In the following embodiments, portions corresponding to FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted.

FIG. 2 shows an embodiment in which the structure of FIG. 1 is slightly modified. The surface of the p ⁻ -type layer 2 between the n-type buffer layer 3 and the n-type cathode layer 13 is covered with an insulating film 16. The drain electrode 11 and the cathode electrode 15 are continuously formed integrally over the top 16.

In the embodiment shown in FIG. 3, the n ⁻ -type drift layer 4 is formed so as not to be in contact with the p-type base layer 7 but slightly away from the p-type base layer 7. As a result, a high reverse withstand voltage between the drain and the source can be obtained.

FIG. 4 shows a p ^- type layer 2 as a semiconductor wafer as a reference example.
With an extremely high resistance n
^- showing the element structure of a case of using a type layer 17 is epitaxially grown. In this case, if the n ⁻ -type layer 17 has a sufficiently high resistance, the n-type cathode layer 13 and the n-type buffer layer 3 are practically separated from each other, and the same effect as in the previous embodiment can be expected.

FIG. 5 shows an embodiment using a dielectric separation wafer.
That is, the portion above the p ⁺ -type layer 1 is the first silicon substrate, and the portion below the p ⁺ -type layer 1 is the second silicon substrate 21, both of which are mirror-polished. In the state in which the oxide film 18 is formed, they are integrated by a direct bonding technique. A groove is provided in the lateral element isolation region, and a polycrystalline silicon film 20 is buried therein with an oxide film 19 formed on an inner wall surface. Such a dielectric isolation wafer structure may of course be formed by a method such as embedding single crystal silicon in polycrystalline silicon, instead of the direct bonding technique of two substrates.

In the above embodiments, only the cross-sectional structure of the main part of the element has been shown.

6 (a) and 6 (b) are a plan view and an AA 'sectional view of an embodiment which embodies the structure of the embodiment of FIG. In this embodiment, the gate region is formed in an elongated ring, a p-type drain layer 8 is formed inside the gate region, and an n-type source layer 9 is formed outside in an elongated ring, and a region n surrounded by the drain layer 8 is formed. A mold cathode layer 13 is formed. The figure shows a part of one unit of a device formed in a stripe shape. In an actual device, a plurality of such unit devices are usually arranged.

FIG. 7 shows an embodiment in which the embodiment of FIG. 6 is slightly modified. In this embodiment, a plurality of cathode layers 13 ₁ , 13 ₂ ,... Are arranged in a region surrounded by the drain layer 8.

FIGS. 8A and 8B show an embodiment in which the relationship between the drain and the source is reversed from the embodiment shown in FIG. That is, the n-type source layer 9 is provided inside the p-type drain layer 8 forming an elongated ring.
Are arranged, and an n-type cathode layer 13 is arranged outside.

FIG. 9 shows an embodiment in which the embodiment of FIG. 8 is slightly modified, and an n-type cathode layer 13 is provided only on a linear portion of a unit element forming an elongated ring.

FIG. 10 is a further modification of the embodiment of FIG. 9, in which a plurality of n-type cathode layers 13 ₁ , 13 ₂ ,... Are arranged around a unit element.

According to these embodiments, the same effects as those of the previous embodiments can be obtained.

The present invention can be implemented with various modifications. For example, as shown in FIG. 11, the device of the present invention can be formed in a region A in a device wafer, and a conventional device can be formed in a region B. The semiconductor wafer is not limited to an epitaxial wafer, and a ZF wafer or a CZ wafer can be used as it is. The present invention is naturally effective even when the conductivity type of each part is reversed.

FIG. 12 shows still another embodiment. The gate electrode 6 formed on the surface of the p-type base layer 7 based on the embodiment of FIG.
Is used as a first gate electrode, and a second gate electrode is formed on the wafer surface between the drain layer 8 and the cathode layer 14 via a gate insulating film 22.
The gate electrode 23 is provided. The specific pattern of this structure can be the same as that described with reference to FIGS. In this case, the surface of the second gate electrode 23 is covered with an insulating film, and the drain electrode and the cathode electrode can be integrally formed thereover.

The basic operation of the conduction modulation type MOSFET of this embodiment is the same as that of FIG. In this embodiment, at the time of turn-on, a negative voltage is applied to the second gate electrode 23 with respect to the drain electrode. As a result, the surface of the n-type buffer layer 3 under the second gate electrode 23 is inverted to form a channel, and the drain layer 8
Holes are directly injected into the p ^-- type layer 2 from. As a result, the effect of the conductivity modulation becomes greater, and a lower ON voltage can be obtained. At the time of turn-off, the second gate electrode 23 has a positive or zero bias. This embodiment can be variously modified as follows. For example, a dielectric separation wafer may be used as the wafer, or the drain electrode 11 and the cathode electrode 15 may be integrally formed (when the arrangement relation of the source layer, the drain layer, and the cathode layer is in the case of FIG. 8).

FIG. 13 is slightly different from the embodiments described so far. Compared with the embodiment of FIG. 1, firstly, it differs in that an anode short structure is adopted on the drain side.
That is, a short-circuit portion 24 in which a part of the drain electrode 11 contacts the n-type buffer layer 3 is formed. And the second
No cathode layer is provided, and a gate insulating film is formed in a region between the drain layer 8 and the p ⁻ -type layer 2 on the surface of the n-type buffer layer 3.
A second gate electrode 23 is provided via 22.

Also in the case of the conduction modulation type MOSFET of this embodiment, similarly to the embodiment of FIG. 12, a negative bias is applied to the second gate electrode 23 at the time of turn-on. Thus, as in the embodiment of FIG. 12, holes are injected from the drain layer 8 into the p ⁻ -type layer 2 through the surface channel below the second gate electrode 23 at the time of ON, and a large conductivity modulation effect is obtained. The reverse conduction function is such that the n-type buffer layer 3-n ⁻ -type drift layer 4-
This is performed by using a pn junction diode including the p-type base layer 7.

The embodiment of FIG. 13 solves the problem that the efficiency of hole injection from the drain layer at the time of ON when the anode short structure is adopted is reduced by a different structure from the embodiment of FIG. You can say that. In this embodiment, a dielectric isolation wafer may be used as the wafer.

FIG. 14 is an embodiment in which the embodiment of FIG. 12 and the embodiment of FIG. 13 are combined. Although the description of the operation is omitted, this embodiment can provide the same effects as those of the previous embodiments. In this embodiment, as in the case of the structure in FIG. 12,
The patterns described with reference to FIGS. 6 to 8 can be used. Further, a dielectric separation wafer can be used as the wafer.

[Effects of the Invention] As described above, according to the present invention, an anode-short structure is adopted by providing an n-type cathode layer maintained at the same potential as a drain layer independently of an n-type base layer. To solve the above-mentioned problem, it is possible to obtain a high-speed turn-off characteristic while maintaining a low on-voltage without causing an increase in element area and a decrease in withstand voltage, and to realize a conductive modulation MOSFET having a reverse conduction function. .

According to the invention, an anode short structure is adopted on the drain side, and a second gate electrode is provided via a gate insulating film on the second conductivity type base layer sandwiched between the drain layer and the wafer region, and the turn-on operation is performed. When the channel is formed under the second gate electrode, carriers can be directly injected from the drain layer into the wafer region, thereby solving the problem of adopting the anode short structure and keeping the ON voltage low. In addition, a high-speed turn-off characteristic can be obtained, and a conduction modulation type MOSFET having a reverse conduction function can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing the structure of a principal part of a conductive modulation type MOSFET according to one embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conductive modulation type MOSFET according to another embodiment, and FIG. FIG. 4 is a cross-sectional view showing the structure of a principal part of a conductive modulation type MOSFET of FIG. 4, FIG. 4 is a sectional view showing the structure of a principal part of a conductive modulation type MOSFET as a reference example, and FIG. 6 (a) and 6 (b) are plan views and an AA 'cross-sectional view of an embodiment of the embodiment of FIG. 2 which is a more concrete example, and FIG. 7 is a sectional view of FIG. Modified conductivity type of the embodiment of the embodiment
FIGS. 8 (a) and 8 (b) are plan views showing a MOSFET, and FIG.
FIGS. 9 and 10 are plan views showing an embodiment of the conduction modulation type MOSFET which is a modification of the embodiment shown in FIG. 8, and FIG. FIG. 12 is a cross-sectional view showing a conductive modulation type MOSFET according to an embodiment. FIG. 12 is a conductive modulation type MO according to an embodiment provided with a second gate electrode.
FIG. 13 is a cross-sectional view showing a main part structure of an SFET. FIG. 13 is a cross-sectional view showing a main part structure of a conductive modulation type MOSFET according to an embodiment in which a similar problem is solved without providing a cathode layer. FIG. 13 is a cross-sectional view showing a main part structure of a conductive modulation type MOSFET according to an embodiment in which the configuration of FIG. 13 is combined, FIG. 15 is a cross-sectional view showing a main part structure of a conventional conductive modulation type MOSFET, and FIG. FIG. 17 is a cross-sectional view showing a main structure of another conventional conduction modulation type MOSFET. 1 ... p-type silicon layer, 2 ... p ^- type layer, 3 ... n-type buffer layer (low-resistance n-base layer), 4 ... n ^- type drift layer (high-resistance n-base layer), 5 ... Gate insulating film, 6 gate electrode (first gate electrode), 7 p-type base layer, 8
p-type drain layer, 9 ... n-type source layer, 10 ... source electrode, 11 ... drain electrode, 13 ... n-type cathode layer, 14 ...
... n ⁺ type layer, 15 ... cathode electrode, 16 ... insulating film, 17 ...
n ^- -type layer, 18, 19 ...... element isolation oxide film, 20 ...... polycrystalline silicon, 21 ...... silicon substrate, 22 ...... gate insulating film, 23 ...
... Second gate electrode.

Claims (10)

(57) [Claims] 1. A semiconductor wafer, a first conductivity type base layer selectively formed on a surface of the semiconductor wafer, and a second conductivity type selectively formed on a surface of the first conductivity type base layer.
A conductive type source layer; a second conductive type base layer selectively formed on the semiconductor wafer; a first conductive type drain layer formed on the surface of the second conductive type base layer; A gate electrode formed on a surface of the first conductive type base layer in a region interposed between the second conductive type base layers via a gate insulating film; and a source electrode and a first conductive type base layer provided at the same time. A source electrode, a drain electrode disposed in contact with the drain layer, and a pn junction separated from the second conductive type base layer adjacent to the second conductive type base layer and the semiconductor wafer. A conductive modulation type MOSFET, comprising: a second conductivity type cathode layer formed on the surface; and a cathode electrode set to the same potential as the drain electrode formed on the cathode layer surface. 2. A semiconductor wafer, a first conductivity type base layer selectively formed on a surface of the semiconductor wafer, and a second conductivity type selectively formed on a surface of the first conductivity type base layer.
A conductive type source layer; a second conductive type base layer selectively formed on the semiconductor wafer; a first conductive type drain layer formed on the surface of the second conductive type base layer; A first gate electrode formed on a surface of the first conductive type base layer in a region sandwiched by the second conductive type base layer via a gate insulating film, and simultaneously contacting the source layer and the first conductive type base layer; A source electrode provided, a drain electrode provided in contact with the drain layer, and a pn junction separated from the second conductivity type base layer adjacent to the second conductivity type base layer, and A second conductivity type cathode layer formed on the surface of the semiconductor wafer; a cathode electrode set to the same potential as the drain electrode formed on the cathode layer surface; and a second electrode sandwiched between the drain layer and the cathode layer. Conductive type And a second gate electrode formed on the surface of the source layer via a gate insulating film. 3. A semiconductor wafer, a first conductivity type base layer selectively formed on the surface of the semiconductor wafer, and a second conductivity type selectively formed on the surface of the first conductivity type base layer.
A conductive type source layer; a second conductive type base layer selectively formed on the semiconductor wafer; a first conductive type drain layer formed on the surface of the second conductive type base layer; A first gate electrode formed on a surface of the first conductive type base layer in a region sandwiched by the second conductive type base layer via a gate insulating film, and simultaneously contacting the source layer and the first conductive type base layer; A source electrode provided, a drain electrode provided in contact with the drain layer and the second conductivity type base layer at the same time, and a second conductivity type base layer surface interposed between the drain layer and the semiconductor wafer region. The second formed through the gate insulating film
A conductive modulation type MOSFET, comprising: a gate electrode; 4. A semiconductor wafer, a first conductivity type base layer selectively formed on a surface of the semiconductor wafer, and a second conductivity type selectively formed on a surface of the first conductivity type base layer.
A conductive type source layer; a second conductive type base layer selectively formed on the semiconductor wafer; a first conductive type drain layer formed on the surface of the second conductive type base layer; A first gate electrode formed on a surface of the first conductive type base layer in a region sandwiched by the second conductive type base layer via a gate insulating film, and simultaneously contacting the source layer and the first conductive type base layer; A source electrode provided, a drain electrode provided in contact with the drain layer and the second conductivity type base layer at the same time, and a second conductivity type base layer adjacent to the second conductivity type base. Is a pn junction-separated cathode layer of the second conductivity type formed on the surface of the semiconductor wafer; a cathode electrode set to the same potential as the drain electrode formed on the surface of the cathode layer; and the drain layer and the cathode. A second conductive type base layer formed on the surface of the second conductive type base layer in a region between the layers via a gate insulating film;
A conductive modulation type MOSFET, comprising: a gate electrode; 5. An insulating film is provided on a surface of a semiconductor wafer between the second conductivity type base layer and the cathode layer, and the drain electrode and the cathode electrode are formed integrally over the insulating film. The conductive modulation type MOSF according to claim 1.
ET. 6. The semiconductor wafer according to claim 1, wherein a semiconductor layer in an element region is formed on the semiconductor substrate by dielectric isolation on a semiconductor substrate. Or a conductive modulation type MOSFET according to any one of the above. 7. A gate region is formed as a ring, a source layer is formed outside the ring, a drain layer is formed inside the ring, and the cathode layer is formed inside the drain layer. The conductive modulation type MOSFET according to any one of claims 1, 2 and 4, wherein: 8. The semiconductor device according to claim 1, wherein a gate region is formed in a ring, a source layer is formed inside the ring, a drain layer is formed outside the ring, and the cathode layer is formed outside the drain layer. A conductive modulation type MOSFET according to any one of claims 1, 2 and 4. 9. The method according to claim 2, wherein an insulating film is provided on the surface of the second gate electrode, and the drain electrode and the cathode electrode are formed integrally over the insulating film. Conduction modulation type MOSFET. 10. A gate region is formed in a ring shape, a source layer is formed inside the ring, a drain layer is formed inside the ring, and a second gate electrode is formed inside the ring. The conductive modulation type MOSFET according to claim 7, wherein: