JPH02224274A - Conductivity modulation type mos fet - Google Patents

Abstract

PURPOSE:To realize an anode short-circuit structure and hence keep on-voltage at a low level without causing an increased device area and reduced withstand voltage by providing an n-type cathode layer kept at the same potential as that of a drain layer independent of an n-type base layer. CONSTITUTION:A second conductivity type cathode layer 13, that adjoins to a second conductivity type base layer 3 including a first conductivity type drain layer 8 formed thereon, and that is isolated from the second conductivity type base layer 3 via a pn junction, is provided, with which cathode layer 13 a cathode electrode, that is set at the same potential as that of a drain electrode 11, that is set at the same potential as that of a drain electrode 11, is allowed to make contact. Hereby, a substantially anode short-circuit structure is realized in its high injection state. Further, since the n-type base layer 3 and the n-type cathode layer 13 are separated from each other via a pn junction, low ionic potential characteristic is assured without causing an increased device area and lowered withstand voltage.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a horizontal conductivity modulation type MOSFET in which a drain, a source, and a gate are formed on one side of a semiconductor wafer.
Regarding T.

(Prior Art) FIG. 15 shows the main structure of a conventional horizontal conduction modulation type MO3FET. The semiconductor wafer is p1
A type silicon substrate 1 on which a p-type layer 2 is epitaxially formed is used. An n-type base layer 7 is formed on the surface of this wafer, and an n+-type source layer 9 is selectively formed therein. Further, adjacent to the n-type base layer 7, a low-type high-resistance base layer (drift layer) 4 and an n-type low-resistance base layer (
A buffer layer) 3 is formed. A p + -type drain layer 8 is formed on the surface of the n-type buffer layer 3 . A region of the n-type base layer 7 sandwiched between the n1-type source layer 9 and the low-type drift layer 4 is used as a channel region, and a gate electrode 6 is formed thereon with a gate insulating film 5 interposed therebetween. The source electrode 10 is placed in contact with the source layer 9 and the n-type base layer 7 at the same time, and the drain electrode 11 is placed in contact with the p + -type drain layer 8 .

In this conductivity modulation type MO8FET, when a positive bias is applied to the gate electrode 6 with respect to the source electrode 10, the surface of the n-type base layer 7 under the gate electrode 6 (channel region)
is reversed, and electrons are injected from the source layer 9 into the n-type drift layer 4. When this electron current enters the drain layer 8 via the n-type buffer layer 3, the pn junction is forward biased, and holes from the drain layer 8 pass through the n-type buffer layer 3 to the n-type drift layer 8. is injected into. In this way, electrons and holes are accumulated in the n-type drift layer 4, causing conductivity modulation. Due to the effect of this conductive modulation, when on, n-
The resistance of the mold drift layer 4 becomes substantially small, and a small on-voltage can be obtained.

By biasing the gate electrode 6 negative or zero with respect to the source electrode 10, the inversion layer in the channel region disappears and is turned off.

In such a horizontal conduction modulation type MO8FET, in order to increase the switching speed at turn-off, 1.
It is necessary to quickly eliminate the carriers accumulated in the mold base layer. If the electrons accumulated in the n-type base layer do not quickly escape to the drain layer 8 side, the p-type drain layer 8-
n-type base layer 3゜4-n-type base layer 7 pnp)
The transistor operates, with a large tail current flowing and a long turn-off time. One way to speed up the turn-off operation is to reduce the carrier lifetime in the n-type base layer. However, although this method improves the turn-off characteristics, it has the drawback of increasing the on-voltage of the device.

On the other hand, when the conductivity modulation type MO3FET is used in an inverter circuit of a motor drive circuit, etc., diodes are connected in antiparallel as shown in FIG. 16. This is to regenerate the energy stored in the inductance component of the motor.

However, having to connect the diodes in this manner increases the size and cost of the device.

In order to solve these problems, as shown in Figure 17,
A structure has been proposed in which the drain electrode 11 is partially short-circuited to the n-type buffer layer 3 by the n+-type layer 12. This is called an anode competition short structure.

If this structure is adopted, carriers accumulated in the n-type base layer are effectively discharged from the anode short portion at turn-off, so that high-speed switching characteristics can be obtained. Further, by introducing this anode short section, a parallel diode shown in FIG. 16 is equivalently built into the conduction modulation type MOSFET, and there is no need to connect a diode externally.

However, when this anode short structure is adopted, the injection of holes from below the p-type drain layer to the n-type base layer 1 is suppressed, so the conductivity modulation effect is not sufficiently obtained and the on-state voltage becomes high. Put it away. In order to cause conductivity modulation, it is necessary to make the lateral resistance of the n-type base layer of the drain layer sufficiently large. Specifically, ■ increasing the width of the p+ type layer up to the short circuit, ■ lowering the impurity concentration of the n type base layer, ■ decreasing the thickness of the n type base layer under the p type drain layer, etc. Conceivable. However, method (2) requires a large element area. Methods (1) and (2) lower the withstand voltage of the element.

(Problems to be Solved by the Invention) As described above, in the conventional conduction modulation type MO3FET, when trying to improve the switching characteristics at turn-off, the on-voltage becomes high, and the conduction modulation type MO3FET adopts an anode short structure and conductivity modulation. If an attempt is made to achieve a sufficient effect, there are problems such as an increase in the size of the device and a decrease in breakdown voltage.

The present invention is a conductive modulation type MOSF that solves these problems.
The purpose is to provide ET.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides, firstly, a lateral conductivity modulation type MO9FET in which a drain layer of a first conductivity type is adjacent to a base layer of a second conductivity type on which a drain layer of a first conductivity type is formed. In addition, a second conductivity type cathode layer separated from the second conductivity type base layer by a pn junction is provided, and a cathode electrode set to the same potential as the drain electrode is brought into contact with this cathode layer.

Second, the present invention adopts an anode short structure in which the drain electrode is partially in contact with the second conductivity type base layer in a lateral conductivity modulation type MOSFET, and the drain electrode is sandwiched between the drain layer and the wafer region. It is characterized in that a second gate electrode is provided on the surface of the second conductive i-type base layer with a gate insulating film interposed therebetween.

(Function) According to the first invention, a substantial anode short structure is formed only when a large current flows. For example, consider a case where the first conductivity type is p type, the second conductivity type is n type, and an n type cathode layer is formed adjacent to an n type base layer. When this element is turned on, electrons injected from the n-type source layer to the n-type base layer are absorbed by the p-type drain layer in a low injection state. At this time, holes are injected from the drain layer to the n'J1 base layer, causing conductivity modulation. When the current increases to a high injection state, holes injected from the p-type drain layer to the n-type base layer leak out of the nu base layer and accumulate in the wafer. When the amount of accumulated holes in the wafer increases, electrons are injected into the wafer from the n-type base layer. At turn-off, these electrons are simply discharged to the cathode layer set at the 78th position, which is the same as the drain layer. In this way, a substantial anode short structure is achieved under high injection conditions.

Moreover, since the n-type base layer and the n-type cathode layer are separated by a pn junction, unlike the case where the conventional anode ◆ short structure is adopted, there is no increase in the size of the device or a decrease in breakdown voltage. Also, pn between the n-type cathode layer and the p-type base layer
Since the junction diode is equivalently connected in antiparallel to the conduction modulation MOSFET, it also has a reverse conduction function.

According to the second invention, an anode short structure is adopted on the drain side, and by applying a bias to the second gate electrode when turned on and forming a channel on the surface of the second base layer, the drain layer This allows sufficient carrier injection into the wafer region. Therefore, the disadvantages of a decrease in carrier injection efficiency from the drain layer during on-time and an increase in on-voltage due to the adoption of the anode short structure can be solved.

(Example) Two aspects of the present invention will be described in detail below.

FIG. 1 is a cross-sectional view showing the main structure of a conductivity modulation type MOSFET according to an embodiment. The same reference numerals as in FIG. 15 are given to parts corresponding to those in FIG. 15, which is a conventional example. A wafer is used in which a p'' (or n+ or n-) type silicon layer 1 is used as a substrate and a p'' type layer 2 is epitaxially grown thereon.
An n-type cathode layer 13 is provided on the surface of the p- type layer 2 in a region facing the p-type base layer 7 across the n-type buffer layer 3, and an n+-type layer 14 is provided on the surface of the n-type cathode layer 13. The cathode electrode 15 is in ohmic contact.

The cathode electrode 15 is connected to the drain electrode 11 and is given the same potential as the drain electrode.

The basic operation of this conductivity modulation type MO5FET is the same as the conventional one. Turn-on is performed by applying a positive bias to the gate electrode 6 with respect to the source electrode 10, inverting the channel region on the surface of the p-type base layer 7, and injecting electrons from the source layer 9 into the n-type drift layer 4. . When this electron current is injected into the p-type drain layer 8 via the n-type buffer layer 3, the p-n junction is forward biased.
Holes are injected into the 6th layer 4. This causes conductivity modulation within the n-type drift layer 4. Due to the effect of this conductivity modulation, the resistance of the n-type drift layer 4 can be substantially reduced,
Low on-voltage can be obtained. When a large current flows, holes injected from the p-type drain layer 8 leak out of the n-type buffer layer 3 and the n-type drift layer 4 and are accumulated in the p-type layer 2.

As a result, electrons in the n-type buffer layer 3 are also injected into the p-type layer 2, causing conductivity modulation within the p-type layer 2 as well.

When the gate electrode 6 is set at a negative bias or zero bias with respect to the source electrode 10, the channel inversion layer under the gate electrode 6 disappears, and electron injection from the source layer 9 disappears. This turns off the device. At this time, in the device of this embodiment, since the n-type cathode layer 13 is provided on the surface of the p-type layer 2, the electrons accumulated in the p-type layer 2 are quickly released from this n-type cathode layer 13. is discharged. That is, the operation is substantially the same as that of the anode short structure, and the switching speed at turn-off is fast.

In this way, according to this embodiment, when turned on, it operates in the same way as a conventional element, and low on-voltage characteristics can be obtained without increasing the element area or reducing withstand voltage when an anode short structure is adopted. . Furthermore, at turn-off, the n-type power/sode layer acts as a substantial anode short, resulting in high-speed turn-off characteristics. In addition, in the device of this embodiment, the p-type base layer 7-p-type layer 2-
Since the diode consisting of the n-type cathode layer 13 is inserted in antiparallel to the element, it has a reverse conduction function without connecting a diode externally.

Some other embodiments of the invention will be described. In the following embodiments, parts corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1, and detailed explanations will be omitted.

FIG. 2 shows an embodiment in which the structure of FIG. 1 is slightly modified, and the surface of the p-type layer 2 between the n-type buffer layer 3 and the n-type cathode layer 13 is covered with an insulating film 16. 16, the drain electrode 11 and cathode electrode 15 are continuously formed integrally.

In the embodiment shown in FIG. 3, the n-type drift layer 4 is formed not in contact with the p-type base layer 7, but slightly separated from the p-type base layer 7. As a result, a device with a high reverse breakdown voltage between the drain and source can be obtained.

FIG. 4 shows an embodiment using a semiconductor wafer in which a p-type layer 2 is epitaxially grown and an extremely high resistance n-type layer 17 is further epitaxially grown.

In the case of this embodiment, if the n-type layer 17 has a sufficiently high resistance, the n-type cathode layer 13 and the n-type buffer layer 3 are effectively separated, so the same effect as in the previous embodiment can be expected. .

FIG. 5 shows an example using a dielectrically separated wafer. That is, the part above the p+ type layer 1 is the first silicon substrate, and the part below is the second silicon substrate 21, both of which are mirror polished, and a dielectric film for isolation is formed on these surfaces. With the oxide film 18 formed, they are integrated by direct bonding technology.

A trench is provided in the lateral element isolation region, and a polycrystalline silicon film 20 is buried inside the trench with an oxide film 19 formed on the inner wall surface. Such a dielectrically isolated wafer structure is
Of course, instead of using the technique of directly bonding two substrates, it may be formed by, for example, embedding single crystal silicon in polycrystalline silicon.

In the above embodiments, only the cross-sectional structure of the main part of the element was shown, but the layout and cross-sectional structure of some embodiments to which the present invention is more specifically applied will be shown.

FIGS. 6(a) and 6(b) are a plan view and a sectional view taken along the line AA' of an embodiment that embodies the structure of the embodiment shown in FIG. In this embodiment, the gate region is formed in the form of an elongated ring, and a p-type drain layer 8 is formed inside the gate region, and an n-type source layer 9 is formed outside the gate region in the form of an elongated ring, and a region n surrounded by the drain layer 8 is formed. A type cathode layer 13 is formed. The figure shows a part of one unit of an element formed in a stripe shape, and in an actual element, a plurality of such unit elements are usually arranged.

FIG. 7 shows a slightly modified embodiment of the embodiment shown in FIG. In this embodiment, a plurality of cathode layers 131, 13□ are provided in the region surrounded by the drain layer 8.

...is placed.

Figures 8(a) and 8(b) show the relationship between the drain and source as shown in the sixth figure.
This is an embodiment reversed from the embodiment shown in the figure.

The inside of the p-type drain layer 8 forming an elongated ring is
A type source layer 9 is arranged, and an n-type cathode layer 13 is arranged on the outside.

FIG. 9 shows a slightly modified embodiment of the embodiment shown in FIG. 8, in which an n-type cathode layer 13 is provided only on the linear portion of a unit element forming an elongated ring.

FIG. 10 shows an embodiment that is a further modification of the embodiment shown in FIG. 9, and includes a plurality of n-type cathode layers 131, 13□.

... are arranged around a unit element.

These embodiments also provide the same effects as those of the previous embodiments.

The present invention can be further modified and implemented in various ways. For example, as shown in FIG. 11, it is possible to form the device of the present invention in region A of the device wafer and to form a conventional device in region B.

The semiconductor wafer is not limited to an epitaxial wafer; it is also possible to use an FZ wafer or a CZ wafer as is. The present invention is naturally effective even when the conductivity type of each part is reversed.

FIG. 12 shows yet another embodiment. Gate electrode 6 formed on the surface of p-type base layer 7 based on the embodiment shown in FIG.
is used as a first gate electrode, and in addition to this, a second gate electrode 23 is provided on the wafer surface between the drain layer 8 and the cathode layer 14 with a gate insulating film 22 interposed therebetween. The specific pattern of this structure can also be the same as that explained in FIGS. 6 to 8. In this case, the surface of the second gate electrode 23 can be covered with an insulating film, and the drain electrode and the cathode electrode can be integrally formed by passing over the insulating film.

The basic operation of the conductivity modulated MO3FET of this embodiment is the same as that shown in FIG. In this embodiment, when turned on, a negative voltage is applied to the second gate electrode 23 with respect to the drain electrode. As a result, the surface of the n-type buffer layer 3 under the second gate electrode 23 is inverted to form a channel, and holes are directly injected from the drain layer 8 into the p-type layer 2. As a result, the effect of conductivity becomes greater, and a lower on-voltage can be obtained. At turn-off, the second gate electrode 23 has a positive or zero bias.

FIG. 13 is a little different from the embodiments described so far. When compared with the embodiment shown in FIG. 1, the first difference is that an anode short structure is adopted on the drain side.

That is, a part of the drain electrode 11 is connected to the n-type buffer layer 3.
A short-circuit portion 24 is formed to contact the. Second, a cathode layer is not provided, and a second gate electrode 23 is provided in a region sandwiched between the drain layer 8 and the p-type layer 2 on the surface of the n-type buffer layer 3 with a gate insulating film 22 interposed therebetween.

Also in the case of the conductivity modulation type MOSFET of this example, the 12th
Similarly to the embodiment shown in the figure, the second gate electrode 2
Give negative bias to 3. As a result, like the embodiment shown in FIG. 12, holes are injected from the drain layer 8 into the p-type layer 2 through the surface channel under the second gate electrode 23 when turned on, and a large conductivity modulation effect can be obtained. The reverse conduction function is achieved by the n-type buffer layer 3-n- short-circuited with the drain electrode 11.
A pn junction diode consisting of a type drift layer 4 and a p-type base layer 7 is used.

The embodiment shown in FIG. 13 solves the problem of reduced hole injection efficiency from the drain layer when on when an anode short structure is adopted by using a different configuration from the embodiment shown in FIG. 1. You can say that.

FIG. 14 is an embodiment in which the embodiment of FIG. 12 and the embodiment of FIG. 13 are combined. Although the explanation of the operation will be omitted, this embodiment also provides the same effects as those of the previous embodiments.

[Effects of the Invention] As described above, according to the present invention, by providing an n-type cathode layer that is kept at the same potential as the drain layer independently of the n-type base layer, when an anode short structure is adopted. By solving this problem, it is possible to maintain a low on-voltage and obtain high-speed turn-off characteristics without increasing the device area or reducing breakdown voltage, and it is possible to realize a conduction modulation type MO3FET that also has a reverse conduction function. .

Further, according to the present invention, an anode short structure is adopted on the drain side, and a second conductivity type base layer is provided on the second conductivity type base layer sandwiched between the drain layer and the wafer region via the gate insulating film.
A gate electrode is provided, and when turned on, this second gate 7ti
By forming a channel at the very bottom, direct carrier injection from the drain layer to the wafer region solves the problem of adopting an anode short structure, keeping the on-voltage low and achieving high-speed turn-off characteristics. Furthermore, it is possible to realize a conduction modulation type MO3FET having a reverse conduction function.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the main structure of a conductivity modulation type MOSFET according to an embodiment of the present invention. FIG. 2 is a sectional view showing a conductivity modulation type MO3FET of another embodiment. FIG. 3 is a sectional view showing the main structure of a conductivity modulation type MOSFET according to another embodiment. FIG. 4 is a sectional view showing the main structure of a conductivity modulation type MO3FET according to another embodiment. FIG. 5 is a sectional view showing the main structure of a conductivity modulation type MOSFET according to another embodiment. 6(a) and 6(b) are a plan view and a sectional view taken along the line AA' of the embodiment shown in FIG. 2, and FIG. 7 is a modification of the embodiment shown in FIG. 6. Conductivity: A type MO3FET
8(a) and 8(b) are plan views showing conductive modulation of yet another embodiment! ! ! Plan view showing MO8FET and its A-A
' Cross-sectional view, Figures 9 and 10 are plan views showing a conduction modulation type MO3FET of an example modified from the example shown in Figure 8, Figure 11 is a cross section showing a conduction modulation type MO8FET of still another example. Figure 12 is a cross-sectional view showing the main part structure of a conductivity modulation type MOSFET of an example in which a second gate electrode is provided, and Figure 13 is a cross-sectional view showing a conductivity modulation type MOSFET of an example in which a cathode layer is not provided and the same problem is solved. 14 is a cross-sectional view showing the structure of a main part of a modulation type MOSFET; FIG. 16 is a sectional view showing the structure of a main part of a conventional conduction modulation type MO3FET, FIG. 16 is an equivalent circuit diagram thereof, and FIG. 17 is a sectional view showing the structure of a main part of another conventional conduction modulation type MO3FET. 1...p-type silicon layer, 2...p-type layer, 3...
・N-type buffer layer (low resistance n base layer), 4...n~
(type drift layer high resistance n base layer) 5... Gate insulating film, 6... Gate electrode (first gate electrode), 7-...
p-type base layer, 8... p-type drain layer, 9... n-type source layer, 10... source electrode, 11... drain electrode, 13... n-type cathode layer, 14... n+ type layer, 15... cathode electrode, 16... insulating film, 17.
...n-type layer, 18.19...element isolation oxide film, 20
... Polycrystalline silicon, 21 ... Silicon substrate, 22
. . . gate insulating film, 23 . . . second gate electrode.

Claims (10)

[Claims] (1) A semiconductor wafer, a first conductivity type base layer selectively formed on the surface of this semiconductor wafer, and a second conductivity type base layer selectively formed on the surface of this first conductivity type base layer.
a conductivity type source layer; a second conductivity type base layer selectively formed on the semiconductor wafer; a first conductivity type drain layer formed on the surface of the second conductivity type base layer; the source layer; A gate electrode formed on the surface of the first conductive type base layer in a region sandwiched between the second conductive type base layers via a gate insulating film, and disposed in simultaneous contact with the source layer and the first conductive type base layer. a drain electrode disposed in contact with the drain layer; a second conductivity type cathode layer formed on the semiconductor wafer surface adjacent to the second conductivity type base layer; A conductivity modulation type MOSFET comprising a cathode electrode set to the same potential as the drain electrode formed on the surface of the cathode layer. (2) a semiconductor wafer; a first conductivity type base layer selectively formed on the surface of the semiconductor wafer; and a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer.
a conductivity type source layer; a second conductivity type base layer selectively formed on the semiconductor wafer; a first conductivity type drain layer formed on the surface of the second conductivity type base layer; the source layer; A first gate electrode formed on the surface of the first conductivity type base layer in a region sandwiched between the second conductivity type base layers via a gate insulating film, and simultaneously contacting the source layer and the first conductivity type base layer. a source electrode disposed; a drain electrode disposed in contact with the drain layer; a second conductivity type cathode layer formed on the semiconductor wafer surface adjacent to the second conductivity type base layer; , a cathode electrode set to the same potential as the drain electrode formed on the surface of the cathode layer, and a gate insulating film formed on the surface of the second conductivity type base layer sandwiched between the drain layer and the cathode layer. A conductivity modulation type MOSFET comprising: a second gate electrode; (3) a semiconductor wafer; a first conductivity type base layer selectively formed on the surface of the semiconductor wafer; and a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer.
a conductivity type source layer; a second conductivity type base layer selectively formed on the semiconductor wafer; a first conductivity type drain layer formed on the surface of the second conductivity type base layer; the source layer; A first gate electrode formed on the surface of the first conductivity type base layer in a region sandwiched between the second conductivity type base layers via a gate insulating film, and simultaneously contacting the source layer and the first conductivity type base layer. a source electrode disposed, a drain electrode disposed in simultaneous contact with the drain layer and the second conductivity type base layer, and a surface of the second conductivity type base layer sandwiched between the drain layer and the semiconductor wafer region. A conductivity modulation type MOSFET, comprising: a second gate electrode formed through a gate insulating film. (4) a semiconductor wafer; a first conductivity type base layer selectively formed on the surface of the semiconductor wafer; and a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer.
a conductivity type source layer; a second conductivity type base layer selectively formed on the semiconductor wafer; a first conductivity type drain layer formed on the surface of the second conductivity type base layer; the source layer; A first gate electrode formed on the surface of the first conductivity type base layer in a region sandwiched between the second conductivity type base layers via a gate insulating film, and simultaneously contacting the source layer and the first conductivity type base layer. a source electrode disposed, a drain electrode disposed in simultaneous contact with the drain layer and the second conductivity type base layer, and a drain electrode formed on the semiconductor wafer surface adjacent to the second conductivity type base layer. a cathode layer of a second conductivity type, a cathode electrode set to the same potential as the drain electrode formed on the surface of the cathode layer, and a base layer of a second conductivity type in a region sandwiched between the drain layer and the cathode layer. A conductivity modulation type MOSFET comprising: a second gate electrode formed on the surface with a gate insulating film interposed therebetween. (5) An insulating film is provided on the surface of the semiconductor wafer between the second conductivity type base layer and the cathode layer, and the drain electrode and the cathode electrode are integrally formed passing over this insulating film. Conductivity modulation type MOSFE according to 1.
T. (6) The conductivity modulation type MOSFET according to any one of claims 1, 2, 3, or 4, wherein the semiconductor wafer is dielectrically isolated on a semiconductor substrate to form a semiconductor layer in an element region. . (7) A gate region is formed in a ring, a source layer is formed on the outside of the ring, a drain layer is formed in a ring on the inside, and the cathode layer is formed inside the drain layer. Claim 1 characterized in that:
Conductivity modulation type MOSFET according to any one of 2 or 4
. (8) Claim characterized in that the gate region is formed in the form of a ring, a source layer is formed inside the ring, a drain layer is formed outside the ring, and the cathode layer is formed outside the drain layer. 5. The conductivity modulation type MOSFET according to any one of 1, 2, and 4. (9) An insulating film is provided on the surface of the second gate electrode, and the drain electrode and the cathode electrode are integrally formed passing over this insulating film.
The conductivity modulation type MOSFET described above. (10) A gate region is formed in a ring shape, a source layer is formed outside the ring, a drain layer is formed in a ring shape inside the ring, and a second gate electrode is formed inside the ring. The conductivity modulation type MOSFET according to claim 7, characterized in that: