JP2629437B2 - Lateral insulated gate bipolar transistor - Google Patents

Description

The present invention relates to a lateral insulated gate bipolar transistor used as a power switching element and as an intelligent switching element.

[Conventional technology]

As a power switching element, a vertical insulated gate bipolar transistor (vertical IGBT) has begun to be generally used. This can be said to be the addition of ap ⁺ layer on the drain electrode side of the drain region of the n-channel vertical MOSFET. However, in recent years, with the advent of RESURF technology, a sufficiently large breakdown voltage can be realized even in a horizontal IGBT, and in addition, all electrodes, that is, sources,
Because of the advantage that gate and drain electrodes can be arranged,
Research and development are being actively conducted for practical use not only as individual elements but also as output stages of intelligent elements in which control circuits are incorporated in the same chip.

The lateral IGBT, p-type substrate 2 as shown in FIG. 2 n of the (second layer) on the high resistivity ^- to form a layer 1 (first layer), the n ^-
A p ⁺ layer 3 (first region) and ap ⁺ layer 4 (second region) are selectively formed on the surface of the layer 1 with an interval therebetween. Then, an n ⁺ layer 5 (third region) is selectively formed on the surface of the p ⁺ layer 3. As a result of the resulting p ⁺ layer 3 n ^- layer 1 and the n ⁺ as a channel in the surface region sandwiched between the layer 5 occurs, a gate electrode connected to the gate terminal G via the gate insulating film 6 thereon 7 is provided. Further, the p ⁺ layer 3 is interposed between the gate electrode 7 and the insulating film 61.
A source electrode 8 connected to the source terminal S in contact with the n ⁺ layer 5, and a drain electrode 9 connected to the drain terminal D in contact with the p ⁺ layer 4 via the field insulating film 62. In addition, the p contacting the source electrode 8 and reaching the p substrate 2
^{The ++} layer 10 (fourth region) and the n ⁺ layer 11 interposed between the p ⁺ layer 4 and the n ⁻ layer 1 are formed. The p ⁺⁺ layer 10 is formed by the RESURF technology.
The n ⁺ layer 11 serves to make the potential of the substrate 2 the same as the source potential, and the depletion layer which expands when a reverse bias is applied to the pn junction between the n ⁻ layer 1 and the p ⁺ layer 3 is a p ⁺ layer 4. To prevent punch through.

In this element, when the source electrode 9 is grounded and a positive voltage is applied to the gate electrode 8 and the drain electrode 10, the n ⁺ layer 5, the p ⁺ layer 3, n ⁻
MOSFET comprising layer 1, gate insulating film 7 and gate electrode 8
Is turned on, and electrons flow into the n ⁻ layer 1. This allows the p ⁺ layer
The 4 / n ⁺ layer 11 junction turns on, holes flow from the p ⁺ layer 4 into the n ⁻ layer 1, and lower the resistance of the n ⁻ layer 2.

[Problems to be solved by the invention]

However, when the device as described above is turned on, not all of the holes injected from the p ⁺ layer 4 flow out to the source electrode 8 through the n ⁻ layer 1, and a part of the holes is transferred to the p substrate 2. It flows in. This is because the p substrate 2 has the same potential as the source electrode 8 by the RESURF technique. For this reason,
That is, the conductivity of the n ^- layer 1 is not sufficiently modulated, thereby increasing the on-state voltage. This disadvantage also exists in a p-channel lateral IGBT in which the conductivity type of each part is reversed.

An object of the present invention is to solve the above-mentioned disadvantages of a horizontal IGBT to which the RESURF technology is applied, and to provide a horizontal IGBT in which conductivity modulation sufficiently occurs.

[Means for solving the problem]

In order to achieve the above-described object, the present invention provides a method in which first and second regions of a second conductivity type selectively formed on a surface portion of a first layer of a first conductivity type having a low impurity concentration are each provided with a predetermined area. A third region of the first conductivity type is selectively formed on the surface portion of the first region, located at an interval, and the surface of the first region sandwiched between the third region and the first layer A gate electrode is provided via an insulating film, and a source electrode commonly in contact with the first region and the third region and a drain electrode in contact with the second region are respectively provided on one surface, and are opposite to the surface of the first layer. On the side, a second layer of the second conductivity type having a relatively low impurity concentration is formed via a third layer of the first conductivity type having a higher impurity concentration than the first layer, and the second layer of the second conductivity type contacts the source electrode and reaches the second layer. It is assumed that a fourth region having an impurity concentration is formed.

[Action]

When a voltage is applied to the gate electrode, a channel is formed on the surface of the first region sandwiched between the third region and the first layer, and the carriers injected from the third region when the device enters an ON state are The flow out into the second layer is prevented by the built-in electric field formed between the first and third layers. As a result, all the carriers injected into the first layer from the second region contribute to the conductivity modulation, thereby preventing an increase in the on-resistance of the device.

〔Example〕

FIG. 1 shows a horizontal IGBT according to an embodiment of the present invention, and portions common to FIG. 2 are denoted by the same reference numerals. The difference from FIG. 2 is that an n-type third layer 12 is interposed between the n ⁻ layer 1 and the p substrate 2. In the IGBT of the first embodiment, an n layer 12 having a thickness of 5 μm and an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ , and an impurity concentration of 1.5 × 10 × 10 ¹⁶ / cm ³ are formed on a p substrate 2 having an impurity concentration of 3.7 × 10 ¹⁴ cm ^3. 10 ¹⁵ / cm ³ of the n ^- layer 1 are sequentially laminated in the epitaxial growth, the surface impurity concentration by ion implantation and heat treatment of the surface ^{1.0 × 10 16 / cm 3,} x j 2μm of p ⁺ layer 4 and the surface impurity concentration of 1.0 × An n ⁺ layer 11 of 10 ¹⁷ / cm ³ , x _j 5 μm was formed. In the current / voltage curve of FIG. 3, the gate voltage V _G = 15 V
The line 31 is an IGBT element having the cross-sectional structure of FIG.
Shows the characteristics of the device of the first embodiment, and as can be seen from this figure, the device of the embodiment of the present invention has a lower on-state voltage, for example, 0.8 V when I = 10 A / cm ² . , I = 20A / cm ²
At this time, they are each reduced by 0.5V.

Next, in the IGBT of the second embodiment, the impurity concentration of the n-layer 12 was set to 1.0 × 10 ¹⁵ / cm ³ . The IV characteristic of the element is the third
As indicated by the line 33 in the figure, the line substantially overlaps the line 31, indicating that the on-voltage does not decrease. Therefore the relationship between the impurity concentration of the decreased amount and the n layer 12 of on-voltage impurity concentration of n ^- layer 1 is 1.5 × 10 ¹⁵ / cm
The case ³ was discussed in more detail. Figure 4 shows I _D = 2
This is a result measured at 0 A / cm ² , and the on-state voltage V _DON starts when the impurity concentration of the n-layer 12 exceeds the impurity concentration of the n ⁻ layer 1.
It can be seen that a decrease has occurred. Next, FIG. 5 shows the relationship between the decrease in the ON voltage at I _D = 20 A and the impurity concentration of the n-layer 12 when the impurity concentration of the n ⁻ layer 1 is increased to 6.2 × 10 ¹⁵ / cm ³ . Also in this case, as in the case of FIG. 4, the on-state voltage starts to decrease when the impurity concentration of the n layer 12 exceeds the impurity concentration of the n ⁻ layer 1. Note that the thickness of the n-layer 12 may be reduced as long as it is practically a layer.

〔The invention's effect〕

According to the present invention, the first layer having a higher impurity concentration than the first layer between the second layer of the second conductivity type and the first layer of the first resistance type having the same resistance as the source potential by the RESURF technique. By providing the third layer of the conductivity type, it was possible to prevent the injected carriers from the drain side contributing to the conductivity modulation from flowing out to the second layer side, and to obtain a lateral IGBT having a low on-voltage.

[Brief description of the drawings]

1 is a cross-sectional view of a horizontal IGBT according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional horizontal IGBT, and FIG. 3 is a current-voltage characteristic diagram of the horizontal IGBT of the embodiment of the present invention and a conventional structure. 4 and 5 are graphs showing the relationship between the impurity concentration of the n-layer and the decrease in the on-voltage according to the present invention. 1 ... n ^- layer (first layer), 2 ... p substrate (second layer), 3 ...
... p ⁺ layer (first area), 4 ... p ⁺ layer (second area), 5 ...
n ⁺ layer (third region), 6 gate insulating film, 7 gate electrode, 8 source electrode, 9 drain electrode, 10
p ⁺⁺ layer (fourth region), 12... n layer (third layer).

Claims (1)

(57) [Claims] The first and second regions of a second conductivity type selectively formed on a surface portion of a first layer of a first conductivity type having a low impurity concentration are located at a predetermined distance from each other. A third region of the first conductivity type is selectively formed on the surface of the region, and a gate electrode is provided via an insulating film on a surface of the first region sandwiched between the third region and the first layer. A source electrode in common contact with the first region and the third region, and a drain electrode in contact with the second region, respectively, on one surface, the impurity concentration is higher than the first layer on the opposite side to the surface of the first layer A second layer of the second conductivity type having a relatively low impurity concentration was formed through the third layer of the first conductivity type, and a fourth region having a high impurity concentration reaching the second layer in contact with the source electrode was formed. A lateral insulated gate bipolar transistor characterized by the above-mentioned.