JP2536122B2 - p-channel insulated gate bipolar transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a p-channel insulated gate bipolar transistor in which a base current of an npn bipolar transistor is supplied by a p-channel MOSFET.

[Conventional technology]

An n-channel insulated gate bipolar transistor (IGBT) is generally used as a power switching element. It can be said that a p ⁺ layer is added to the drain electrode side of the drain region of the n-channel vertical MOSFET. However, in recent years, the p-channel IGBT has been vigorously developed because the control circuit can be simplified and can be easily integrated with the control circuit. p-channel type
The IGBT is an n-channel IGBT with all conductivity types reversed.

That is, as shown in FIG. 2, a low resistance p ⁺ layer 2 (second layer) as a buffer layer is formed on an n ⁺ substrate 1 (first layer), and a high resistance p ⁻ layer 3 is formed on the surface thereof. (Third layer) is formed,
An n ⁺ layer 4 (first region) is selectively formed on the surface of the p ⁻ layer 3.
Further, the p ⁺ layer 5 (second region) is selectively formed on the surface of the n ⁺ layer 4.
Further, with the surface region of the n ⁺ layer 4 sandwiched by the p ⁻ layer 3 and the P ⁺ layer 5 as a channel region, a gate electrode 7 is formed thereon with a gate insulating film 6 interposed therebetween. Then, the source electrode 8 is brought into contact with the n ⁺ layer 4 and the p ⁺ layer 5, and the drain electrode 9 is brought into contact with the surface of the n ⁺ substrate 1.

When the source electrode 8 is grounded and a negative voltage is applied to the gate electrode 7 and the drain electrode 9, the electrons turn on the MOSFET and holes flow into the p ⁻ layer 3. Occurs layers 3 electron injection into, p ^{- -} This p of n ⁺ substrate 1 in correspondence by the layer 3 conductivity modulation occurs, the resistance of this region is low.

[Problems to be Solved by the Invention]

When a p-channel IGBT is turned off with an L load, a voltage of several hundred V of the L load back electromotive force and, for example, a power supply voltage of 200 V are applied to the junction of the p ⁻ layer and the n ⁺ layer 4 in the form of reverse bias. Join.
Therefore, a large electric field is generated at the junction. Further, since the npn transistors of the n ⁺ substrate 1, p ⁺ layer, p ⁻ layer 3, and n ⁺ layer 4 try to keep a constant current flowing, the main current becomes an electron current. High electric field (about 10 ⁵ V / cm) electron impact ionization ratio when applied, for about 100 to 1,000 times than that of the hole larger, p-channel IGBT compared to n-channel IGBT, susceptible to avalanche breakdown during turn-off .

The present invention solves the above-mentioned drawbacks which are urgent problems,
It is an object of the present invention to provide a p-channel IGBT that is unlikely to cause avalanche breakdown at turn-off.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention provides a high impurity concentration n-type first layer, a high impurity concentration p-type second layer, and a low impurity concentration p-type third layer in order, An n-type first region is selectively formed on the surface portion of the third layer, and a p-type second region is selectively formed on the surface portion of the first region. The third layer and the second region are formed. In a p-channel insulated gate bipolar transistor in which a gate electrode is provided on the sandwiched first region via an insulating film, a portion in contact with the second layer of the third layer has a specific resistance of the third layer and a second layer. A layer having a resistivity in the middle of the resistivity is used.

[Action]

By providing a layer having an intermediate specific resistance in the portion of the third layer which is in contact with the second layer, even when a large electric field is generated at the junction between the second layer and the first region, The injection of electrons from the first layer to the second layer of an npn bipolar transistor consisting of three layers and the first region is reduced, and the current amplification factor h _{FE of the} transistor whose main current becomes an electron current is reduced, thereby reducing the collector. Avalanche breakdown is less likely to occur because positive feedback to the current is less likely to occur.

〔Example〕

FIG. 1 shows a p-channel IGBT according to an embodiment of the present invention. The parts common to those in FIG. 2 are designated by the same reference numerals, but different from FIG. 2 are the p-layer 3 and the p-layer 2. The point is that the p-layer 10 having an intermediate specific resistance is inserted between. Such an IGBT is manufactured in the following steps.

A specific resistance of 0.07 Ωcm or less, a thickness of 500 μm, and a p ⁺ buffer layer of a specific resistance of 0.4 Ωcm and a thickness of 10 μm on the surface of the n ⁺ substrate 1, a specific resistance of 2
Ωcm, p layer 10 with a thickness of 20 μm, specific resistance 90 Ωcm, p with a thickness of 35 μm
^-Laminate Layer 3. The sum of the p layer 10 and the p ⁻ layer 3 of 55 μm is equal to the thickness of the p ⁻ layer 3 in FIG. Then, the surface is covered with an oxide film having a thickness of 1000Å and a polycrystalline silicon layer having an impurity concentration of 10 ¹⁷ / cm ³ and a thickness of 1 μm, and the gate oxide film 6 and the gate electrode 7 are patterned. Using this gate electrode as a mask, n ⁺
Ion implantation and thermal diffusion to form layer 4 are performed. The impurity concentration of the generated n ⁺ layer 4 is 10 × 10 ¹⁸ / cm ³ and the depth is 10
μm. Further, shallow ion implantation and thermal diffusion for forming the p ⁺ layer 5 are also performed using the gate oxide film 7 as a mask. The resulting p ⁺ layer 5 has an impurity concentration of 3.0 × 10 ²⁰ / cm ³ and a depth of 0.2 μm. After that, an insulating film 11 such as PSG is covered, and the source electrode 8 that contacts the p ⁺ layer 5 and the n ⁺ layer 4 through the opened contact hole and the drain electrode 9 that contacts the back surface of the n ⁺ substrate 1 are formed. Form.

The secondary breakdown potential V _DSX of the IGBT having such a structure and the IGBT shown in FIG. 2 without the p-layer 10 was calculated by Poisson's equation or the like. The power supply voltage was 200V. FIG. 3 shows the relationship between the current _ID and V _{DSX at} the time of turning off according to the calculation result, the line 31 is the element of the embodiment of the present invention shown in FIG. 1, and the line 32 is shown in FIG. It is a value for a conventional device. From this figure, the IGBT according to the present invention has a larger V _DSX . The V _DSX obtained with the actual device almost agreed with this calculation result. That is, the IGBT according to the present invention is less likely to be avalanche destroyed than the conventional type.

〔The invention's effect〕

According to the present invention, by only disposing the intermediate resistance layer between the low impurity concentration of the p-channel IGBT and the buffer layer, the first layer (drain side) to the second layer of the npn bipolar transistor are turned off at the time of turn-off. The number of electrons injected into the collector is reduced, positive feedback to the collector current is less likely to occur, and avalanche breakdown at the time of L load turn-off is less likely to occur, so the obtained effect is extremely large.

[Brief description of drawings]

FIG. 1 is a sectional view of a p-channel IGBT according to an embodiment of the present invention,
FIG. 2 is a cross-sectional view of a conventional p-channel IGBT, and FIG. 3 is a line obtained by calculation of the relationship between the off-state drain current and the secondary breakdown voltage of the p-channel IGBT according to the embodiment of the present invention and the conventional example. It is a figure. 1: n ⁺ substrate (first layer), 2: p ⁺ buffer layer (second layer), 3: p ^-
Third layer, 4: n ⁺ first region, 5: p ⁺ second region, 6: gate insulating film, 7: gate electrode, 8: source electrode, 9: drain electrode, 1
0: p intermediate resistivity layer.

Claims (1)

(57) [Claims] 1. A n-type first layer having a high impurity concentration, a p-type second layer having a high impurity concentration, and a p-type third layer having a low impurity concentration are adjacent in this order, and a surface portion of the third layer is provided. An n-type first region is selectively formed, and a p-type second region is selectively formed on the surface of the first region, and the p-type second region is sandwiched between the third layer and the second region. In the one in which the gate electrode is provided via the insulating film, the portion of the third layer in contact with the second layer has a resistivity intermediate between the resistivity of the third layer and the resistivity of the second layer, and A p-channel insulated gate bipolar transistor comprising a layer thicker than the layer.