JPH0620141B2 - Conduction modulation type MOSFET - Google Patents
Conduction modulation type MOSFETInfo
- Publication number
- JPH0620141B2 JPH0620141B2 JP6442685A JP6442685A JPH0620141B2 JP H0620141 B2 JPH0620141 B2 JP H0620141B2 JP 6442685 A JP6442685 A JP 6442685A JP 6442685 A JP6442685 A JP 6442685A JP H0620141 B2 JPH0620141 B2 JP H0620141B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- electrode
- base layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、導電変調型ＭＯＳＦＥＴに関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a conductive modulation type MOSFET.
近年、電力用スイッチング素子として、ＤＳＡ（Ｄiffu
sion Ｓelf Ａlign）法によりソース及びチャネル領
域を形成するパワーＭＯＳＦＥＴが市場に現われてい
る。しかしこの素子は１０００Ｖ以上の高耐圧ではオン
抵抗が高くなってしまい、大電流を流すことが難しい。
これに代わる有力な素子として、ドレイン領域にソース
とは逆の導電型層を設けることにより高抵抗層に導電変
調を起こさせてオン抵抗を下げるようにした、いわゆる
導電変調型ＭＯＳＦＥＴが知られている。In recent years, DSA (Diffu
Power MOSFETs that form a source and a channel region by the sion self alignment method have appeared on the market. However, this device has a high on-resistance at a high breakdown voltage of 1000 V or more, and it is difficult to flow a large current.
As a powerful alternative to this, a so-called conduction modulation type MOSFET is known, in which a conduction type layer opposite to the source is provided in the drain region to cause conduction modulation in the high resistance layer to lower the on-resistance. There is.
この様な導電変調型ＭＯＳＦＥＴの基本構造を第７図に
示す。１１はドレイン層となるｐ＋型Ｓｉ基板であり、
この上に低不純物濃度の高抵抗ｎ−型層１２が形成さ
れ、このｎ−型層の表面にＤＳＡ法によりｐ型ベース層
１３とｎ＋型ソース層１４が形成されている。即ちｐ型
ベース層１３を拡散形成した拡散窓をそのままｎ＋型ソ
ース層１４の拡散窓の一部として用いて二重拡散するこ
とにより、ｐ型ベース層１３に自己整合的にチャネル領
域１９を残した状態でｎ＋型ソース層１４が形成され
る。そしてチャネル領域１９上にはゲート絶縁膜１５を
介してゲート電極１６が形成され、ソース層１４上には
ベース層１３に同時にオーミック接触するソース電極１
７が形成される。基板１１の裏面にはドレイン電極１８
が形成されている。The basic structure of such a conductivity modulation type MOSFET is shown in FIG. Reference numeral 11 is a p + type Si substrate serving as a drain layer,
A high-resistance n − -type layer 12 having a low impurity concentration is formed on this, and a p-type base layer 13 and an n + -type source layer 14 are formed on the surface of this n − -type layer by the DSA method. That is, by using the diffusion window formed by diffusing the p-type base layer 13 as it is as a part of the diffusion window of the n + -type source layer 14 and performing double diffusion, the channel region 19 is self-aligned with the p-type base layer 13. The n + type source layer 14 is formed in the state where it is left. Then, the gate electrode 16 is formed on the channel region 19 via the gate insulating film 15, and the source electrode 1 on the source layer 14 is in ohmic contact with the base layer 13 at the same time.
7 is formed. The drain electrode 18 is formed on the back surface of the substrate 11.
Are formed.
この導電変調型ＭＯＳＦＥＴでは、ソース層１４からチ
ャネル領域１９を通ってｎ−型層１２に注入される電子
電流に対して、ｐ＋型基板１１から正孔注入が起り、こ
の結果ｎ−型層１２には多量のキャリア蓄積による導電
変調が起こる。ｎ−型層１２に注入された正孔電流はｐ
型ベース層１３のソース層１４直下を通り、ソース電極
１７へ抜ける。In this conductivity modulation type MOSFET, holes are injected from the p + -type substrate 11 with respect to the electron current injected from the source layer 14 to the n − -type layer 12 through the channel region 19, and as a result, the n − -type layer is injected. Conduction modulation occurs in 12 due to the accumulation of a large amount of carriers. The hole current injected into the n − type layer 12 is p
It passes under the source layer 14 of the mold base layer 13 and exits to the source electrode 17.
この構造はサイリスタと似ているが、サイリスタ動作は
しない。ソース電極１７がベース層１３とソース層１４
を短絡してサイリスタ動作を阻止しており、ゲート・ソ
ース間電圧を零とすれば素子はターンオフする。またこ
の構造は従来のパワーＭＯＳＦＥＴとも似ているが、ド
レイン領域にパワーＭＯＳＦＥＴとは逆の導電型層を設
けてバイポーラ動作を行わせている点で異なる。This structure is similar to a thyristor, but it does not operate as a thyristor. The source electrode 17 is the base layer 13 and the source layer 14.
The thyristor operation is blocked by short-circuiting, and the element is turned off if the gate-source voltage is set to zero. Further, this structure is similar to the conventional power MOSFET, but is different in that the drain region is provided with a conductivity type layer opposite to that of the power MOSFET to perform a bipolar operation.
この導電変調型ＭＯＳＦＥＴでは、高耐圧化した場合に
も、従来のパワーＭＯＳＦＥＴに比べて導電変調の結果
として十分低いオン抵抗が得られる。In this conductivity modulation type MOSFET, a sufficiently low on-resistance can be obtained as a result of the conductivity modulation compared with the conventional power MOSFET even when the breakdown voltage is increased.
しかしながらこの導電変調型ＭＯＳＦＥＴにも未だ問題
がある。即ち素子を流れる電流が大きくなると、ソース
層１４下の横方向抵抗による電圧降下が大きくなる。そ
してｐ型ベース層１３とｎ＋型ソース層１４の間が順方
向バイアスされるようになるとサイリスタ動作に入り、
ゲート・ソース間電圧を零にしても素子がオフしない、
いわゆるラッチアップ現象を生じる。However, this conductivity modulation type MOSFET still has a problem. That is, as the current flowing through the element increases, the voltage drop due to the lateral resistance under the source layer 14 increases. When a forward bias is applied between the p-type base layer 13 and the n + -type source layer 14, the thyristor operation starts,
The element does not turn off even if the gate-source voltage is zero,
A so-called latch-up phenomenon occurs.
この問題を解決するために従来は、第８図に示すよう
に、深いｐ＋型層２０を拡散形成して、ｐ型ベース層１
３の抵抗を下げることが行われている。しかしこの方法
だけでは、十分高い電流密度までラッチアップ現象を防
ぐことはできない。In order to solve this problem, conventionally, as shown in FIG. 8, a deep p + -type layer 20 is formed by diffusion to form the p-type base layer 1.
The resistance of 3 is being reduced. However, this method alone cannot prevent the latch-up phenomenon up to a sufficiently high current density.
本発明は上記した点に鑑みなされたもので、効果的に大
電流領域までラッチアップ現象を生じないようにした導
電変調型ＭＯＳＦＥＴを提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a conductive modulation type MOSFET in which a latch-up phenomenon does not effectively occur even in a large current region.
本発明は、第１導電型ドレイン層の上に第２導電型の高
抵抗層を有し、この高抵抗層にＤＳＡ法により第１導電
型ベース層とその表面に第２導電型ソース層が形成され
る導電変調型ＭＯＳＦＥＴにおいて、ドレイン側からベ
ース層に注入されるキャリアの内ソース層下を通る成分
を少なくして、ソース層下の横方向抵抗による電圧降下
を小さくし、もって大電流領域までラッチアップを生じ
ないようにする。このようにソース層下を通る電流成分
を少なくするために本発明では、複数のベース層の内に
ソース層を形成しないベース層を設け、このようなベー
ス層上に補助電極を設けて、この補助電極から高抵抗層
内の過剰なキャリアを排出し、ソース層の形成されたベ
ース層へ流入するキャリアの量を少なくする。ところで
この様な構成とすると、ラッチアップする時の電流密度
を増大させることができるが、スイッチング時でない定
常のオン状態の時もソース層のないベース層から電流が
流出し、高抵抗層に蓄積する過剰キャリア量を少なくし
てしまい、順方向電圧降下が少し高くなる。これを避け
るためには、キャリアがソース層のないベース素子から
補助電極を介してソース電極へ抜ける時にｐｎ接合やシ
ョットキー障壁を通過するように構成することが有効で
ある。このようにすれば、定常状態ではこのバリアのた
めキャリアの流れが少なくなるので、オン電圧低下は防
止される。過剰キャリアを収集するための上述の補助電
極は、ソース電極ではなくゲート電極に接続してもよ
い。The present invention has a second-conductivity-type high-resistance layer on the first-conductivity-type drain layer, on which a first-conductivity-type base layer and a second-conductivity-type source layer are formed on the surface by the DSA method. In the formed conductivity modulation type MOSFET, the components of the carriers injected from the drain side to the base layer that pass under the source layer are reduced, and the voltage drop due to the lateral resistance under the source layer is reduced, thereby providing a large current region. To prevent latch up. In order to reduce the current component passing under the source layer, the present invention provides a base layer in which the source layer is not formed among a plurality of base layers, and an auxiliary electrode is provided on such a base layer. Excessive carriers in the high resistance layer are discharged from the auxiliary electrode to reduce the amount of carriers flowing into the base layer where the source layer is formed. By the way, with such a configuration, the current density at the time of latch-up can be increased, but current flows out from the base layer without the source layer and accumulates in the high resistance layer even in the steady ON state other than switching. The amount of excess carriers to be used is reduced, and the forward voltage drop is slightly increased. In order to avoid this, it is effective that the carrier passes through the pn junction or the Schottky barrier when it escapes from the base element having no source layer to the source electrode via the auxiliary electrode. In this case, in the steady state, the flow of carriers is reduced due to this barrier, so that the on-voltage drop is prevented. The above-mentioned auxiliary electrode for collecting excess carriers may be connected to the gate electrode instead of the source electrode.
本発明によれば、簡単かつ効果的に導電変調型ＭＯＳＦ
ＥＴのラッチアップ現象を抑制することができ、大電流
または動作する導電変調型ＭＯＳＦＥＴが得られる。According to the present invention, the conductivity modulation type MOSF can be simply and effectively used.
It is possible to suppress the ET latch-up phenomenon and obtain a conductive modulation type MOSFET that operates with a large current or operates.
以下本発明の実施例を説明する。 Examples of the present invention will be described below.
第１図は一実施例の導電変調型ＭＯＳＦＥＴの断面図で
ある。第７図及び第８図と対応する部分にはそれらと同
一符号を付してある。これを製造工程に従って説明す
る。ドレイン層となるｐ＋型Ｓｉ基板１１を用意し、こ
れにエピタキシャル成長により低不純物濃度で比抵抗５
０Ω・cm以上の高抵抗ｎ−型層１２を１００μｍ程度形
成する。次にこのｎ−型層１２の表面を酸化してゲート
酸化膜１５を形成し、その上に５０００Åの多結晶Ｓｉ
膜によるゲート電極１６を形成する。この後ゲート電極
１６をマスクとしてボロンを４μｍ程度拡散してｐ型ベ
ース層１３（１３１，１３２，…）を形成する。次いで
ゲート電極１６による拡散窓の中にソース形成用の開口
を持つ酸化膜（図示せず）を形成し、この酸化膜とゲー
ト電極１６をマスクとしてソース層形成のためのドーズ
量５×１０１５／cm2のＡｓイオン注入を行ない、熱処
理してｎ＋型ソース層１４を形成する。図では二個のベ
ース層１３１，１３２の内一方１３１にはソース層１４
を形成し、他方１３２にはソース層を形成しない。即ち
複数個のベース層のうち、所定個数のベース層にはソー
ス層を形成し、他のベース層にはソース層を形成しない
ようにする。この後ベース層１３内に高濃度のｐ＋型層
２０を形成し、ソース層１４が形成されたベース層１３
１にはソース層１４とベース層１３１の両方にオーミッ
ク接触するソース電極１７１を形成し、ソース層のない
ベース層１３２にはこれにオーミック接触する，過剰キ
ャリア排出のための補助電極１７２を形成する。補助電
極１７２はソース電極１７１に接続される。基板１１の
裏面にはＶ−Ｎｉ−Ａｕ膜の蒸着によりドレイン電極１
８を形成する。これにより、チャネル領域１９（１
９１，１９２，…）は、ＭＯＳＦＥＴ動作をする実効的
チャネル領域１９１と、ソース層がないためにＭＯＳＦ
ＥＴ動作をしない部分１９２とが規則性をもって配列さ
れた状態となる。FIG. 1 is a sectional view of a conductivity modulation type MOSFET of one embodiment. The parts corresponding to those in FIGS. 7 and 8 are designated by the same reference numerals. This will be described according to the manufacturing process. A p + type Si substrate 11 to be a drain layer is prepared, and a specific resistance of 5 is obtained at a low impurity concentration by epitaxial growth.
A high resistance n − type layer 12 having a resistance of 0 Ω · cm or more is formed to about 100 μm. Next, the surface of the n − -type layer 12 is oxidized to form a gate oxide film 15, and 5000 Å of polycrystalline Si is formed on the gate oxide film 15.
The gate electrode 16 made of a film is formed. Thereafter, boron is diffused by about 4 μm using the gate electrode 16 as a mask to form the p-type base layer 13 (13 1 , 13 2 , ...). Next, an oxide film (not shown) having an opening for forming a source is formed in the diffusion window formed by the gate electrode 16, and a dose amount of 5 × 10 15 for forming the source layer is formed using the oxide film and the gate electrode 16 as a mask. / Cm 2 As ions are implanted and heat-treated to form the n + type source layer 14. In the figure, one of the two base layers 13 1 and 13 2 has a source layer 14 on one side 13 1.
Forming a not form source layers and the other 13 2. That is, the source layer is formed on a predetermined number of base layers among the plurality of base layers, and the source layer is not formed on the other base layers. After that, a high-concentration p + -type layer 20 is formed in the base layer 13 and the source layer 14 is formed.
Forming a source electrode 17 1 to ohmic contact with both the source layer 14 and base layer 13 1 to 1, to which ohmic contact with the base layer 13 2 with no source layer, an auxiliary electrode for the excess carrier discharging 17 Form 2 . The auxiliary electrode 17 2 is connected to the source electrode 17 1 . The drain electrode 1 is formed on the back surface of the substrate 11 by vapor deposition of a V-Ni-Au film.
8 is formed. Thereby, the channel region 19 (1
9 1 , 19 2 , ...) are MOSFs because there is no effective channel region 19 1 for MOSFET operation and no source layer.
And portion 19 2 which is not the ET operation is a state of being arranged with regularity.
この実施例のＭＯＳＦＥＴでは、素子がオンの時にゲー
ト電極１６下に開口するｎ−型層１２からｐ型ベース層
１３に注入される正孔電流のうち、チャネル部分１９２
を通るものはソース層１４の下を通らず補助電極１７２
に流れる。従って従来の構造に比べてソース層１４下で
横方向に流れる正孔の量が減り、大電流までラッチアッ
プ現象を生じない。In MOSFET of this embodiment, n elements are opened under the gate electrode 16 in the on - of the hole current injected from the mold layer 12 to the p-type base layer 13, the channel part 19 2
Which through not pass under the source layer 14 auxiliary electrode 17 2
Flow to. Therefore, the amount of holes flowing laterally under the source layer 14 is reduced as compared with the conventional structure, and the latch-up phenomenon does not occur up to a large current.
第２図は別の実施例のＭＯＳＦＥＴの断面図を第１図に
対応させて示す。この実施例では、補助電極１７２とソ
ース電極１７１の間に補助電極１７２側をアノードとす
るダイオード２１を接続している。それ以外は第１図と
同じである。FIG. 2 shows a sectional view of a MOSFET of another embodiment corresponding to FIG. In this embodiment, a diode 21 having an anode on the side of the auxiliary electrode 17 2 is connected between the auxiliary electrode 17 2 and the source electrode 17 1 . Otherwise, it is the same as in FIG.
このように構成すれば、補助電極１７２の電位がソース
電極１７１のそれより高くなり、この補助電極１７２を
介して流出する電流が抑制される。即ち補助電極１７２
を介しての正孔の流出を素子のスイッチング時に限るこ
とができ、素子がオンの定常状態での順方向電圧降下を
増大させることなく、ラッチアップ現象を抑制すること
ができる。According to this structure, the potential of the auxiliary electrode 17 2 becomes higher than that of the source electrode 17 1 , and the current flowing out via this auxiliary electrode 17 2 is suppressed. That auxiliary electrode 17 2
It is possible to limit the outflow of holes through the element during switching of the element, and suppress the latch-up phenomenon without increasing the forward voltage drop in the steady state in which the element is on.
第３図は更に別の実施例のＭＯＳＦＥＴの断面図であ
る。この実施例では、ソース層のないベース層１３２に
ｐ＋型層を設けず、このベース層１３２と補助電極１７
２の間にショットキー障壁２２を形成している。このシ
ョットキー障壁２２は第２図の実施例のダイオード２１
と同じ働きをし、従って第２図の実施例と同様にオン電
圧の増大をもたらすことなくラッチアップ現象を抑制で
きる、という効果が得られる。FIG. 3 is a sectional view of a MOSFET of yet another embodiment. In this embodiment, the p + type layer is not provided on the base layer 13 2 having no source layer, and the base layer 13 2 and the auxiliary electrode 17 are not provided.
A Schottky barrier 22 is formed between the two . This Schottky barrier 22 is the diode 21 of the embodiment of FIG.
Therefore, the same effect as in the embodiment of FIG. 2 can be obtained, and the latch-up phenomenon can be suppressed without increasing the on-voltage.
第４図は第２図の実施例を変形した実施例で、補助電極
１７２をダイオード２１を介してゲート電極１６に接続
している。ゲート電極１６の電位は素子のオン状態では
正であるため、ここからの正孔の流出はなく、またダイ
オード２１が逆バイアスされるのでゲート電流も素子内
に流れ込まない。一方、素子のスイッチングオフ時に
は、ゲート電極１６の電位は零または負になり、補助電
極１７２からダイオード２１を介して過剰な正孔電流が
排出される。従ってこの実施例によっても先の実施例と
同様の効果が得られる。Figure 4 is connected a second in embodiment obtained by modifying the embodiment of FIG, an auxiliary electrode 17 2 to the gate electrode 16 through the diode 21. Since the potential of the gate electrode 16 is positive in the ON state of the element, holes do not flow out from here, and the gate current does not flow into the element because the diode 21 is reverse biased. On the other hand, during the switching off of the element, the potential of the gate electrode 16 becomes zero or negative, excessive hole current is discharged through the diode 21 from the auxiliary electrode 17 2. Therefore, according to this embodiment, the same effect as the previous embodiment can be obtained.
第５図は第３図の実施例を変形した実施例である。この
実施例では、ショットキー障壁２２を形成する補助電極
１７２をゲート電極１６に接続している。この実施例に
よっても先の実施例の説明から明らかなように、オン電
圧の増大を伴うことなくラッチアップ現象を抑制するこ
とができる。FIG. 5 shows an embodiment obtained by modifying the embodiment shown in FIG. In this example, it connects the auxiliary electrode 17 2 which forms a Schottky barrier 22 to the gate electrode 16. Also in this embodiment, as is clear from the description of the previous embodiment, the latch-up phenomenon can be suppressed without increasing the ON voltage.
第６図は第１図の実施例を変形した実施例である。この
実施例では、補助電極１７２とソース電極１７１の間に
スイッチ素子としてＭＯＳＦＥＴ２３を設けている。こ
のような構成として、ＭＯＳＦＥＴ２３を、素子がオン
の定常状態ではオフとし、素子がスイッチングオフ時に
のみオンとなるように制御する。これにより先の実施例
と同様、オン電圧の増大を伴うことなく、大電流までラ
ッチアップ現象を生じないようにすることができる。FIG. 6 shows an embodiment obtained by modifying the embodiment shown in FIG. In this embodiment, it is provided MOSFET23 as a switching element between the auxiliary electrode 17 2 and the source electrode 17 1. With such a configuration, the MOSFET 23 is controlled so as to be turned off in a steady state in which the element is on and turned on only when the element is switched off. As a result, as in the previous embodiment, it is possible to prevent the latch-up phenomenon up to a large current without increasing the ON voltage.
本発明はその他、その趣旨を逸脱しない範囲で種々変形
して実施することができる。The present invention can be modified in various ways without departing from the scope of the invention.
第１図は本発明の一実施例の導電変調型ＭＯＳＦＥＴを
示す断面図、第２図は他の実施例の導電変調型ＭＯＳＦ
ＥＴを示す断面図、第３図〜第６図は更に他の実施例の
導電変調型ＭＯＳＦＥＴを示す断面図、第７図及び第８
図は従来の導電変調型ＭＯＳＦＥＴを示す断面図であ
る。 １１……ｐ＋型Ｓｉ基板（ドレイン層）、１２……高抵
抗ｎ−型層、１３（１３１，１３２…）……ｐ型ベース
層、１４……ｎ＋型ソース層、１５……ゲート絶縁膜、
１６……ゲート電極、１７１……ソース電極、１７２…
…補助電極、１８……ドレイン電極、１９（１９１，１
９２，…）……チャネル領域、２０……ｐ＋型層、２１
……ダイオード、２２……ショットキー障壁、２３……
ＭＯＳＦＥＴ（スイッチ素子）。FIG. 1 is a sectional view showing a conductivity modulation type MOSFET according to an embodiment of the present invention, and FIG. 2 is a conductivity modulation type MOSF according to another embodiment.
Sectional views showing ET, FIGS. 3 to 6 are sectional views showing a conductive modulation type MOSFET of still another embodiment, FIG. 7 and FIG.
The figure is a cross-sectional view showing a conventional conductive modulation type MOSFET. 11 ...... p + -type Si substrate (drain layer) 12 ...... high resistance n - type layer, 13 (13 1, 13 2 ...) ...... p -type base layer, 14 ...... n + -type source layer, 15 ... ... gate insulating film,
16 ... Gate electrode, 17 1 ... Source electrode, 17 2 ...
... auxiliary electrode, 18 ... drain electrode, 19 (19 1 , 1
9 2 , ...) ... Channel region, 20 ... p + type layer, 21
…… Diode, 22 …… Schottky barrier, 23 ……
MOSFET (switch element).
フロントページの続き (72)発明者 大橋 弘通 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝総合研究所内 (56)参考文献 特開 昭57−120369（ＪＰ，Ａ)Front page continuation (72) Inventor Hiromichi Ohashi 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute Co., Ltd. (56) Reference JP-A-57-120369 (JP, A)
Claims (8)
層上に連続してある第２導電型の高抵抗層と、この高抵
抗層表面部に拡散形成された第１導電型のベース層と、
このベース層の表面にベース層と自己整合的に拡散形成
された第２導電型のソース層と、このソース層と前記高
抵抗層に挟まれたベース層表面に絶縁膜を介して形成さ
れたゲート電極と、前記ソース層が形成されたベース層
内でソース層とベース層の両方にオーミック接触するよ
うに形成されたソース電極と、ソース層が形成されてい
ない領域でベース層表面に形成された，ドレイン層から
注入されたキャリアによる過剰電流を収集する補助電極
と、前記ドレイン層にオーミック接触するドレイン電極
とを備えたことを特徴とする導電変調型ＭＯＳＦＥＴ。1. A first conductivity type drain layer, a second conductivity type high resistance layer continuous on the drain layer, and a first conductivity type base diffused on the surface of the high resistance layer. Layers and
A second-conductivity-type source layer is formed on the surface of the base layer in a self-aligned diffused manner, and an insulating film is formed on the surface of the base layer sandwiched between the source layer and the high resistance layer. A gate electrode, a source electrode formed in the base layer in which the source layer is formed so as to make ohmic contact with both the source layer and the base layer, and formed on the surface of the base layer in a region where the source layer is not formed. A conduction modulation type MOSFET, further comprising: an auxiliary electrode for collecting an excess current due to carriers injected from the drain layer, and a drain electrode in ohmic contact with the drain layer.
触し、かつソース電極に接続されている特許請求の範囲
第１項記載の導電変調型ＭＯＳＦＥＴ。2. The conduction modulation type MOSFET according to claim 1, wherein the auxiliary electrode is in ohmic contact with the base layer and is connected to the source electrode.
触し、かつ素子のオン状態での電流を抑制するダイオー
ドを介してソース電極と接続されている特許請求の範囲
第１項記載の導電変調型ＭＯＳＦＥＴ。3. The conductive modulation according to claim 1, wherein the auxiliary electrode is in ohmic contact with the base layer and is connected to the source electrode through a diode that suppresses a current in an ON state of the device. Type MOSFET.
トキー障壁を形成するものであり、かつソース電極に接
続されている特許請求の範囲第１項記載の導電変調型Ｍ
ＯＳＦＥＴ。4. The conductivity modulation type M according to claim 1, wherein the auxiliary electrode forms a Schottky barrier with the base layer and is connected to the source electrode.
OSFET.
触し、かつ素子のオン状態での電流を抑制するダイオー
ドを介してゲート電極と接続されている特許請求の範囲
第１項記載の導電変調型ＭＯＳＦＥＴ。5. The conductive modulation according to claim 1, wherein the auxiliary electrode is in ohmic contact with the base layer and is connected to the gate electrode via a diode that suppresses a current in an ON state of the device. Type MOSFET.
トキー障壁を形成するものであり、かつゲート電極と接
続されている特許請求の範囲第１項記載の導電変調型Ｍ
ＯＳＦＥＴ。6. The conductivity modulation type M according to claim 1, wherein the auxiliary electrode forms a Schottky barrier with the base layer and is connected to the gate electrode.
OSFET.
オフにする時にオンになるように制御されるスイッチを
有する特許請求の範囲第１項記載の導電変調型ＭＯＳＦ
ＥＴ。7. The conduction modulation type MOSF according to claim 1, further comprising a switch between the auxiliary electrode and the source electrode, the switch being turned on when the element is turned off.
ET.
域とソース層が形成されていない領域を含む複数領域か
らなる特許請求の範囲第１項記載の導電変調型ＭＯＳＦ
ＥＴ。8. The conduction modulation type MOSF according to claim 1, wherein the base layer comprises a plurality of regions including a region where a source layer is formed and a region where a source layer is not formed.
ET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6442685A JPH0620141B2 (en) | 1985-03-28 | 1985-03-28 | Conduction modulation type MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6442685A JPH0620141B2 (en) | 1985-03-28 | 1985-03-28 | Conduction modulation type MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61222260A JPS61222260A (en) | 1986-10-02 |
| JPH0620141B2 true JPH0620141B2 (en) | 1994-03-16 |
Family
ID=13257941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6442685A Expired - Lifetime JPH0620141B2 (en) | 1985-03-28 | 1985-03-28 | Conduction modulation type MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620141B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4779123A (en) * | 1985-12-13 | 1988-10-18 | Siliconix Incorporated | Insulated gate transistor array |
| JP2722453B2 (en) * | 1987-06-08 | 1998-03-04 | 三菱電機株式会社 | Semiconductor device |
| JPH01256172A (en) * | 1988-04-06 | 1989-10-12 | Fuji Electric Co Ltd | Manufacture of conductivity modulating mosfet |
| JP2508818B2 (en) * | 1988-10-03 | 1996-06-19 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| US5331192A (en) * | 1989-06-15 | 1994-07-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
| US5381025A (en) * | 1989-08-17 | 1995-01-10 | Ixys Corporation | Insulated gate thyristor with gate turn on and turn off |
| JPH05283702A (en) * | 1992-04-03 | 1993-10-29 | Hitachi Ltd | Composite control type semiconductor device and power converter using thereof |
| JP4696354B2 (en) * | 2000-12-08 | 2011-06-08 | 株式会社デンソー | Driving method of semiconductor device |
| US11282948B2 (en) | 2018-08-02 | 2022-03-22 | Mitsubishi Electric Corporation | Wide band gap semiconductor device and power conversion apparatus |
-
1985
- 1985-03-28 JP JP6442685A patent/JPH0620141B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61222260A (en) | 1986-10-02 |
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