JPH053205A - Insulated-gate bipolar transistor - Google Patents

Abstract

PURPOSE:To decrease power loss in the on-state of a high-speed device by providing one collector-shorting member for a plurality of cells to eliminate the negative resistance region in the on-state I-V curve. CONSTITUTION:A collector-shorting region 10 of a first conductivity type is provided for a plurality of cells. The region 10, formed into a single columnar member rather than divided to be distributed on a collector layer, penetrates through the collector layer 9 and in contact with a collector electrode 11. As a result, the electron current injected from an n<+> emitter region 3 to a channel region 4 by the voltage applied between the gate and emitter flows into a common buffer 8 through the channels of the cells. The current is concentrated in the n<+> collector-shorting region 10 by the built-in field between the n-type collector-shorting region 10 and p<+> collector layer. Therefore, the distance the electron current passes by the p<+> region 9 brings about a voltage drop, thereby assisting the injection of holes from the p<+> region to promote conductivity modulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) having a MOS structure on the surface of a bipolar transistor and used as a voltage-driven switching element.

[0002]

2. Description of the Related Art In recent years, attention has been paid to a MOSFET, a so-called IGBT, which uses conductivity modulation as a switching element. The IGBT has a high input impedance like the MOSFET, and can have a low on-resistance like the bipolar transistor. In order to increase the switching speed of the IGBT, a collector short structure has been adopted. FIG. 3 shows a basic structure of an IGBT having an n buffer region and a collector short structure. In this structure, p base region 2 is selectively formed in the surface layer of n ⁻ substrate 1, and n ⁺ emitter region 3 is selectively formed in the surface layer. n ⁻ substrate 1 and n ^{+ of} p base region 2
The surface region sandwiched by the emitter region 3 is the channel region 4
A gate electrode 6 is formed on the above portion via the gate oxide film 5 and is connected to the gate terminal G.
An emitter electrode 7 is in contact with part of the n ⁺ emitter region 3 in common with the p base region 2 and is connected to the emitter terminal E. The emitter electrode 7 is insulated from the gate electrode 6 by the insulating film 50.

An n buffer layer 8 is formed on the other side of the n ⁻ substrate 1 by a high impurity concentration thermal diffusion method, and a p ⁺ collector region 9 is also formed as a collector layer on a part of the lower surface of the n ⁺ buffer layer 8. Although it is formed by the thermal diffusion method, a part of it is replaced with the n ⁺ collector short region 10 having a higher impurity concentration than the buffer layer, instead of the entire surface. The p ⁺ collector region 9 and the n ⁺ collector short region 10 are commonly contacted by the collector electrode 11 connected to the collector terminal C to form a collector short type structure. In such a collector-short type IGBT, the emitter electrode 7 is grounded and a voltage is applied to the gate electrode 6 to inject an electron current from the n ⁺ emitter region 3 through the channel region 4 into the n ⁻ substrate 1, It passes through the n ⁺ buffer layer 8. A part of this electron current flows near the p / n junction on the lower surface of the n ⁺ buffer layer 8 to cause a potential drop, whereby p ⁺
From collector region 9 to n ⁺ buffer layer 8 and n ⁻ substrate 1
Holes are injected into the n ⁺ buffer layer 8 and the n ⁻ substrate 1, resulting in conductivity modulation. The hole current injected into the n ⁺ buffer layer 8 and the n ⁻ substrate 1 is p
It passes through just below the n ⁺ emitter region 3 of the base region 2 and exits to the emitter electrode 7. The emitter electrode 7 has p base region 2 and n
^{Since the +} emitter region 3 is short-circuited, the thyristor operation of the pnpn structure composed of the p ⁺ collector region 9, the n ⁺ buffer layer 8 and the n ⁻ substrate 1, the p base region 2, and the n ⁺ emitter region 3 is blocked, and the gate is -The element can be turned off by setting the potential between the emitters to zero.

As shown in FIG. 4, the n ⁺ collector short region 10 has a cylindrical shape extending from the contacting surface 12 of the collector electrode 11 to the n ⁺ buffer region 8 and is uniformly dispersed in the plane. Alternatively, strip-shaped n ⁺ collector short regions are provided in the collector layer in stripes. A large number of cells having such a basic structure form one unit IGBT element portion, and the gate electrode 6 is led out to a common gate wiring. Then, a plurality of such unit element portions are formed on one semiconductor wafer.

[0005]

In such a collector-short type IGBT with an n-buffer, as described above, when the element is on, an electron current passes from the n ⁺ emitter region 3 through the channel region 4 to the n ⁻ substrate 1. is injected, the injected electrons are passed through the n buffer layer 8 having a high impurity concentration, further the electron current in built-in field of the n ⁺ collector-short region 10 and p ⁺ collector region 9 is n ⁺ collector-short region 10
Be accelerated to. Therefore, the electron current passing through the p collector region 9 is reduced, so that the built-in electric field is not secured slowly. When the device is turned on, the n ⁺ emitter region 3, the n ⁻ substrate 1, the n ⁺ buffer layer 8, the n ⁺ collector short region 10
Are electrically connected with the same conductivity type,
Due to the formation of ET, a negative resistance, which is a characteristic of MOSFET, is generated in the current-voltage characteristic of the element as shown by the line 51 in FIG. Further, even if the injection of holes from the p ⁺ collector region 10 is started, the rate of recombination by the n ⁺ buffer layer 8 is large, and therefore the rate of conductivity modulation in the n ⁺ buffer layer 8 and the n ⁻ substrate 1. Becomes smaller and the saturation voltage increases. This leads to power loss at the time of turning on, which is a serious problem particularly when driving at a high frequency.

An object of the present invention is to eliminate the above-mentioned drawbacks, eliminate the negative resistance component at the time of ON, and reduce the saturation voltage, thereby providing an IGBT with a small power loss at the time of ON.

[0007]

In order to achieve the above object, the present invention provides a second conductivity type base region selectively formed in a surface layer on one side of a first conductivity type first layer. And an emitter region of the first conductivity type is selectively formed in the surface layer of the base region by sandwiching the exposed portion of the first layer, and the first conductivity type and the high impurity concentration region are formed on the other side of the first layer. The collector layer of the second conductivity type is formed via the buffer layer, and the portion sandwiched between the exposed portion of the first layer of the base region and the emitter region is used as the channel region, and is provided on the surface thereof via the gate insulating film. An IGBT having a plurality of cell structures each having a gate electrode, an emitter electrode commonly contacting an emitter region and a base region, and a collector electrode contacting a collector layer in one semiconductor device,
It is assumed that one region of the first conductivity type that penetrates the collector layer and reaches the buffer layer is provided for each of the plurality of cell structures. In that case, it is also effective that the collector electrode is made of a metal which makes ohmic contact with the layer of the second conductivity type and has Schottky contact with the region of the first conductivity type. Further, it is effective that the first conductivity type region penetrating the collector layer has a columnar shape with a cross-sectional area of 0.02 mm ² or more, and further that it has a columnar shape. Further, it is effective that the impurity concentration of the buffer layer and collector layer of these IGBTs is substantially uniform in the thickness direction, which can be realized by each layer being formed by epitaxial growth using the first layer as a substrate. .

[0008]

The collector short region of the first conductivity type for short-circuiting the collector electrode and the buffer layer is not provided dispersedly in the collector layer of the second conductivity type of each cell.
As a result, the currents due to the carriers injected through the channel of the surface layer when the device is turned on are all built-in electric field between the collector layer of the second conductivity type and the collector short region of the first conductivity type that penetrates the collector layer. It is accelerated by and concentrates on the collector short area. that time,
Since the distance that this current passes near the collector layer becomes longer and the current density increases, a potential drop occurs at the interface between the buffer layer of the first conductivity type and the collector region of the second conductivity type. Causes injection of carriers of opposite polarity into the first-conductivity-type first layer, resulting in conductivity modulation of the first layer. Since the area of the collector region is larger than that of the conventional collector short type IGBT, the positive feedback of the conductivity modulation is likely to occur, and the negative resistance of the current-voltage characteristic at the time of turning on disappears. In this case, since the current reaches the region linearly from the cell immediately above the through region of the first conductivity type that short-circuits the collector electrode and the buffer layer, the current should flow along the collector region of the second conductivity type. However, if the collector electrode makes a Schottky contact with the first conductivity type through region, carriers are blocked by the barrier and accumulated in the through region, resulting in the second conductivity type. A built-in potential drop is likely to occur between the collector region and the collector region, and the injection of reverse carriers from the collector region into the cell immediately above the first conductivity type through region is accelerated. Furthermore, by eliminating the impurity concentration gradient in the thickness direction of the collector layer and the buffer layer, the impurity concentration at the interface between the two layers changes abruptly, facilitating carrier ejection from the collector layer to the first layer, and increasing the diffusion current. Increase and the on-voltage decreases.

[0009]

1 and 2 are a cross-sectional view showing a single cell of an IGBT according to an embodiment of the present invention and a perspective view of the semiconductor element body with its lower surface facing upward, which are common to FIGS. 3 and 4. The parts have the same reference numerals. This IGBT has a thickness of 220 μm
Of n ^- p base region 2 are n width 40μm on the surface layer of the substrate 1 ^- it is formed across the exposed portion of the substrate 1, n ⁺ emitter region 3 is formed in the surface layer of the base region. Further, a gate electrode 6 is formed on the channel region 4 having a width of 5 μm via a gate oxide film 5. The above structure is the same as in FIGS. On the other hand, the bottom surface of the substrate 1 has 7 to 8
thick n ⁺ buffer layer 8 is provided in [mu] m, FIG. 3 also p ⁺ collector layer 9 of a thickness of 2~3μm on its lower surface is formed is similar to FIG. 4, n ⁺ collector A large number of short-circuit regions 10 are not provided, but one or a plurality of short-circuit regions 10 are formed in a unit IGBT element portion which is an aggregate of cells as shown in the figure. n ⁺ collector short region 10 is n ⁺
It has a higher impurity concentration than the buffer layer 8 and is formed in a columnar shape that penetrates the p ⁺ collector layer 9, but its diameter is 200 μm and is 0.1 μm.
It has a cross-sectional area of 0314 mm ² . By applying a voltage between the gate and emitter of the IGBT, the electron current injected from the n ⁺ emitter region 3 into the channel region 4 passes to the n ⁺ buffer layer 8. Electron current entering from the channel region into a common buffer layer 8 of each cell, the built-in electric field between the n ⁺ collector-short region 10 and the p ⁺ collector layer 9, n ⁺
Focus on collector short area 10. Thus, since the electron current is concentrated to the n ⁺ collector-short region 10 from each chip, the difference electron current 3, the structure shown in FIG. 4, p ⁺
As the distance passing through the side of the region 9 becomes longer and the current density thereof increases, a potential drop is caused, and injection of holes from the p ⁺ region is promoted to cause conductivity modulation. Furthermore p
^{Since the} area of the ⁺ region 9 is large, positive feedback of conductivity modulation is likely to occur, and as shown by the line 52 in FIG. 5, in the element IV characteristic, the negative resistance disappears and the saturation voltage is reduced. , The loss at the time of on is reduced. In addition, collector short area 10
If the cross-sectional area of is small, it becomes difficult for the electron current to flow in, so 0.02 mm ² or more is desirable.

FIG. 6 shows a cross section of a single cell of an IGBT according to another embodiment of the present invention, in which the n ⁺ buffer layer 8 has a cylindrical p ⁺ shape.
A thin n ⁺ collector short region 10 is formed on the surface of the collector layer 9 and extends in contact with the collector electrode 11.

A further embodiment shown in FIG. 7 has a structure similar to that of FIG. 6, but the collector electrode 14 in contact with the p ⁺ collector layer 9 and the n ⁺ collector short region 10 is between the n ⁺ region 10. A Schottky barrier is formed on. As described above, a metal having a work function larger than the electron affinity energy of n-type Si is selected as the material of the collector electrode 13 that forms the Schottky barrier for n-type Si.
Mo was used in this example. When a voltage is applied between the gate electrode 6 and the emitter electrode 7 of this IGBT, the electron current from the cell immediately above the n ⁺ collector short region 10 linearly reaches the n ⁺ region 10, so that the p ⁺ collector region 9
Does not flow in the vicinity of, and does not contribute to an increase in the potential drop at the junction between the p ⁺ collector region 9 and the n ⁺ buffer region 8. However, due to the existence of the Schottky barrier between the collector electrode 13 and the n ⁺ region 10, the current concentrated in the n ⁺ region 10 is accumulated, resulting in the n ⁺ collector short region 10 and the p ⁺ collector region 9 being formed. The built-in potential is likely to drop, the injection of holes from the p ⁺ region is accelerated, and the injection amount increases. Then, when the electron concentration further increases, the electrons flow into the collector electrode 13 over the barrier. As a result, as shown in FIG. 8, in the current / voltage characteristic 82 of the IGBT of the embodiment of FIG. 7, the on-voltage is further reduced as compared with the current / voltage characteristic 81 of the embodiment of FIG.

When the p ⁺ collector layer 9 in the above embodiment is formed by thermally diffusing impurities from the surface of the n ⁻ substrate, the impurity concentration of the collector layer 9 decreases as it gets closer to the n ⁺ buffer layer 8. Have. Further n ⁺
Since the buffer layer 8 is formed by thermal diffusion, an impurity concentration gradient also occurs in that layer. The electric field created by these concentration gradients tends to increase the saturation voltage, and the decrease in the hole concentration of the p ⁺ collector layer 9 at the interface between the n ⁺ buffer layer 8 and the p ⁺ collector layer 9 means that the diffusion It will reduce the current. In another embodiment of the present invention, an n ⁺ layer is epitaxially grown to a thickness of 10 μm or more on an n ⁻ substrate 1, and a surface layer of 5 μm is formed except for a columnar portion where a collector short region is formed. After the removal, the buffer layer 8 having a thickness of 5 μm or more is formed, and then the p ⁺ collector layer 9 is formed by epitaxial growth on the removed portion. An n ⁺ collector short region 10 is formed in the surface layer of the n ⁺ buffer layer 8 exposed in the collector layer 9 by impurity diffusion. In this way, the impurity concentration gradient in the thickness direction of the n ⁺ buffer layer 8 and the p ⁺ collector layer 9 is eliminated, and the hole concentration of the p ⁺ collector layer 9 at the interface is adjusted to be constant with the surface concentration. Can be reduced. That is, as shown in FIG. 9, the IGB of the embodiment in which the buffer layer 8 and the collector layer 9 are formed by the thermal diffusion method.
Compared with the current / voltage characteristic 91 of T, the on-voltage was lower in the current / voltage characteristic 92 of the IGBT of the example formed by the epitaxial method.

Although the embodiments of the n-channel IGBT have been described above, the p-channel IG in which the conductivity types of the respective parts are exchanged is described.
It is clear that the same characteristics as described above can be obtained by carrying out in BT.

[0014]

According to the present invention, one short circuit portion for collector short circuit is not provided in a distributed manner, but one is provided for a plurality of cells, and carriers injected through the channel on the surface of each cell are buffer layers. Since the conductivity modulation is promoted by allowing the current to flow concentratedly through the short circuit via the rectifier, the negative resistance component of the IV characteristic at the time of ON is eliminated, and the power at the time of ON of the element having a high switching speed is eliminated. The loss could be reduced. Further, by using a metal forming a Schottky barrier between the short-circuited portion and the short-circuited portion as a material for the collector electrode, carriers concentrated in the short-circuited portion are accumulated, or the impurity concentration of the buffer layer and the collector layer is substantially uniform in the thickness direction. By promoting the injection of carriers from the collector layer, the effect of promoting conductivity modulation could be further enhanced.

[Brief description of drawings]

FIG. 1 is a sectional view of a single cell of an IGBT according to an embodiment of the present invention.

FIG. 2 is a perspective view of the semiconductor element body of the IGBT shown in FIG.

FIG. 3 is a cross-sectional view of a conventional collector short-type IGBT single cell.

FIG. 4 is a perspective view with the lower surface of the semiconductor element body of the IGBT shown in FIG. 2 facing up.

FIG. 5: I of the conventional example and the embodiment of the present invention shown in FIG.
GBT current / voltage diagram

FIG. 6 is a sectional view of an IGBT single cell according to another embodiment of the present invention.

FIG. 7 is a sectional view of an IGBT single cell according to another embodiment of the present invention.

FIG. 8 is an IGBT according to the embodiment of the present invention shown in FIGS. 6 and 7.
Current / voltage diagram

FIG. 9 is a sectional view of a single cell of an IGBT according to yet another embodiment of the present invention.

[Explanation of symbols]

1 n ^- Substrate 2 p Base region 3 n ⁺ Emitter region 4 Channel region 5 Gate oxide film 6 Gate electrode 7 Emitter electrode 8 n ⁺ Buffer layer 9 p ⁺ Collector layer 10 n ⁺ Collector short region 11 Collector electrode 13 Schottky collector electrode

Claims (6)

[Claims] 1. A base region of a second conductivity type is selectively formed in a surface layer on one side of a first layer of the first conductivity type, and a base layer of the first layer is selectively formed in a surface layer of the base region. A first-conductivity-type emitter region is formed across the exposed portion, and a second-conductivity-type collector layer is formed on the other side of the first layer with a first-conductivity-type buffer layer having a high impurity concentration, and a base. A region sandwiched between the exposed portion of the first layer of the region and the emitter region is used as a channel region, and a gate electrode provided on the surface thereof via a gate insulating film, an emitter electrode commonly contacting the emitter region and the base region, and In one semiconductor device having a plurality of cell structures each having a collector electrode in contact with the collector layer, a plurality of first conductivity type regions contacting the collector electrode and penetrating the collector layer to reach the buffer layer are provided. Cell structure Insulated gate bipolar transistor, characterized in that provided one Te. 2. The insulated gate bipolar transistor according to claim 1, wherein the collector electrode is made of a metal which makes ohmic contact with the layer of the second conductivity type and has Schottky contact with the region of the first conductivity type. 3. The insulated gate bipolar transistor according to claim 1, wherein the first conductivity type region penetrating the collector layer is a column having a cross-sectional area of 0.02 mm or more. 4. The insulated gate bipolar transistor according to claim 3, wherein the first conductivity type region penetrating the collector layer is cylindrical. 5. The insulated gate bipolar transistor according to claim 1, wherein the impurity concentrations of the buffer layer and the collector layer are substantially uniform in the thickness direction. 6. The insulated gate bipolar transistor according to claim 5, wherein the buffer layer and the collector layer are layers formed by epitaxial growth using the first layer as a substrate.