JP4052463B2 - High voltage Schottky diode - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high withstand voltage Schottky diode having a low forward voltage and excellent switching characteristics, and is mainly used for a switching power supply.
[0002]
[Prior art]
Although it has been difficult to stably obtain the withstand voltage of a planar Schottky diode, this defect can be improved by protecting the periphery of the Schottky junction with a guard ring having a conductivity type opposite to that of the semiconductor substrate. .
[0003]
When the forward voltage is 0.6V or more, minority carriers are injected from the guard ring, and the high speed is impaired. For this reason, it has been considered that a diffusion layer of an opposite conductivity type is formed on the surface of the guard ring and minority carrier injection from the guard ring is prevented by this pn junction (see Patent Document 1).
[0004]
Furthermore, a plurality of regions opposite to the semiconductor substrate, that is, the same conductivity type as that of the guard ring are formed on the Schottky junction surface portion, and the withstand voltage can be improved more stably by the effect of relaxing the electric field by these regions. (See Patent Documents 2 and 3).
[0005]
However, in a Schottky diode using a silicon semiconductor, when the withstand voltage is 150 V or higher, the voltage drop due to the series resistance increases, and the forward voltage becomes larger than the forward voltage of the pn junction element. For this reason, the breakdown voltage of the Schottky diode was only 150V.
[0006]
A plurality of regions of a conductivity type opposite to the semiconductor substrate are mixed in a Schottky junction surface portion of a high breakdown voltage Schottky diode having a breakdown voltage of 150 V or higher, and minority carriers are injected from the pn junction portion to reduce the series resistance. (See Patent Documents 4, 5, and 6, Non-Patent Documents 3 and 4.) FIG. 7 is a diagram for explaining a first example of a conventional high voltage Schottky diode based on this concept.
[0007]
An n-type semiconductor layer 1 is formed on the n ⁺ -type semiconductor layer 2 by an epitaxial method, and a plurality of p-type semiconductor regions 3 are formed on the surface of the n-type semiconductor layer 1. A first electrode 5 is formed on the surface of the n-type semiconductor layer 1 including a plurality of p-type semiconductor regions 3. A second electrode 6 is formed on the lower surface of the n ⁺ type semiconductor layer 2.
[0008]
The second electrode 6 fabricated on the lower surface of the n ⁺ type semiconductor layer 2 has an ohmic junction. The plurality of p-type semiconductor regions 3 and the first electrode 5 are in ohmic contact. The concentration of the n-type semiconductor layer 1 is relatively low, and the n-type semiconductor layer 1 and the first electrode 5 form a Schottky junction.
[0009]
When a positive voltage is applied to the first electrode 5 and the second electrode 6 is set to a negative voltage, a forward current flows from the first electrode 5 to the second electrode 6. When the forward voltage is low, that is, when the forward current is small, the forward current flows through the Schottky junction.
[0010]
Next, when the forward current increases, the forward voltage increases due to the resistance of the n-type semiconductor layer 1. By this voltage, a voltage is applied to the pn junction between the n-type semiconductor layer 1 and the p-type semiconductor region 3, and holes which are minority carriers are injected from the p-type semiconductor region 3, and the n-type semiconductor layer is subjected to conductivity modulation. The resistance of 1 decreases. Therefore, it operates with a lower forward voltage than a Schottky diode in which no pn junction is mixed. However, due to the injected accumulated carriers, the reverse recovery time becomes longer and the high speed is impaired.
[0011]
For this reason, in order to shorten the reverse recovery time, a lifetime killer must be introduced to shorten the lifetime and control the injection amount (see Patent Documents 7 and 8 and Non-Patent Document 5). . However, generally, there is a drawback that the temperature coefficient of the lifetime is large, the lifetime is increased at a high temperature, and the reverse recovery time is increased.
[0012]
When a positive voltage is applied to the second electrode 6 and the first electrode 5 is set to a negative voltage, the Schottky junction is reverse-biased and a reverse current flows. If the pn junction formed by the p-type semiconductor region 3 and the n-type semiconductor layer 1 is reverse-biased, and the depletion layer is sufficiently widened in the n-type semiconductor layer 1 between the adjacent p-type semiconductor regions 3, the Schottky junction It is possible to relax the electric field applied to the substrate and to stably obtain a high breakdown voltage.
[0013]
On the other hand, a conventional low breakdown voltage Schottky diode having a low Schottky barrier that does not use injection from a pn junction does not have such a disadvantage and can realize high-speed switching without a lifetime killer. However, if the withstand voltage is increased while the voltage is low, there is a drawback in that the forward voltage increases because of less injection.
[0014]
By increasing the Schottky barrier, minority carriers can be injected from the Schottky barrier (see Patent Document 9, Non-Patent Documents 6, 7, and 8). When the number of minority carriers injected is large, the forward voltage decreases, but the high speed is impaired by the accumulation of minority carriers. In this case as well, it is possible to introduce a lifetime killer in order to shorten the reverse recovery time. However, in general, there is a disadvantage that the temperature coefficient of the lifetime is large, the lifetime is increased at a high temperature, and the reverse recovery time is increased.
[0015]
If the height of the Schottky barrier is set low so as to ensure high speed without introducing a lifetime killer as described above, minority carrier injection does not occur, resulting in a rise in forward voltage. .
[0016]
As described above, when the height of the Schottky barrier is set high in order to lower the forward voltage, naturally, minority carrier injection increases. Although the forward voltage decreases, the high speed performance is impaired due to the accumulation of minority carriers. In this case as well, it is possible to introduce a lifetime killer in order to shorten the reverse recovery time, but there is a disadvantage that the number of processes increases. In general, the temperature coefficient of the lifetime is large, and when the temperature is high, there is a disadvantage that the lifetime becomes longer and the reverse recovery time becomes longer.
[0017]
[Patent Document 1]
Japanese Examined Patent Publication No. 49-034028 (page 4, Fig. 7)
[Patent Document 2]
Japanese Laid-Open Patent Publication No. 52-024465 (page 4, FIG. 1)
[Patent Document 3]
JP 56-088376 (page 11, FIG. 11)
[Patent Document 4]
JP 56-035473 (page 4, FIG. 4)
[Patent Document 5]
Japanese Patent Laid-Open No. 60-031271 (page 5, FIG. 1)
[Patent Document 6]
US Pat. No. 5,241,195 (FIGS. 1 and 3)
[Patent Document 7]
JP 05-218389 A ([0006], page 4, FIG. 1)
[Patent Document 8]
US Patent Application Publication No. 2002/0008246 (FIGS. 1 and 2)
[Patent Document 9]
JP 58-148469 A (page 7, FIG. 5)
[Non-Patent Document 1]
MASAYOSHI NAITO et al., IEEE Trans.Electron Devices, Vol.23, No.8, pp.945-949 (1976)
[Non-Patent Document 2]
YOSHIHITO AMEMIYA et al., IEEE Trans.Electron Devices, Vol.29, No.2, pp.236-243 (1982)
[Non-Patent Document 3]
YOSHITERU SHIMIZU et al., IEEE Trans. Electron Devices, Vol.31, No.9, pp.1314-1319 (1984)
[Non-Patent Document 4]
B. JAYANT BALIGA, IEEE Trans. Electron Device Letters, Vol.8, No.9, pp.407-409 (1987)
[Non-Patent Document 5]
Y. Khersonsky et al., PCIM May, pp.16-25 (1992)
[Non-Patent Document 6]
DLSCHARFETTER, Solid-State Electronics, Vol.8, pp.299-311 (1965)
[Non-Patent Document 7]
Katsusuke Ichikawa et al., INTELEC, pp.520-526 (1983)
[Non-Patent Document 8]
YOSHIHITO AMEMIYA et al., IEEE Trans. Electron Devices, Vol.31, No.1, pp.35-42 (1984)
[0018]
[Problems to be solved by the invention]
The present invention is intended to solve the above problem, and provides a high breakdown voltage Schottky diode having a low forward voltage and excellent switching characteristics in a high breakdown voltage Schottky diode of 200 V or higher.
[0019]
[Means for Solving the Problems]
The present invention constitutes a high-voltage Schottky diode having a low forward voltage and suitable for high-speed switching by having a Schottky junction for injecting minority carriers and providing a passage having an npn structure.
As means for solving the above-described problems, a high breakdown voltage Schottky diode of the present invention includes a first conductivity type first semiconductor layer and a higher impurity concentration than the first semiconductor layer provided below the first semiconductor layer. A first conductivity type second semiconductor layer, a second conductivity type first semiconductor region selectively formed on the surface side of the first semiconductor layer, and the first conductivity type on the surface side of the first semiconductor region. A second semiconductor region of a first conductivity type formed so as to be surrounded by the semiconductor region; a first electrode formed on a surface of the first semiconductor layer; and a first electrode formed on a back surface of the second semiconductor layer. Two electrodes,
The first electrode, wherein the surface of the first semiconductor layer a first semiconductor region and the second said at sites other than the semiconductor region first semiconductor layer and the Rutotomoni obtain a Schottky junction, the first semiconductor layer and obtaining the second semiconductor region and the ohmic junction at the surface, the said said first semiconductor region of higher impurity concentration than the impurity concentration of the first semiconductor layer, impurity concentration higher than the impurity concentration of the first semiconductor region first A portion that causes minority carrier injection from the first electrode to the first semiconductor layer when a forward voltage is applied to the first electrode with respect to the second electrode. It is a junction.
Further, the surface concentration of the first semiconductor region is set so as to obtain a Schottky junction with the first electrode at the site on the surface of the first semiconductor region.
Further, the impurity concentration of the second semiconductor layer is 1E18 atom / cm ³ or less.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining the structure of the first embodiment of the present invention.
[0021]
An n-type semiconductor layer 1 is formed on the n ⁺ -type semiconductor layer 2 by an epitaxial method, and a plurality of p-type semiconductor regions 3 are formed on the surface of the n-type semiconductor layer 1. A first electrode 5 is formed on the surface of the n-type semiconductor layer 1 including a plurality of p-type semiconductor regions 3. A second electrode 6 is formed on the lower surface of the n ⁺ type semiconductor layer 2.
[0022]
The n ⁺ -type semiconductor layer 2 is a semiconductor substrate on which the n-type semiconductor layer 1 is epitaxially grown, and has a specific resistance as small as 0.010 Ω · cm or less in order to reduce the series resistance, and has a thickness of 450 μm that is easy to handle in the process. . The n-type semiconductor layer 1 was epitaxially grown on the n ⁺ -type semiconductor layer 2 with a thickness of 60 μm and an impurity concentration of 1E14 atoms / cm ³ so as to obtain a withstand voltage of 600V.
[0023]
A thermal oxide film is formed on the surface of the n-type semiconductor layer 1 epitaxially grown on the n ⁺ -type semiconductor layer 2, and a plurality of p-type semiconductor regions 3 are formed by this photographic process and an oxide film etching process. A window was opened at a position, and boron was diffused in an oxidizing atmosphere to form a p-type semiconductor region 3 having a surface concentration of 5E19 atoms / cm ³ and a diffusion depth of 5 μm. The interval between the p-type semiconductor regions 3 on the surface of the n-type semiconductor layer 1 is 30 μm.
[0024]
In order to ensure a withstand voltage, the interval is desirably a width in which a depletion layer extending from a pn junction formed by adjacent p-type semiconductor regions 3 overlaps at a working voltage or less, and a small number so that minority carriers are efficiently extracted. It is desirable to be not more than twice the carrier diffusion length. In the structure of the present invention, the p semiconductor region 3 serves as an effective area at the time of forward bias, so that the interval can be made relatively narrow, and the electric field at the Schottky junction surface can be relaxed at the time of reverse bias.
[0025]
When the impurity concentration of the n-type semiconductor layer 2 is 1E14 atoms / cm ^{3 as} in the embodiment and a reverse bias of 400 V is applied, the depletion layer width is about 20 μm. Therefore, the width of the Schottky junction is set to 30 μm as an interval at which the depletion layer width is sufficiently connected.
[0026]
Utilizing an oxide film formed by boron diffusion, this oxide film is opened in a window where a plurality of n ⁺ -type semiconductor regions 4 are formed by a photographic process and an oxide film etching process, and phosphorus is diffused in an oxidizing atmosphere. Then, an n ⁺ type semiconductor region 4 having a surface concentration of 1E20 atoms / cm ³ and a diffusion depth of 3 μm was formed. The n ⁺ type semiconductor region 4 is formed in the region of the p type semiconductor region 3, and the width of the n ⁺ type semiconductor region 4 on the surface of the p type semiconductor region 3 is 12 μm. The width of the p-type semiconductor region 3 is 18 μm.
[0027]
A p-type semiconductor sandwiched between the n ⁺ -type semiconductor region 4 and the n-type semiconductor layer 1 so as to prevent a breakdown voltage from being reduced by an npn structure including the n ⁺ -type semiconductor region 4, the p-type semiconductor region 3, and the n-type semiconductor layer 1. The amount of impurities in the region 3 (corresponding to the base layer of the npn structure portion) is adjusted, and the surface concentration of the n ⁺ type semiconductor region 4 is set to a high concentration so that an ohmic connection with the first electrode 5 can be easily obtained. It was.
[0028]
The periphery of the Schottky junction is protected by an npn-structured guard ring formed by the n ⁺ type semiconductor region 4, the p-type semiconductor region 3, and the n-type semiconductor layer 1 (not shown).
[0029]
The first electrode 5 and the plurality of n ⁺ type semiconductor regions 4 are in ohmic contact. The first electrode 5 and the n-type semiconductor layer 1 form a Schottky junction. This barrier is subject to 0.76 eV or more. In this example, platinum was used as the metal forming the Schottky barrier. The first electrode has a three-layer system of platinum, chromium, and nickel so that solder connection is easy.
[0030]
The minority carrier injection amount p (X1) in the large injection region from the depletion layer end (X1) of the Schottky junction can be expressed by an equation (see Reference 6). Here, _ni is the intrinsic concentration, J is the current density, and _JS is the saturation current density flowing through the Schottky barrier. Injection volume is inversely proportional to the impurity concentration N _D, inversely proportional to the saturation current J _S. That is, as the Schottky barrier increases, the number of injections increases logarithmically.
[0031]
p (X1) = (n _i ² / N _D ) (J / J _s )
[0032]
If the impurity concentration _{N D} of 8E14atom / cm ^3, the breakdown voltage is ideally leaving 400V. Equivalent concentration implanted assume the impurity concentration _{N D} is the Schottky barrier height 8E14 that there is in the impurity concentration _{N D} is 0.86EV, the 1E14 0.76 eV is injection condition of minority carriers.
[0033]
Therefore, when applying the present invention to the above high-voltage Schottky diode 400V is the Schottky barrier height is 0.76eV above, _{N D} is required 8E14 or less. The first electrode 5 and the plurality of n ⁺ type semiconductor regions 4 are in ohmic contact.
[0034]
The second electrode 6 is a two-layer system using chromium as an ohmic metal and nickel on the surface of the chromium so as to facilitate solder connection.
[0035]
FIG. 3 is a concentration distribution of injected carriers by numerical analysis in the depth direction of the Schottky junction when a forward voltage of 0.9 V is applied in the first embodiment of the present invention shown in FIG. The forward current density at this time is 200 A / cm ² . The vertical axis represents the injected carrier and is shown in logarithm. The horizontal axis represents the depth of the n-type semiconductor layer 1, and the zero point corresponds to the Schottky junction. Solid line a is the injected electron, broken line b is the injected hole, and dotted line c is the impurity concentration.
[0036]
There is 7E14 atom / cm ³ hole injection from the Schottky barrier on the anode side, and 2E17 atom / cm ³ electron injection from the n ⁺ type semiconductor layer 2 on the cathode side. The first conventional example has substantially the same injection amount and injection shape.
[0037]
FIG. 4 is a concentration distribution of injected carriers by numerical analysis when the forward voltage of FIG. 4 is applied in the depth direction of the npn junction portion in the first embodiment of the present invention of FIG. The vertical axis represents the injected carrier and is shown in logarithm. The horizontal axis indicates the depth of the n-type semiconductor layer 1, and the zero point corresponds to the surface portion of the n ⁺ -type semiconductor region 4. Solid line a is the injected electron, broken line b is the injected hole, and dotted line c is the impurity concentration. Electrons injected from the cathode pass through the p-type semiconductor region 3 and reach the n ⁺ -type semiconductor region 4. In addition, injection of holes from the p-type semiconductor region 3 is suppressed by the n ⁺ -type semiconductor region 4.
[0038]
FIG. 5 shows the concentration distribution of injected carriers when the same 0.9 V forward voltage as in FIG. 3 is applied to the pn junction portion in FIG. The vertical axis represents the injected carrier and is shown in logarithm. The horizontal axis indicates the depth of the n-type semiconductor layer 1, and the zero point corresponds to the surface portion of the n ⁺ -type semiconductor region 4. Solid line a is the injected electron, broken line b is the injected hole, and dotted line c is the impurity concentration.
[0039]
Comparing FIG. 4 of the present invention with FIG. 5 of the conventional first example, it can be seen that the accumulation amount of electrons and holes is reduced on the anode side. This shows that, in the first conventional example shown in FIG. 5, more carriers are injected than in the p-type semiconductor region 3, whereas the present invention has a structure that suppresses injection from there.
[0040]
In the present invention having the n ⁺ -type semiconductor region 4, the p-type semiconductor region 3 not only provides an effect of relaxing the electric field applied to the Schottky junction when a reverse voltage is applied, but also acts as an effective area for driving a forward current during forward bias. . The operation is as follows. At a large current density, electrons injected from the second electrode 6 reach the n-type semiconductor layer 1 and further recombine with holes in the p-type semiconductor region 3, but most of the electrons are in the n ⁺ -type semiconductor region. 4 can be reached. An npn junction formed of the n ⁺ type semiconductor region 4, the p type semiconductor region 3, and the n type semiconductor layer 1 performs an npn bipolar transistor operation. That is, a part of the lateral current flowing from the n-type semiconductor layer 1 to the Schottky junction reaches the n ⁺ -type semiconductor region 4 via the p-type semiconductor region 3 and becomes a current path.
[0041]
Accordingly, the forward voltage characteristic of almost the same level as that of the high breakdown voltage Schottky diode (hereinafter referred to as the second conventional example) having a structure without the p-type semiconductor region 3 shown in FIG. be able to.
[0042]
The forward voltage is 0.86 V (current density 100 A / cm ² ) in the first embodiment of the present invention, 0.80 V in the first conventional example, and 0. 0 in the second conventional example. 84V.
[0043]
If the reverse recovery time is 1 in the first embodiment of the present invention, it is 3 in the first conventional example and 1.0 in the second conventional example.
[0044]
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a view for explaining the structure of the second embodiment of the present invention.
[0045]
Compared to the first embodiment of the present invention, an oxide film 7 is formed on the surface of the p-type semiconductor region 3 exposed on the surface of the n-type semiconductor layer 1. If the surface of the p-type semiconductor region 3 is connected to the first electrode 5, minority carriers may be injected from the pn junction formed by the p-type semiconductor region 3 and the n-type semiconductor layer 1.
[0046]
In this embodiment, since there is an oxide film as an insulator between the surface of the p-type semiconductor region 3 and the first electrode 5, the implantation from the pn junction by the p-type semiconductor region 3 and the n-type semiconductor layer 1 is completely performed. It is pressed down. The characteristics are almost the same as those in the first embodiment, such as forward voltage, breakdown voltage, and reverse recovery time.
[0047]
Next, a third embodiment will be described. In the first embodiment of FIG. 1, the junction between the p-type semiconductor region 3 and the first electrode can form a Schottky barrier by setting the surface concentration of the p-type semiconductor region 3 to 1E18 atoms / cm ³ or less. it can. Therefore, this portion has a stacked structure of a Schottky junction, a p-type semiconductor region 3, and an n-type semiconductor layer 1. When the forward operation of the high breakdown voltage Schottky diode is performed, the Schottky junction is formed on the p-type semiconductor region 3. As a result of the reverse series, minority carrier injection does not occur. That is, it is not necessary to form the oxide film of Example 2. The characteristics are the same as in the second embodiment.
[0048]
Next, a fourth embodiment will be described. 1 differs from the first embodiment in that the impurity concentration of the n ⁺ type semiconductor layer 2 on the cathode side is 1E18 atom / cm ³ or less.
[0049]
FIG. 6 shows the concentration distribution of injected carriers when the same forward voltage of 0.9 V as in FIG. 3 is applied in the depth direction of the Schottky junction portion in the fourth embodiment of the present invention. The vertical axis indicates the logarithm of the injected carrier. The horizontal axis indicates the depth of the n-type semiconductor layer 1, and the zero point corresponds to the surface portion of the n-type semiconductor layer 1.
[0050]
The line group A shown in the upper side of FIG. 6 is the case of the first conventional example, and the line group B shown in the lower side of FIG. 6 is the case of the fourth embodiment of the present invention. Solid line a is the injected electron, broken line b is the injected hole, and dotted line c is the impurity concentration.
[0051]
By reducing the impurity concentration of the n ⁺ type semiconductor layer 2 on the cathode side, not only the amount of injected carriers from the cathode side can be reduced, but also the amount of injection from the anode side which is a Schottky junction is reduced, Compared to the first example of the prior art and the first, second and third embodiments of the present invention, the number is significantly reduced.
[0052]
Accordingly, minority carrier injection is significantly less than in the conventional example, and the reverse recovery time is significantly shortened although the forward voltage is slightly increased. Comparing the forward voltage at a current density of 100 A / cm ² , it is 1.20 V in the fourth embodiment of the present invention, 0.80 V in the first conventional example, and 0 in the second conventional example. .84V.
[0053]
Also, if the reverse recovery time is 1 in the first embodiment of the present invention, it is 3 in the first conventional example, 1 in the second conventional example, and in the fourth embodiment of the present invention. It is 1/10.
[0054]
In the present invention, the minority carrier injection level can be adjusted by appropriately selecting the barrier height of the Schottky junction or by reducing the impurity concentration of the n ⁺ type semiconductor layer 2 on the cathode side, but a lifetime killer is introduced. In addition, it is possible to optimize the height of the Schottky barrier in consideration of both the lifetime and the height of the Schottky barrier or the impurity concentration of the n ⁺ type semiconductor layer 2. Therefore, the structure of the present invention falls within the technical scope of the present invention even if a lifetime killer is included.
[0055]
In the embodiment of the present invention, the p-type semiconductor region 3 and the n ⁺ -type semiconductor region 4 having the planar structure have been described. However, a groove is formed in the n-type semiconductor layer 1 to form the p-type semiconductor region 3 and the n ⁺ -type semiconductor region 4. It may be formed.
[0056]
Although the silicon semiconductor has been described, the present invention can be applied to other semiconductors such as germanium, gallium arsenide, and silicon carbide.
[0057]
In addition, although an example using an n-type semiconductor layer as the first semiconductor layer 1 has been described, even if a p-type semiconductor is used and the p-type and the n-type of the above-described embodiment are interchanged, It is natural to enter the range.
[0058]
The first electrode 5 for forming the Schottky barrier may not be a metal, but may be a silicide, an intermetallic compound, or a solid solution of metal.
[0059]
【The invention's effect】
According to the present invention, it is possible to realize a high breakdown voltage Schottky diode excellent in switching characteristics with a low forward voltage and having a good trade-off between the two.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the structure of a first embodiment of the present invention.
FIG. 2 is a diagram for explaining the structure of a second embodiment of the present invention.
FIG. 3 is a diagram for explaining a carrier distribution in a Schottky junction portion according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining a carrier distribution of an npn portion according to the first embodiment of the present invention.
FIG. 5 is a diagram for explaining a carrier distribution of a pn portion according to the first embodiment of the present invention.
FIG. 6 is a diagram for explaining a carrier distribution according to a fourth embodiment of the present invention.
FIG. 7 is a diagram for explaining a first conventional example.
[Explanation of symbols]
1 n-type semiconductor layer 2 n ⁺ -type semiconductor layer 3 p-type semiconductor region 4 n ⁺ -type semiconductor region 5 first electrode 6 second electrode 7 oxide film

Claims (3)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer provided under the first semiconductor layer;
A first semiconductor region of a second conductivity type selectively formed on the surface side of the first semiconductor layer;
A second semiconductor region of a first conductivity type formed on the surface side of the first semiconductor region so as to be surrounded by the first semiconductor region;
A first electrode formed on a surface of the first semiconductor layer;
A second electrode formed on the back surface of the second semiconductor layer,
The first electrode, wherein the surface of the first semiconductor layer a first semiconductor region and the second said at sites other than the semiconductor region first semiconductor layer and the Rutotomoni obtain a Schottky junction, the first semiconductor layer Obtaining an ohmic junction with the second semiconductor region on the surface;
The first semiconductor region having an impurity concentration higher than that of the first semiconductor layer;
The second semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region,
The Schottky junction is a portion that causes minority carrier injection from the first electrode to the first semiconductor layer when a forward voltage is applied to the first electrode with respect to the second electrode. Withstand voltage Schottky diode. 2. The high breakdown voltage Schottky according to claim 1, wherein a surface concentration of the first semiconductor region is set in order to obtain a Schottky junction with the first electrode at the portion of the surface of the first semiconductor region. diode. 2. The high breakdown voltage Schottky diode according to claim 1, wherein an impurity concentration of the second semiconductor layer is set to 1E18 atom / cm ³ or less.

Images