JP2000269518A - Powering semiconductor device and method for forming semiconductor layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make compatible a high turn-off gain and low off-resistance by a method wherein there is formed an auxiliary region where a first conductive semiconductor layer and a second conductive semiconductor layer having a carrier integral amount the repetitive direction of a predetermined value or less are alternately adjacent to each other. SOLUTION: An auxiliary region 16 where a P-type layer and an N-type layer are alternately disposed is formed in a region sandwiched between P+-type gate layers 4, and a P-type layer of the auxiliary region 16 is connected to the P+-type gate layers 4. Here, a concentration and width of the respective layers are established so that carrier integral amounts calculated from concentration X width of the P-type layer and N-type layer of this auxiliary region 16 substantially agree with each other at schematically 5×1012 cm2 or less. With this structure, since the concentration of the N-type layer of the auxiliary region 16 can be established to be higher than that of an N--type base layer 2, it is possible to decrease resistance components of the region pinched between the P+-type gate layers 4. Accordingly, it is possible to obtain a high turn-off gain, and also to realize a sufficiently low on-resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a method of forming a semiconductor layer, and more particularly to a static induction transistor having improved turn-off gain and on-resistance, and a Schottky transistor having improved leakage current and on-resistance. Regarding diodes.

[0002]

2. Description of the Related Art FIG. 22 is a perspective view including a sectional view showing an element structure of a conventional junction type static induction transistor (SIT). The basic structure of this device is as follows: an N ⁺ type drain layer 1, an N ⁻ type base layer 2, an N ⁺ type source layer 3, a P ⁺ type gate layer 4, a drain electrode 5, a source electrode 6, and a gate electrode 7.
Is a junction type SIT.

In this prior art device structure, the gate electrode 7
When the potential of the source electrode 6 is made positive with respect to the potential of the source electrode 6,
State, and when turned negative, the state becomes non-conductive. In non-conducting state
Is P ⁺Type gate layer 4 and N⁻Joining with mold base layer 2
Is reverse biased, the depletion layer extends, and N⁺Type source layer 3 straight
Raise the lower potential to N⁺From the source layer 3
Injection is blocked. Turn off with such element structure
To increase the gain, P⁺By narrowing the distance between the mold gate layers 4
N⁺It is necessary to increase the potential directly under the mold source layer 3
there were.

However, during the P ⁺ -type gate layer 4 high-resistance N ^- part because they are formed by type base layer 2, passes electrons in the conducting state and reduce the distance P ⁺ -type gate layer 4 However, the turn-off gain cannot be increased sufficiently.

In addition, the potential of the gate electrode 7 is
The element keeps the non-conductive state when it is equal to the potential of
To realize the so-called normally-off characteristic,⁺Type gate
The depletion layer formed by the built-in potential
Or shrink to fit⁺Mesh between mold gate layers 4
Shape P⁺Means to add a mold layer or a single P-type layer
In some cases, P⁺Type gate
High resistance N between layers 4 ⁻Mold base layer 2
Therefore, the increase of the on-resistance was inevitable.

FIG. 23 shows a conventional MOS type electrostatic induction type transformer.
Perspective including a cross-sectional view showing the element structure of a transistor (SIT)
FIG. The basic structure of this element is N⁺Drain layer
1, N ⁻Mold base layer 2, N⁺Source layer 3, drain electrode
Whether the pole 5, the source electrode 6, the gate electrode 7, the gate insulating film 8
MOS-type SIT.

In this conventional device structure, the gate electrode 7
Is made conductive when the potential of the source electrode 6 is made positive with respect to the potential of the source electrode 6, and made non-conductive when the potential is made negative. A gate insulating film 8 is in the non-conducting state N ^- N from the interface between the mold base layer 2 ^-
A depletion layer extends to a type base layer 2, to increase the potential immediately under the N ⁺ -type source layer 3 and prevents the injection of electrons from the N ⁺ -type source layer 3. In this element structure, since a storage layer having a high electron concentration is formed at the interface between the gate insulating film 8 and the N ⁻ type base layer 2 in a conductive state, the resistance between the gate electrodes 7 as in the junction type SIT described above. Is not a problem.

However, in this element structure, the junction type S
Since the elongation of the depletion layer is smaller than that of IT, it is necessary to further narrow the interval between the gate electrodes 7 to increase the potential immediately below the N ⁺ type source layer 3. From the viewpoint of the manufacturing process, there is a minimum value not only in the distance between the gate electrodes 7 but also in the width of the gate electrodes 7, and the area occupied by the gate electrodes 7 in the element region increases by reducing the distance between the gate electrodes 7. However, there is a problem that the on-resistance increases after all.

FIG. 24 is a perspective view including a sectional view showing an element structure of a conventional junction barrier control Schottky diode (SBD). The basic structure of this device is such that the cathode electrode 1 in ohmic contact with the N ⁺ type cathode layer 9, the N ⁻ type cathode layer 10, the P ⁺ type layer 11, and the N ⁺ type cathode layer 9.
2. An anode electrode 13 in ohmic contact with the P ⁺ type layer 11 and in Schottky contact with the N ⁻ type cathode layer 10.
Is a junction barrier control SBD composed of

In the conventional device structure, the cathode electrode 12
Is higher than the potential of the anode electrode 13 in a non-conductive state.
Is P⁺Mold layer 11 and N⁻Contact with the mold cathode layer 10
Is reverse biased, the depletion layer extends, and P⁺Between mold layers 11
To stop the flow of electrons. So
As a result, the barrier height is low to reduce the on-resistance.
Even when a metal is used for the anode electrode 13, the leakage current
Can be kept small. Such an element structure
In order to further reduce the leakage current, ⁺Mold layer 1
It is necessary to narrow the interval of 1 and increase the potential between them
was there.

However, between the P ⁺ -type layers 11, a high-resistance N ⁻
P ⁺ type layer 1
If the interval of 1 is reduced, the resistance of the portion where electrons pass in the conductive state increases and the on-resistance increases, and the leak current cannot be reduced sufficiently.

FIG. 25 is a perspective view including a sectional view showing an element structure of a conventional MOS barrier controlled Schottky diode (SBD). The basic structure of this device is as follows: an N ⁺ type cathode layer 9, an N ⁻ type cathode layer 10, and an N ⁺ type cathode layer 9.
Electrode 12 and insulating film 1 in ohmic contact with
The MOS barrier control SBD includes the anode electrode 13 which is in ohmic contact with the electrode 15 formed through the anode electrode 4 and in Schottky contact with the N ⁻ type cathode layer 10.

In this prior art device structure, the potential of the cathode electrode 12 is lower than that of the anode electrode 13 in this prior art device structure.
In the non-conducting state higher than the potential, the depletion layer extends from the interface between the insulating film 14 and the N ⁻ -type cathode layer 10 to the N ⁻ -type cathode layer 10, thereby increasing the potential between the electrodes 15 and blocking the flow of electrons. I have. In this element structure, a storage layer having a high electron concentration is formed at the interface between the insulating film 14 and the N ⁻ -type cathode layer 10 in a conductive state.
There is no problem that the resistance between the electrodes 15 becomes a problem unlike BD.

However, in this device structure, since the extension of the depletion layer is smaller than that of the junction barrier control SBD, the electrode 1
It was necessary to further narrow the interval between the electrodes 5 to increase the potential between the electrodes 15. From the viewpoint of the manufacturing process, the electrode 15
There is a minimum value not only in the distance between the electrodes 15 but also in the width of the electrodes 15.
Occupies an increased area, and eventually increases the on-resistance.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has realized an electrostatic induction transistor having both a high turn-off gain and a low on-resistance, and a low on-resistance with a reduced leakage current. It is an object to provide a Schottky diode.

[0016]

In order to achieve the above object, a power semiconductor device according to the present invention (claim 1) comprises:
A first conductivity type high resistance semiconductor layer, a second conductivity type low resistance semiconductor layer formed on the first main surface at a predetermined distance, and the second conductivity type low resistance semiconductor layer on the first main surface A first first conductivity type low resistance semiconductor layer formed in a region sandwiched between
A second first-conductivity-type low-resistance semiconductor layer formed on a second main surface of the first-conductivity-type high-resistance semiconductor layer;
A first main electrode formed on the conductive low-resistance semiconductor layer;
A second main electrode formed on the first low resistance semiconductor layer of the first conductivity type; and a gate electrode formed on the low resistance semiconductor layer of the second conductivity type. The auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers of approximately 5 × 10 ¹² cm ⁻² or less are alternately adjacent to each other is at least the second conductive type of the first conductive type high-resistance semiconductor layer. Formed in the region between the low-resistance semiconductor layers,
The second conductive type semiconductor layer in the auxiliary region is connected to the second conductive type low resistance semiconductor layer.

The effect of the auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers are alternately adjacent to each other is described in, for example, T.W. Fujihira, Jpn. J.
Appl. Phys. Vol. 36 (199
7) pp. 6254-6262.
That is, the carrier integration amount of the first conductive type semiconductor layer and the second conductive type semiconductor layer in the auxiliary region in the repeating direction is approximately 5 × 1.
If they are designed to be almost the same below 0 ¹² cm ⁻² , these layers will be completely depleted when a reverse voltage is applied between these layers.

According to this principle, for example, the concentration of the first conductivity type semiconductor layer is set to one of the concentration of the first conductivity type high resistance semiconductor layer.
Even if it is set to 00 times, the width is narrowed and the carrier integration amount is 5
If the adjustment is performed so as to be not more than × 10 ¹² cm ^−2, no breakdown occurs in the auxiliary region. Therefore, if such an auxiliary region is formed in a region sandwiched between the second conductive type low-resistance semiconductor layers, the resistance of this portion can be significantly reduced.

The auxiliary region has a property that the breakdown voltage increases in proportion to the thickness (the size of the auxiliary region in the thickness direction of the semiconductor element) without changing the concentration and width.
The on-resistance is linearly proportional to the breakdown voltage.

On the other hand, when there is no auxiliary region, the breakdown voltage does not increase unless the thickness is increased while reducing the concentration of the first conductivity type high-resistance semiconductor layer. Therefore, the on-resistance is significantly increased in proportion to the square of the breakdown voltage. To increase. Therefore, by extending the auxiliary region to the portion of the first conductivity type high resistance semiconductor layer,
The resistance at this portion can be significantly reduced.

The second conductive type semiconductor layer in the auxiliary region is connected to the second conductive type low-resistance semiconductor layer and is set at substantially the same potential as the gate electrode, and the first conductive type semiconductor layer in the auxiliary region is the first conductive type semiconductor layer. The first main electrode is connected to the first first conductivity type semiconductor layer and is set at substantially the same potential as the second main electrode. Therefore, when a negative voltage is applied to the gate electrode with respect to the second main electrode, the depletion layer spreads quickly in the narrow first conductive type semiconductor layer of the auxiliary region, and a high turn-off gain can be obtained. it can.

Further, according to the present invention (claim 2),
The semiconductor element includes a first conductive type high resistance semiconductor layer and a first conductive type high resistance semiconductor layer.
The gate formed at a predetermined distance from the main surface of the
Between the gate electrode and the gate electrode on the first main surface.
A first first conductivity type low resistance semiconductor layer formed in the region;
The first conductive type high resistance semiconductor layer is formed on a second main surface.
The second first conductivity type low resistance semiconductor layer, and the second first conductivity type low resistance semiconductor layer.
A first main electrode formed on the conductive low-resistance semiconductor layer;
A first conductive type low resistance semiconductor layer formed on the first conductive type low resistance semiconductor layer;
2 main electrodes, and the amount of carrier integration in the repeating direction
Is approximately 5 × 10 ¹²cm^-2The following first conductive type semiconductor layer
And an auxiliary region in which the second conductive type semiconductor layers are alternately adjacent to each other
At least the gate of the first conductive type high resistance semiconductor layer
Characterized in that it is formed in the area between the electrodes
You.

In the power semiconductor device according to the present invention (claim 2), the current control type gate in the above invention (claim 1) can be replaced with a voltage control type gate,
It becomes possible to drive with lower power.

In this device structure, when a negative voltage is applied to the gate electrode with respect to the second main electrode, depletion occurs from the interface between the insulating film and the first conductive type high resistance semiconductor layer to the first conductive type high resistance semiconductor layer. The layer extends to increase the potential immediately below the first first conductivity type low-resistance semiconductor layer to prevent electron injection. At this time, the second conductivity type semiconductor layer in the auxiliary region is fixed at the potential of the depletion layer, and as the potential of the first main electrode increases, the second conductivity type semiconductor layer in which the width of the auxiliary region becomes narrower is increased. The depletion layer spreads quickly, and a high turn-off gain can be obtained. In a voltage-controlled gate, the second
Since the width of the depletion layer extending when a negative voltage is applied to the main electrode is small, the effect of improving the turn-off gain by introducing the auxiliary region is further increased.

Further, a power semiconductor device according to the present invention (claim 3) comprises a first conductivity type high resistance semiconductor layer and a first conductive type high resistance semiconductor layer.
A second-conductivity-type low-resistance semiconductor layer formed at a predetermined distance from the main surface of the first conductive type; a first-conductivity-type low-resistance semiconductor layer formed on a second main surface of the first-conductivity-type high-resistance semiconductor layer; A first main electrode formed on the first conductive type low-resistance semiconductor layer and an ohmic contact with the second conductive type low-resistance semiconductor layer formed on the first main surface; The region between the semiconductor layers is composed of the second main electrode in Schottky contact, and the carrier integration amount in the repetition direction is approximately 5 × 10
^An auxiliary region in which the first conductivity type semiconductor layers and the second conductivity type semiconductor layers of ¹² cm ⁻² or less are alternately adjacent to each other is formed in at least the second conductivity type low resistance semiconductor layer of the first conductivity type high resistance semiconductor layer. The second conductive type semiconductor layer of the auxiliary region is formed in a region sandwiched therebetween, and is connected to the second conductive type low-resistance semiconductor layer.

In the power semiconductor device according to the present invention (claim 3), similarly to the above invention (claim 1), the auxiliary region is formed in a region sandwiched between the second conductive type low resistance semiconductor layers. The resistance of this portion can be significantly reduced. The second conductive type semiconductor layer in the auxiliary region is connected to the second conductive type low-resistance semiconductor layer and is set at substantially the same potential as the second main electrode, and the first conductive type semiconductor layer in the auxiliary region is the second conductive type semiconductor layer. The first main electrode is connected to the one-conductivity-type high-resistance semiconductor layer, and is set at substantially the same potential as the first main electrode, and a barrier is provided between the second main electrode and the Schottky barrier. As the potential of the first main electrode increases, a reverse bias is applied between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in the auxiliary region,
The depletion layer quickly spreads in the narrow first conductivity type semiconductor layer, and the leakage current can be reduced.

Further, the power semiconductor device according to the present invention (claim 4) comprises a first conductive type high resistance semiconductor layer and a first conductive type high resistance semiconductor layer.
An electrode formed at a predetermined distance from the main surface of the first conductive type via an insulating film; a first conductive type low-resistance semiconductor layer formed on a second main surface of the first conductive type high-resistance semiconductor layer; A first main electrode formed on a one-conductivity-type low-resistance semiconductor layer;
And a second main electrode formed in ohmic contact with the electrode and interposed between the electrodes and having a Schottky contact with the second main electrode, and the carrier integration amount in the repetitive direction is approximately 5 ×
An auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers of 10 ¹² cm ⁻² or less are alternately adjacent to each other is formed in at least a region of the first conductive type high resistance semiconductor layer sandwiched between the gate electrodes. It is characterized by being formed.

In the power semiconductor device according to the present invention (claim 4), when the potential of the first main electrode is increased, the first conductive type high resistance semiconductor layer is moved from the interface between the insulating film and the first conductive type high resistance semiconductor layer. A depletion layer extends to the semiconductor layer, increasing the potential between the electrodes and blocking the flow of electrons. At this time, the second
The conductivity type semiconductor layer is fixed to the potential of the depletion layer. As the potential of the first main electrode increases, the depletion layer quickly spreads in the first conductivity type semiconductor layer having a narrow auxiliary region, and the leakage current increases. Can be reduced. In the MOS barrier control SBD, since the extension of the depletion layer is small, the effect of reducing the leak current by introducing the auxiliary region is further increased.

In the above invention (claim 1 or 3), the width of the first conductivity type semiconductor layer constituting a portion of the auxiliary region sandwiched between the second conductivity type low resistance semiconductor layers is It is desirable to set the width to be smaller than the width of the first conductivity type semiconductor layer constituting the portion formed deeper than it (sixth invention).

In the power semiconductor device having such a configuration, since the width of the first conductive type semiconductor layer in the auxiliary region is narrowed, the resistance of the portion sandwiched between the second conductive type low resistance semiconductor layers can be further reduced, and furthermore, the non-conductive area can be reduced. Depletion easily occurs in the conductive state, and the effect of improving the turn-off gain (or reducing the leak current) can be realized at the same time.

As the width of the first conductive type semiconductor layer in the auxiliary region is reduced, the junction is formed by the first conductive type semiconductor layer and the second conductive type semiconductor layer forming the auxiliary region. The depletion layer extends in the first conductivity type semiconductor layer, and the width of the first conductivity type carriers substantially decreases, which causes a problem that the on-resistance increases.

However, in a conductive state where a positive voltage is applied to the gate electrode with respect to the second main electrode (or a positive voltage is applied to the second main electrode with respect to the first main electrode). ,
Since a forward bias is applied between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer forming the auxiliary region, the depletion layer extending in the first conductivity type semiconductor layer disappears, and a sufficiently small ON-state is formed. Resistance can be realized.

The width of the first conductive type semiconductor layer in the auxiliary region in the portion formed deeper than the second conductive type low resistance semiconductor layer is set to such a width that the depletion layer due to the built-in potential does not matter. In addition, a problem arises that the on-resistance increases even if the second conductive type semiconductor layer in the auxiliary region is not at the same potential as the gate electrode (or the second main electrode) apart from the second conductive type low resistance semiconductor layer. Absent.

In the above invention (claim 2 or 4), the width of the first conductive type semiconductor layer constituting the gate electrode or the portion sandwiched between the electrodes in the auxiliary region is set to be larger than that. It is desirable to set the width to be smaller than the width of the first conductivity type semiconductor layer constituting the deeply formed portion (seventh invention).

In the power semiconductor device having such a configuration, the width of the first conductive type semiconductor layer in the auxiliary region is reduced, so that the semiconductor layer is easily depleted in a non-conductive state, and the turn-off gain is improved (or the leak current is reduced). . In this element structure,
In a conductive state where a positive voltage is applied to the gate electrode with respect to the second main electrode (or a positive voltage is applied to the second main electrode with respect to the first main electrode), the insulating film and the semiconductor , A high-concentration first-conductivity-type carrier layer is formed at the interface, so that a sufficiently small on-resistance can be realized.

Unlike the above invention (sixth invention), in this element structure, no forward bias is applied between the first conductive semiconductor layer and the second conductive semiconductor layer in the auxiliary region. But,
A high-concentration first-conductivity-type storage layer is formed at the interface between the first-conductivity-type semiconductor layer and the insulating film in a portion of the auxiliary region formed shallower than the gate electrode (or electrode). The first part of the auxiliary area of the part formed deeper than
If the width of the conductive semiconductor layer is set to such a width that the depletion layer due to the built-in potential does not cause a problem, the problem of an increase in on-resistance does not occur.

In the above invention (claims 1 and 2 and the sixth and seventh inventions), when the potential of the gate electrode is equal to the potential of the second main electrode, the potential of the auxiliary region At least a portion of the one conductivity type semiconductor layer is depleted,
The first conductive type semiconductor layer of the auxiliary region is configured to block the flow of the first conductive type carrier from the first first conductive type low resistance semiconductor layer to the second first conductive type low resistance semiconductor layer. (The eighth invention).

In the power semiconductor device having such a configuration, at least a part of the first conductive type semiconductor layer in the auxiliary region is depleted by the built-in potential, so that the second conductive type low resistance semiconductor layer (or insulating film) is depleted from the depletion layer. Even if is not extended, electron injection from the first first conductivity type low resistance semiconductor layer is prevented, and normally-off characteristics are realized.

In the above inventions (claims 3 and 4, and the sixth and seventh inventions), when the potential of the first main electrode is higher than the potential of the second main electrode, the auxiliary At least a portion of the first conductivity type semiconductor layer in the region is depleted to prevent the flow of the first conductivity type carrier from the second first conductivity type low resistance semiconductor layer to the second main electrode, It is desirable to set the concentration and width of the first conductivity type semiconductor layer in the auxiliary region (ninth invention).

In the power semiconductor device having such a configuration, at least a portion of the first conductive type semiconductor layer in the auxiliary region is depleted by the built-in potential, so that the second conductive type low resistance semiconductor layer (or insulating film) is depleted. Even if is not extended, the flow of the first conductivity type carrier from the second first conductivity type low resistance semiconductor layer to the second main electrode is blocked, and the leak current can be sufficiently reduced.

In each of the above aspects of the present invention, the auxiliary region is formed on the entire first main surface, and when forming a junction termination structure at an end of the power semiconductor element structure,
It is preferable that the third first conductivity type low-resistance semiconductor layer for suppressing the extension of the depletion layer is formed on the surface of the auxiliary region (tenth invention). A high withstand voltage can be obtained even if it is formed over the range. Therefore, an auxiliary region is formed on the entire surface of the wafer without patterning by the epitaxial growth method of the present invention (claim 5) or another process described below, and then the element structure is easily formed by a normal method. Each element structure of the present invention can be realized.

Further, in the method of forming a semiconductor layer according to the present invention (claim 5), the first conductive type high resistance semiconductor layer is polished at a predetermined angle in advance, and the first conductive type high resistance semiconductor layer is polished by the polishing. On the terrace formed on the first main surface of the semiconductor layer, the carrier integration amount in the repeating direction is approximately 5 × 10 ¹²
In forming an auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers each having a size of cm ⁻² or less are alternately adjacent to each other by epitaxial growth, a single step flow is performed from the step formed on the first main surface. As the crystal grows,
The second conductivity type impurity is added until the single crystal grows to just half of the terrace, and then the first conductivity type impurity is added until the single crystal grows on the entire terrace, and this cycle is repeated. An auxiliary area is formed.

In the method of forming a semiconductor layer having such a structure, a terrace having a width corresponding to the polishing angle is formed, and
Is the width of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in the auxiliary region, so that an auxiliary region having a width that is too small by ordinary patterning can be realized by selecting an angle. According to this method, an auxiliary region having a narrow first conductive type semiconductor layer in a portion sandwiched between gate electrodes (or electrodes) formed via a second conductive type low resistance semiconductor layer or an insulating film is formed. This is a particularly suitable method.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is N-type,
The case where the second conductivity type is P-type is shown.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Of the junction type static induction transistor (SI
It is a perspective view including a sectional view showing an element structure of T). Hereinafter, in the first to fourth embodiments corresponding to FIGS.
Parts corresponding to those of the conventional junction type SIT shown in FIG. 20 are denoted by the same reference numerals, and detailed description is omitted.

In the device structure of the junction type SIT of this embodiment, an auxiliary region 16 in which P-type layers and N-type layers are alternately arranged is formed in a region sandwiched between the P ⁺ -type gate layers 4. The P-type layer of the auxiliary region 16 is connected to the P ⁺ -type gate layer 4. The carrier integral calculated from the concentration × width of the P-type layer and the N-type layer in the auxiliary region is approximately 5 × 10 ¹² cm.
The densities and widths of the respective layers are set so that they substantially match at ^-2 or less. For example, if the width is 5 μm, the density is 3
× 10 ¹⁵ cm ⁻³ , if the width is 1 μm, the concentration is 2 × 1
0 ¹⁶ cm ^-3 can be selected.

According to the present embodiment, the concentration of the N-type layer of the auxiliary area 16 N ^- since it set higher than the concentration of type base layer 2, a conventional junction type SIT P ⁺ -type gate layer a was the problem of 4 makes it possible to significantly reduce the resistance component in the region sandwiched between the layers. The P-type layer of the auxiliary region 16 is connected to the P ⁺ -type gate layer 4 and is set at substantially the same potential as the gate electrode 7, and the N-type layer of the auxiliary region 16 is of the N ⁺ -type source layer 3.
And is set at substantially the same potential as the source electrode 6.

Therefore, when a negative voltage is applied to the gate electrode 7 with respect to the source electrode 6, the N
The depletion layer quickly spreads in the mold layer, and a high turn-off gain can be obtained. Further, the width of the N-type layer in the auxiliary region 16 is reduced to about 0.05 μm, and the concentration is set to 5 × 10
By selecting about ¹⁷ cm ⁻³ , the N
The N-type layer in the auxiliary region 16 is covered with a depletion layer by the built-in potential of the PN junction composed of the type layer and the P-type layer.

Thus, even if the gate electrode 7 and the source electrode 6 are at the same potential, electron injection from the N ⁺ -type source layer 3 does not occur, and normally-off can be realized.
As a result, when the system is stopped, the current can be kept in a cut-off state, and safety can be improved. Even in this case, if a positive voltage is applied to the gate electrode 7 with respect to the source electrode 6, the PN junction formed of the N-type layer and the P-type layer in the auxiliary region 16 is forward-biased, and the built-in The depletion layer due to the potential disappears, and a sufficiently low on-resistance can be realized.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
Of the junction type static induction transistor (SI
It is a perspective view including a sectional view showing an element structure of T). The element structure of junction type SIT of this embodiment, the auxiliary region 16 are formed deeper than the P ⁺ -type gate layer 4, N of the auxiliary area 16 of the portion sandwiched between the P ⁺ -type gate layer 4
The width of the mold layer is set to be smaller than the width of the N-type layer in the auxiliary region 17 that forms a portion formed deeper than the mold layer.

According to the present embodiment, since the width of the N-type layer in the auxiliary region 16 is reduced, the resistance of the portion sandwiched between the P ⁺ -type gate layers 4 can be further reduced, and depletion easily occurs in a non-conductive state. The effect of improving the turn-off gain can be realized at the same time. Also in this case, the width of the N-type layer in the auxiliary region 16 can be reduced to about 0.05 μm to be normally off.

The width of the N-type layer of the auxiliary region 17 constituting the portion formed deeper than the P ⁺ -type gate layer 4 is the same as the width of the N-type layer of the auxiliary region 16 constituting the portion sandwiched between the P ⁺ -type gate layers 4. Although it may be set to be the same as the width of the layer, it is set to be large in this embodiment. The P-type layer or the N-type layer of the auxiliary region 17 constituting the portion formed deeper than the P ⁺ -type gate layer 4 is formed by the P ⁺ -type gate layer 4 or the N ⁺ -type source layer 3 depending on the resistance of each layer. Does not become equipotential. In such a case, even if a positive voltage is applied to the gate electrode 7 with respect to the source electrode 6, the depletion layer due to the built-in potential spreading inside the N-type layer below the auxiliary region 17 is sufficiently eliminated. Can not.

[0053] To avoid such a situation, the width of the N-type layer of the auxiliary area 17 constituting the deeper portion than P ⁺ -type gate layer 4 in this embodiment, the P ⁺ -type gate layer 4
Is set to be larger than the width of the N-type layer of the auxiliary region 16 constituting the portion sandwiched between the two. This element structure is also suitable for employing a manufacturing process in which selective doping of P-type impurities and N-type impurities by epitaxial growth and ion implantation is repeated.

That is, in the epitaxial growth, the semiconductor substrate needs to be heated to a high temperature. At this time, the P-type impurity and the N-type impurity in the auxiliary region already formed in the base are diffused and spread, and their widths are changed. I will. In particular, if the width of the N-type impurity in the auxiliary region is set to be small, in the worst case, the N-type layer may disappear due to the diffusion of the P-type impurity. Therefore, if the width of the N-type layer of the auxiliary region 17 formed in a deep portion of the semiconductor substrate which is first epitaxially grown is set to be large, N
Even if the width of the mold layer fluctuates, the auxiliary region 17 is stable.
Can be formed.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
Of the junction type static induction transistor (SI
It is a perspective view including a sectional view showing an element structure of T). In the device structure of the junction type SIT according to the present embodiment, the auxiliary region 17 reaches the N ⁺ type drain layer 1.

According to this embodiment, the auxiliary region 17 has the property that the breakdown voltage increases in proportion to the thickness (the size of the auxiliary region in the thickness direction of the semiconductor element) without changing the concentration and width. Therefore, when there is no auxiliary area 17 or when the auxiliary area 17
Can be reduced as compared with the case where only a part of the N ⁻ type base layer 2 is formed.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
Of the junction type static induction transistor (SI
It is a perspective view including a sectional view showing an element structure of T). In the device structure of the junction type SIT of the present embodiment, the P ⁻ type layer 18 is formed near the surface of the auxiliary region 16.

According to the present embodiment, since the N-type layer of the auxiliary region 16 and the N ⁺ -type source layer 3 are separated by the P ⁻ -type layer 18, electrons flow into the N-type layer of the auxiliary region 16. It cannot show normally-off characteristics. Even in such a case, if a positive voltage is applied to the gate electrode 7 with respect to the source electrode 6, the P ⁺ composed of the N ⁺ type source layer 3 and the P ⁻
The N junction is forward-biased, and electrons are injected from the N ⁺ type source layer 3 through the P ⁻ type layer 18 into the N type layer of the auxiliary region 16. However, if the concentration of the P ⁻ -type layer 18 is excessively increased, the resistance in this portion increases, which adversely affects the on-resistance. The width of the N-type layer of the auxiliary region 16 is, for example, 1 μm
It is desirable to set the concentration to a range of about .mu.m to sub-.mu.m, which is possible in a normal manufacturing process, and to the minimum concentration required for normally-off.

(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
MOS type static induction transistor (S
FIG. 2 is a perspective view including a cross-sectional view showing an element structure of (IT). Hereinafter, in the fifth to eighth embodiments corresponding to FIGS.
Portions corresponding to the conventional MOS type SIT shown in FIG. 21 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the device structure of the MOS type SIT according to the embodiment, an auxiliary region 16 in which P-type layers and N-type layers are alternately arranged is formed in a region sandwiched between the gate electrodes 7. The auxiliary region 16 is shallower than the bottom of the gate electrode 7, and an N ⁻ -type layer 19 is formed between the auxiliary region 16 and the N ⁺ -type source layer 3. Also in this embodiment, the concentrations and widths of the P-type layer and the N-type layer in the auxiliary region 16 can be selected as in the first embodiment.

According to the present embodiment, the current control type gate in the element structure of the first to fourth embodiments can be replaced with a voltage control type gate, and the device can be driven with lower power. Becomes In this device structure, when a negative voltage is applied to the gate electrode 7 with respect to the source electrode 6, a depletion layer extends from the interface between the gate insulating film 8 and the N ⁻ type layer 19 to the N ⁻ type layer 19, and the N ⁺ type source The potential immediately below the layer 3 is increased to prevent electron injection. At this time, P
The depletion layer is fixed to the potential of the depletion layer. As the potential of the drain electrode 5 increases, the depletion layer spreads quickly in the N-type layer having a narrow auxiliary region, and a high turn-off gain can be obtained. In the voltage-controlled gate, the width of the depletion layer extending when a negative voltage is applied to the gate electrode 7 with respect to the source electrode 6 is small, so that the effect of improving the turn-off gain by introducing the auxiliary region 16 is further increased.

(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
MOS type static induction transistor (S
FIG. 2 is a perspective view including a cross-sectional view showing an element structure of (IT). In the element structure of the MOS type SIT of the present embodiment, the auxiliary region 1
6 is formed deeper than the gate electrode 7, and the width of the N-type layer of the auxiliary region 16 forming the portion sandwiched by the gate electrode 7 is set to the width of the auxiliary region 17 forming the portion formed deeper than that. The width is set smaller than the width of the N-type layer.

According to the present embodiment, since the width of the N-type layer in the auxiliary region 16 is reduced, the resistance of the portion sandwiched between the gate electrodes 7 can be further reduced, and the depletion is easily caused in a non-conductive state. The effect of improvement can be realized at the same time. Also in this case, the width of the N-type layer in the auxiliary region 16 can be reduced to about 0.05 μm to be normally off. The width of the N-type layer of the auxiliary region 17 constituting the portion formed deeper than the gate electrode 7 is set to be the same as the width of the N-type layer of the auxiliary region 16 constituting the portion sandwiched between the gate electrodes 7. However, in this embodiment, it is set large. Unlike the second embodiment, in this element structure, no forward bias is applied between the N-type layer and the P-type layer in the auxiliary regions 16 and 17. However, the auxiliary region 16 and the gate insulating film 8
Since an electron accumulation layer with a high concentration is formed at the interface, if the width of the N-type layer in the auxiliary region 17 is set to such a width that the depletion layer due to the built-in potential does not cause a problem, the on-resistance increases. Does not occur.

(Seventh Embodiment) FIG. 7 shows a seventh embodiment of the present invention.
MOS type static induction transistor (S
FIG. 2 is a perspective view including a cross-sectional view showing an element structure of (IT). In the element structure of the MOS type SIT of the present embodiment, the auxiliary region 1
7 has reached the N ⁺ type drain layer 1.

According to the present embodiment, the auxiliary region 17 has the property that the breakdown voltage increases in proportion to the thickness (the size of the auxiliary region in the thickness direction of the semiconductor element) without changing the concentration and width. Therefore, when there is no auxiliary area 17 or when the auxiliary area 17
Can be reduced as compared with the case where only a part of the N ⁻ type base layer 2 is formed.

(Eighth Embodiment) FIG. 8 shows an eighth embodiment of the present invention.
MOS type static induction transistor (S
FIG. 2 is a perspective view including a cross-sectional view showing an element structure of (IT). In the element structure of the MOS type SIT of the present embodiment, the auxiliary region 1
6, a P-type layer 20 connected to the source electrode 6 is formed near the surface.

According to the present embodiment, since the N-type layer of the auxiliary region 16 and the N ⁺ -type source layer 3 are separated by the P-type layer 20, electrons flow into the N-type layer of the auxiliary region 16. And normally-off characteristics. Even in such a case, if a positive voltage is applied to the gate electrode 7 with respect to the source electrode 6, an inversion layer is formed at the interface between the gate insulating film 8 and the P-type layer 20, and electrons are transferred to the N ⁺ -type source layer. 3 is injected into the N-type layer of the auxiliary region 16 through the inversion layer. Since this element structure is the same as that of a normal MOS-type FET with an auxiliary region added, the concentration of the P-type layer 20 must be selected so that the threshold value of the inversion layer falls within an appropriate range.

(Ninth Embodiment) FIG. 9 shows a ninth embodiment of the present invention.
FIG. 4 is a perspective view including a cross-sectional view showing an element structure of a junction barrier control Schottky diode (SBD) according to the embodiment. Hereinafter, in the ninth to thirteenth embodiments corresponding to FIGS. 9 to 13, the conventional junction barrier control SB shown in FIG.
Portions corresponding to D are denoted by the same symbols and detailed description is omitted.

In the element structure of the junction barrier control SBD of the present embodiment, an auxiliary region 16 in which P-type layers and N-type layers are alternately arranged is formed in a region sandwiched between P ⁺ -type layers 11. The P-type layer of the auxiliary region 16 is connected to the P ⁺ -type layer 11. Also in this embodiment, the P-type layer of the auxiliary region 16;
The concentration and width of the N-type layer can be selected in the same manner as in the first embodiment.

According to the present embodiment, the auxiliary region 16 is formed in the region sandwiched between the P-type layers 11 as in the first embodiment, so that the resistance of this portion can be significantly reduced. . The P-type layer of the auxiliary region 16 is a P ⁺ -type layer 1
1 and is set at substantially the same potential as the anode electrode 13, and the N-type layer of the auxiliary region 16 is the N ⁻ -type cathode layer 1.
It is connected to 0 and is set at substantially the same potential as the cathode electrode 12, and the anode electrode 13 is provided with a barrier by a Schottky barrier. As the potential of the cathode electrode 12 increases, a reverse bias is applied between the N-type layer and the P-type layer in the auxiliary region 16, and the depletion layer quickly spreads in the narrow N-type layer, thereby reducing leakage current. be able to. Furthermore,
By reducing the width of the N-type layer of the auxiliary region 16 to about 0.05 μm and selecting the concentration to about 5 × 10 ¹⁷ cm ⁻³ , the PN junction of the N-type layer and the P-type layer of the auxiliary region 16 is formed. The N-type layer of the auxiliary region 16 is covered with a depletion layer by the built-in potential. In this way, even if a metal having a low barrier height is used for the anode electrode 13, a barrier for preventing the flow of electrons is generated, and the leak current can be reduced. Also in this case, if a positive voltage is applied to the anode electrode 13 with respect to the cathode electrode 12, the PN junction of the auxiliary region 16 composed of the N-type layer and the P-type layer is forward-biased,
The depletion layer due to the built-in potential covering the mold layer disappears, and a sufficiently low on-resistance can be realized.

(Tenth Embodiment) FIG. 10 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode (SBD) according to a tenth embodiment of the present invention. The device structure of the junction barrier control SBD of the present embodiment, the auxiliary region 16 are formed deeper than the P ⁺ -type layer 11, N-type layer of the auxiliary area 16 of the portion sandwiched between the P ⁺ -type layer 11 Is set to be smaller than the width of the N-type layer of the auxiliary region 17 forming a portion formed deeper than that.

According to the present embodiment, since the width of the N-type layer in the auxiliary region 16 is reduced, the resistance of the portion sandwiched between the P ⁺ -type layers 11 can be further reduced, and depletion easily occurs in a non-conductive state. The effect of reducing the current can also be realized at the same time. Also in this case, the width of the N-type layer in the auxiliary region 16 can be reduced to about 0.05 μm to form a barrier with a built-in potential. The width of the N-type layer of the auxiliary area 17 constituting the deeper portion than P ⁺ -type layer 11 is the same as the width of the N-type layer of the auxiliary area 16 of the portion sandwiched between the P ⁺ -type layer 11 May be set, but in this embodiment, it is set large. The reason is the same as that described in the second embodiment.

(Eleventh Embodiment) FIG. 11 is a sectional view showing an element structure of a junction barrier control Schottky diode (SBD) according to an eleventh embodiment of the present invention.
In the element structure of the junction barrier control SBD according to the present embodiment, the auxiliary region 17 has reached the N ⁺ type cathode layer 9.

According to this embodiment, the auxiliary region 17 has the property that the breakdown voltage increases in proportion to the thickness (the size of the auxiliary region in the thickness direction of the semiconductor element) without changing the concentration and the width. Therefore, when there is no auxiliary area 17 or when the auxiliary area 17
Can be reduced as compared with the case where is formed only halfway in the N ⁻ -type cathode layer 10.

(Twelfth Embodiment) FIG. 12 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode (SBD) according to a twelfth embodiment of the present invention. In the device structure of the junction barrier control SBD of the present embodiment, the P ⁻ type layer 18 is formed near the surface of the auxiliary region 16.

According to the present embodiment, the N-type
Layer and anode electrode 13 in addition to the Schottky barrier
P⁻Since a barrier is provided by the mold layer 18, the electron
The flow is blocked and the leak current can be reduced. This
Even in such a case, the cathode electrode 1 is connected to the anode electrode 13.
When a positive voltage is applied to the second region 2, the N-type
Layer and P⁻The PN junction composed of the mold layer 18 is forward biased.
And electrons are transferred from the N-type layer to P ⁻Forward via through mold layer 18
Across the Schottky barrier height
Flows out to pole 13. However, this P⁻The concentration of the mold layer 18
If it is too high, the resistance in this area will increase, so
Affects resistance. Must be within practical leakage current
It is desirable to set the minimum concentration.

(Thirteenth Embodiment) FIG. 13 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode (SBD) according to a thirteenth embodiment of the present invention. In the device structure of the junction barrier control SBD of the present embodiment, the N of the auxiliary region 16 is located near the surface of the auxiliary region 16.
An N ^- type layer 19 having a lower concentration than the mold layer is formed.

According to the present embodiment, the depletion layer from the P ⁺ -type layer 11 extends more widely, the potential in the N ⁻ -type layer 19 increases, and the flow of electrons is blocked, so that the leak current can be reduced. .

(Fourteenth Embodiment) FIG. 14 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode (SBD) according to a fourteenth embodiment of the present invention. Hereinafter, a fourteenth embodiment corresponding to FIGS.
In the seventeenth embodiment, the conventional MOS shown in FIG.
Parts corresponding to the barrier control SBD are denoted by the same reference numerals, and detailed description is omitted.

In the element structure of the MOS barrier control SBD of the present embodiment, an auxiliary region 16 in which P-type layers and N-type layers are alternately arranged is formed in a region sandwiched between the electrodes 15. The auxiliary region 16 is shallower than the bottom of the electrode 15, and an N ⁻ type layer 19 is formed between the auxiliary region 16 and the anode electrode 13.
Also in this embodiment, the concentrations and widths of the P-type layer and the N-type layer in the auxiliary region 16 can be selected as in the first embodiment.

According to this embodiment, the cathode electrode 12
When the potential increases, the insulating film 14 and N ⁻Interface with mold layer 19
To N⁻The depletion layer extends to the mold layer 19 and the potential between the electrodes 15 is increased.
Raise the char to stop the flow of electrons. At this time,
The P-type layer in the region 16 is fixed to the potential of the depletion layer.
And as the potential of the cathode electrode 12 increases,
A depletion layer quickly spreads in the narrow N-type region 16.
As a result, leakage current can be reduced. MOS barrier
In the control SBD, the extension of the depletion layer is small.
The effect of reducing leakage current by introducing
Become.

(Fifteenth Embodiment) FIG. 15 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode (SBD) according to a fifteenth embodiment of the present invention. In the element structure of the MOS barrier control SBD of the present embodiment, the auxiliary region 16 is formed deeper than the electrode 15, and the width of the N-type layer of the auxiliary region 16 forming a portion sandwiched between the electrodes 15 is set to be smaller than that. The width is set to be smaller than the width of the N-type layer of the auxiliary region 17 forming the deeply formed portion.

According to this embodiment, since the width of the N-type layer in the auxiliary region 16 is reduced, the resistance of the portion sandwiched between the electrodes 15 can be further reduced. The effect described above can also be realized at the same time. Also in this case, the width of the N-type layer in the auxiliary region 16 is set to 0.0
A barrier with a built-in potential can be formed by shrinking to about 5 μm. The width of the N-type layer of the auxiliary region 17 forming a portion formed deeper than the electrode 15 may be set to be the same as the width of the N-type layer of the auxiliary region 16 forming a portion sandwiched between the electrodes 15. However, in this embodiment, it is set large. The reason is the same as that described in the sixth embodiment.

(Sixteenth Embodiment) FIG. 16 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode (SBD) according to a sixteenth embodiment of the present invention. In the element structure of the MOS barrier control SBD of the present embodiment, the auxiliary region 17 has reached the N ⁺ type cathode layer 9.

According to the present embodiment, the auxiliary region 17 has the property that the breakdown voltage increases in proportion to the thickness (the size of the auxiliary region in the thickness direction of the semiconductor element) without changing the concentration and width. Therefore, when there is no auxiliary area 17 or when the auxiliary area 17
Can be reduced as compared with the case where is formed only halfway in the N ⁻ -type cathode layer 10.

(Seventeenth Embodiment) FIG. 17 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode (SBD) according to a seventeenth embodiment of the present invention. The device structure of the MOS barrier control SBD of the present embodiment, P near the contact surface of the anode electrode 13 ^-
A mold layer 18 is formed.

According to the present embodiment, since the N-type layer of the auxiliary region 16 and the anode electrode 13 are provided with a barrier by the P ⁻ -type layer 18 in addition to the Schottky barrier, the flow of electrons is prevented and the leakage is prevented. The current can be reduced. Even in such a case, the cathode electrode 1 is connected to the anode electrode 13.
When a positive voltage is applied to 2, the N-type layer of the auxiliary region 16 and the PN composed of the N ⁻ -type layer 19 and the P ⁻ -type layer 18 thereon are formed.
The junction is forward biased and electrons flow from the N-type layer to the N ^- type layer 1
9. It flows through the P ⁻ -type layer 18 to the anode electrode 13 over the forward-biased Schottky barrier height. However, if the concentration of the P ⁻ -type layer 18 is excessively increased, the resistance in this portion increases, which adversely affects the on-resistance. It is desirable to set the concentration to the minimum necessary within a practical leak current.

(Eighteenth Embodiment) FIG. 18 and FIG.
It is a figure showing the manufacturing method of the power semiconductor device concerning an 18th embodiment of the present invention. In the power semiconductor device of the present embodiment, the crystal substrate (specifically, the N ⁻ type base layer 2,
^{The +} type drain layer 1, the N ⁻ type cathode layer 10, the N ⁺ type cathode layer 9 and the like are polished in advance with a predetermined off angle θ (FIG. 18A), so that an auxiliary surface is formed on the terrace formed on the crystal surface. In forming the region 16 (or 17) by epitaxial growth, when a single crystal is grown by a step flow from a step formed on the crystal surface, a P-type impurity is doped until the single crystal grows to just half of the terrace. N-type impurities are added until a single crystal grows on the entire terrace (FIG. 18A).
The auxiliary region 16 (or 17) is formed by repeating this cycle (FIG. 19B).

According to the present embodiment, a terrace having a width of 2 W (= d / tan θ, where d is the height of the step) corresponding to the off angle θ of polishing is formed, and a half thereof is formed in the auxiliary region 16.
(Or 17), the width W of the N-type layer and the P-type layer. Therefore, depending on the selection of the angle θ, the auxiliary region 16 (or 1) having a width W that is too small by ordinary patterning.
7) can be realized. This method uses the auxiliary area 1
This is a method particularly suitable for forming a narrow N-type layer 6. For example, in the case of a crystal having a step height of d = 1.5 °, by setting the off angle to θ = 0.086 ° or more, it is possible to realize W = 0.05 μm or less required for normally-off. .

(Nineteenth Embodiment) FIG. 20 and FIG.
It is a perspective view including a sectional view showing an element structure of a junction type static induction transistor (SIT) according to a nineteenth embodiment of the present invention. FIG. 20 is a diagram including the joint end portion in a plane parallel to the paper surface of FIG. 1, and FIG. 21 is a diagram including the joint end portion in a plane perpendicular to the paper surface of FIG. 1. The joint termination is
P ⁻ layer (RESURF) for depletion to reduce the electric field
A layer 21, an N ⁺ -type layer (channel stopper layer) 22 for stopping the depletion layer from spreading, and a passivation film 23 such as an oxide film or a SIPOS film (oxygen-doped polycrystalline silicon). The auxiliary region 16 is formed on the entire surface of the wafer, in which an element structure and a junction termination structure are formed. In this element structure, the N ⁻ type base layer 2 remains, but the auxiliary region 1
6 may be formed directly on the N ⁺ drain layer 1.

According to the present embodiment, a high breakdown voltage can be obtained even if the auxiliary region 16 is formed over the entire surface of the wafer.
Therefore, the auxiliary region 16 is formed on the entire surface of the wafer by the epitaxial growth method described in the eighteenth embodiment or another process, and then the element structure is formed by a normal method. Can be realized.

In addition, various modifications can be made without departing from the spirit of the present invention. For example, the auxiliary area 16,
17 is arranged so as to be repeated in a direction perpendicular to the paper surface of the sectional view of the basic element structure, but may be parallel or angled. Further, although the N-type layer and the P-type layer constituting the auxiliary regions 16 and 17 are plate-shaped, they may have other geometric shapes such as a square shape or a honeycomb shape. In addition, as for each basic element structure, an auxiliary region can be added to variously modified ones and used.

[0093]

As described in detail above, according to the present invention,
When the auxiliary region formed in the region between the gate regions is off, it exhibits the same effect as pinch-off, and when it is on, it works as a low-resistance conductive layer, so it has a large turn-off gain and small on-resistance. Can be realized. Also in a Schottky diode, low leakage current and low on-resistance can be simultaneously realized by using the auxiliary region.

[Brief description of the drawings]

FIG. 1 is a perspective view including a sectional view showing an element structure of a junction type static induction transistor according to a first embodiment of the present invention.

FIG. 2 is a perspective view including a sectional view showing an element structure of a junction type static induction transistor according to a second embodiment of the present invention.

FIG. 3 is a perspective view including a sectional view showing an element structure of a junction type static induction transistor according to a third embodiment of the present invention.

FIG. 4 is a perspective view including a sectional view showing an element structure of a junction type static induction transistor according to a fourth embodiment of the present invention.

FIG. 5 is a perspective view including a cross-sectional view showing an element structure of a MOS static induction transistor according to a fifth embodiment of the present invention.

FIG. 6 is a perspective view including a sectional view showing an element structure of a MOS type static induction transistor according to a sixth embodiment of the present invention.

FIG. 7 is a perspective view including a sectional view showing an element structure of a MOS-type electrostatic induction transistor according to a seventh embodiment of the present invention.

FIG. 8 is a perspective view including a sectional view showing an element structure of a MOS-type electrostatic induction transistor according to an eighth embodiment of the present invention.

FIG. 9 is a perspective view including a cross-sectional view illustrating an element structure of a junction barrier control Schottky diode according to a ninth embodiment of the present invention.

FIG. 10 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode according to a tenth embodiment of the present invention.

FIG. 11 is a perspective view including a cross-sectional view showing an element structure of a junction barrier control Schottky diode according to an eleventh embodiment of the present invention.

FIG. 12 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode according to a twelfth embodiment of the present invention.

FIG. 13 is a perspective view including a sectional view showing an element structure of a junction barrier control Schottky diode according to a thirteenth embodiment of the present invention.

FIG. 14 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode according to a fourteenth embodiment of the present invention.

FIG. 15 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode according to a fifteenth embodiment of the present invention.

FIG. 16 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode according to a sixteenth embodiment of the present invention.

FIG. 17 is a perspective view including a sectional view showing an element structure of a MOS barrier control Schottky diode according to a seventeenth embodiment of the present invention.

FIG. 18 is a view illustrating a method of manufacturing a power semiconductor device according to an eighteenth embodiment of the present invention.

FIG. 19 is a view showing a method of manufacturing a power semiconductor device according to an eighteenth embodiment of the present invention.

FIG. 20 is a perspective view including a sectional view showing an element structure of a power semiconductor element according to a nineteenth embodiment of the present invention.

FIG. 21 is a perspective view including a sectional view showing an element structure of a power semiconductor element according to a nineteenth embodiment of the present invention.

FIG. 22 is a perspective view including a sectional view showing an element structure of a conventional junction type static induction transistor.

FIG. 23 is a perspective view including a sectional view showing an element structure of a conventional MOS-type electrostatic induction transistor.

FIG. 24 is a perspective view including a sectional view showing an element structure of a conventional junction barrier control Schottky diode.

FIG. 25 is a perspective view including a sectional view showing an element structure of a conventional MOS barrier controlled Schottky diode.

[Explanation of symbols]

1 ... ^{N +} -type drain layer 2 ... N ^- type base layer 3 ... ^{N +} -type source layer 4 ... ^{P +} -type gate layer 5 ... drain electrode 6 ... source electrode 7 ... gate electrode 8 ... gate insulating film 9 ... ^{N +} -type Cathode layer 10 N ^- type cathode layer 11 P ⁺ type layer 12 Cathode electrode (ohmic electrode) 13 Anode electrode (Schottky electrode) 14 Insulating film 15 Electrode 16 Auxiliary area 17 Auxiliary area 18 P ^- -type layer 19 ... N ^- -type layer 20 ... P-type layer 21 ... P ^- -type layer (RESURF layer) 22 ... ^{N +} -type layer (channel stopper layer) 23 ... a passivation film

Claims (5)

[Claims] A first conductive type high-resistance semiconductor layer;
A second conductive type low-resistance semiconductor layer formed at a predetermined distance from the main surface of the second conductive type, and a first conductive type low-resistance semiconductor layer formed on the first main surface in a region interposed between the second conductive type low-resistance semiconductor layers. A one-conductivity-type low-resistance semiconductor layer, a second first-conductivity-type low-resistance semiconductor layer formed on a second main surface of the first-conductivity-type high-resistance semiconductor layer,
A first main electrode formed on the second first-conductivity-type low-resistance semiconductor layer, a second main electrode formed on the first first-conductivity-type low-resistance semiconductor layer, A first conductivity type semiconductor layer and a second conductivity type semiconductor layer comprising a gate electrode formed on a two conductivity type low resistance semiconductor layer and having a carrier integration amount of about 5 × 10 ¹² cm ⁻² or less in a repeating direction; An auxiliary region adjacent to the first conductive type high resistance semiconductor layer is formed at least in a region sandwiched between the second conductive type low resistance semiconductor layers, and the second conductive type semiconductor layer of the auxiliary region is A power semiconductor device connected to a two-conductivity low-resistance semiconductor layer. 2. A high-resistance semiconductor layer of a first conductivity type and a first
A gate electrode formed at a predetermined distance from the main surface via an insulating film, and a first first conductivity type low-resistance semiconductor layer formed in a region of the first main surface interposed between the gate electrodes. When,
A second first-conductivity-type low-resistance semiconductor layer formed on a second main surface of the first-conductivity-type high-resistance semiconductor layer;
A first main electrode formed on the conductive low-resistance semiconductor layer;
A first conductive type semiconductor layer comprising a second main electrode formed on the first first conductive type low-resistance semiconductor layer and having a carrier integration amount of about 5 × 10 ¹² cm ⁻² or less in a repeating direction; A power semiconductor element, wherein an auxiliary region in which second conductive semiconductor layers are alternately adjacent to each other is formed in at least a region of the first conductive high resistance semiconductor layer sandwiched between the gate electrodes. 3. A first conductive type high resistance semiconductor layer and a first conductive type high resistance semiconductor layer.
A second-conductivity-type low-resistance semiconductor layer formed at a predetermined distance from the main surface of the first conductive type; a first-conductivity-type low-resistance semiconductor layer formed on a second main surface of the first-conductivity-type high-resistance semiconductor layer; A first main electrode formed on the first conductive type low-resistance semiconductor layer and an ohmic contact with the second conductive type low-resistance semiconductor layer formed on the first main surface; The region between the semiconductor layers is composed of the second main electrode in Schottky contact, and the carrier integration amount in the repetition direction is approximately 5 × 10
^An auxiliary region in which the first conductivity type semiconductor layers and the second conductivity type semiconductor layers of ¹² cm ⁻² or less are alternately adjacent to each other is formed in at least the second conductivity type low resistance semiconductor layer of the first conductivity type high resistance semiconductor layer. A power semiconductor element formed in a sandwiched region, wherein the second conductive type semiconductor layer of the auxiliary region is connected to the second conductive type low resistance semiconductor layer. 4. A first conductive type high resistance semiconductor layer and a first conductive type high resistance semiconductor layer.
An electrode formed at a predetermined distance from the main surface of the first conductive type via an insulating film; a first conductive type low-resistance semiconductor layer formed on a second main surface of the first conductive type high-resistance semiconductor layer; A first main electrode formed on a one-conductivity-type low-resistance semiconductor layer;
And a second main electrode in ohmic contact with the electrode and sandwiched between the electrodes, the second main electrode having a Schottky contact, and the carrier integration amount in the repetitive direction is approximately 5 ×
An auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers of 10 ¹² cm ⁻² or less are alternately adjacent to each other is formed in at least a region of the first conductive type high resistance semiconductor layer sandwiched between the gate electrodes. A power semiconductor element characterized by being formed. 5. The high-resistance semiconductor layer of the first conductivity type is polished at a predetermined angle in advance, and on the terrace formed on the first main surface of the high-resistance semiconductor layer of the first conductivity type by the polishing,
The carrier integration amount in the repetition direction is approximately 5 × 10 ¹² cm
^In forming an auxiliary region in which the first conductive type semiconductor layers and the second conductive type semiconductor layers of ^-2 or less are alternately adjacent to each other by epitaxial growth, a single crystal is formed by a step flow from the step formed on the first main surface. Is grown, a second conductivity type impurity is added until a single crystal grows to just half of the terrace, and then a first conductivity type impurity is added until a single crystal grows on the entire terrace. A method for forming a semiconductor layer, wherein the auxiliary region is formed by repeating a cycle.