JP4351745B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a diode and a switching element are combined.
[0002]
[Prior art]
There is an inverter in a power electronics device that drives a motor. This inverter uses a switching element and a free-wheeling diode connected in reverse parallel thereto. These switching elements and diodes are required to have high speed in order to realize high-speed operation of the inverter. However, although the diode is required to have high speed, it is difficult to increase the speed because of the simple element structure.
[0003]
Conventionally, the diode has a structure such as “A novel soft and fast recovery diode (SFD) with thin P-layer formed by Al-Si electrode” (ISPSD'91 Conference.record p.113-p.117). Are known.
[0004]
FIG. 18 is a cross-sectional view showing a configuration of a diode having such a structure. An n− type base layer 2 is formed on the n + type emitter layer 1, and a p + type emitter layer 3 or a p− type emitter layer 4 is selectively formed on the surface of the n− type base layer 2. An anode electrode 5 is formed on the p + -type emitter layer 3 and the p − -type emitter layer 4. A cathode electrode 6 is formed on the n + -type emitter layer 1.
[0005]
In this diode, when a positive voltage is applied to the anode electrode 5 and a negative voltage is applied to the cathode electrode 6, electrons are injected from the n + -type emitter layer 1 as a cathode into the n − -type base layer 2 and p +. The type emitter layer 3 and the p − type emitter layer 4 are reached. Accordingly, holes are injected into the n − type base layer 2 from the p + type emitter layer 3 and the p − type emitter layer 4 as anodes. In this way, both electrons and holes are injected into the n − -type base layer 2 and turned on to accumulate carriers.
[0006]
Further, when a negative voltage is applied to the anode electrode 5 and a positive voltage is applied to the cathode electrode 6 at the time of turn-off, injection of electrons and holes stops and holes in the n − -type base layer 2 are It is discharged from the p + -type emitter layer 3 and the p − -type emitter layer 4 and is turned off.
[0007]
In this structure, a p-type emitter layer for injecting holes as an anode is divided into a p + -type layer 3 and a p − -type layer 4, and the injection amount of holes is limited by reducing the concentration of the p − -type layer 4. The carrier discharge speed is increased at the turn-off time.
[0008]
However, although the diode having this structure can realize high speed performance, there is a problem that a large amount of leakage current occurs because the p-type layer 4 has a low concentration. Furthermore, when a trench structure is used to increase the switching element speed, there is a problem that integration is difficult. Here, integration of diodes is an important issue for improving characteristics such as downsizing of the chip and reduction of connection inductance.
[0009]
On the other hand, as the switching element, an IGBT (Insulated Gate Bipolar Transistor) having a withstand voltage of about 600V to 1200V is widely used. However, an IGBT having a withstand voltage of 600 V generally has an n + -type buffer layer 12 formed on the surface of a p + -type collector layer 11 having a thickness of about 500 μm by an epitaxial method as shown in FIG. An extremely thin n − -type base layer 13 having a thickness of about 60 to 100 μm is formed on the substrate 12.
[0010]
Here, in order to integrate the diodes in antiparallel, the n + type emitter layer 1 in contact with the n − type base layer 13 instead of the p + type collector layer 11 on the anode side, that is, the p + type collector layer 11 side. Need to form. However, since the n− type base layer 13 is very thin, the n + type emitter layer 1 cannot be formed on the anode side, which makes it impossible to integrate the diodes.
[0011]
[Problems to be solved by the invention]
As described above, the conventional diode has a problem that the leakage current is large. Furthermore, when a trench structure is used to increase the switching element speed, there is a problem that integration is difficult. Further, the conventional IGBT has a problem that diodes cannot be integrated.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can reduce leakage current and can be easily integrated in a trench structure.
[0012]
[Means for Solving the Problems]
The gist of the present invention is to separate a p-type layer serving as an anode by a trench structure, and to limit injection of holes from the p-type layer by the trench. In other words, since the amount of injected holes is limited without reducing the concentration of the p-type layer, both good device characteristics by reducing leakage current and high-speed operation by high-speed carrier discharge at turn-off can be achieved. Can do.
[0013]
According to the present invention, since the diode has a trench structure, the diode and the switching element can be easily integrated when the switching element to be integrated has a trench structure.
[0015]
  Now, based on the gist of the present invention as described above, the following means are specifically taken.
Claim1The invention corresponding toA first conductive type base layer having a high resistance, a first conductive type emitter layer formed on one surface of the first conductive type base layer, and a first type formed on the other surface of the first conductive type base layer. A two-conductivity type emitter layer, a plurality of grooves formed at a depth penetrating the second conductive type emitter layer and reaching the middle of the first conductive type base layer, and formed in the first conductive type emitter layer And a second main electrode formed on the second conductive type emitter layer.Semiconductor deviceBecauseA semiconductor device comprising an insulating layer selectively disposed between a predetermined plurality of second conductivity type emitter layers of the second conductivity type emitter layers between the grooves and the second main electrode It is.
[0017]
  And claims2The first conductive type base layer having a high resistance; the first conductive type emitter layer formed on one surface of the first conductive type base layer; and the other of the first conductive type base layer. A first second conductivity type emitter layer selectively formed on the surface; and an impurity density lower than that of the first second conductivity type emitter layer; and the other surface of the first conductivity type base layer. Of these, the second second-conductivity-type emitter layer formed in a region without the first second-conductivity-type emitter layer and the first and second second-conductivity-type emitter layers pass through the first and second second-conductivity-type emitter layers. A plurality of grooves formed at a depth reaching a middle of the conductive type base layer, a first main electrode formed in the first conductive type emitter layer, and the first and second second conductive type emitters And a second main electrode formed in the layer.
  Claims3The invention corresponding to2In the semiconductor device corresponding to the above, the first and second second conductivity type emitter layers are formed in stripes in parallel with each other, and the grooves are formed in the longitudinal direction of the first and second second conductivity type emitter layers. The semiconductor device is formed along a direction substantially orthogonal to the.
  And claims4The first conductive type base layer having a high resistance; the first conductive type emitter layer formed on one surface of the first conductive type base layer; and the other of the first conductive type base layer. A second second-conductivity-type emitter layer formed on the surface; and a higher impurity density than the second second-conductivity-type emitter layer, and stripes on the surface of the second second-conductivity-type emitter layer The first and second conductivity type emitter layers selectively formed on the surface of the second and second conductivity type emitter layers are selectively formed in a region without the first and second conductivity type emitter layers. The first conductivity type source layer thus formed, the first second conductivity type emitter layer, and the first conductivity type source layer are penetrated through the both layers along a direction substantially perpendicular to the longitudinal direction of the first conductivity type source layer. A plurality of grooves formed at a depth reaching a middle of the conductive type base layer; Comprising a first main electrode formed on the emitter layer, and said first second main electrode formed on the second conductive type emitter layer and the first conductivity type source layerAct as a diodeIt is a semiconductor device.
(Function)
  Therefore, in the invention corresponding to claim 1, by taking the above-described means, the second conductivity type emitter layer is divided by each groove, and the injection of carriers from the second conductivity type emitter layer is limited. Therefore, carriers can be discharged at a high speed at the time of turn-off, and it is not necessary to reduce the concentration of the second conductivity type emitter layer, so that a good blocking characteristic can be realized without increasing the leakage current. .
[0018]
  Further, since the diode having this structure has a trench structure, it can be easily integrated when the switching element to be integrated has a trench structure.
  Claims1In the invention corresponding to the above, an insulating layer is selectively disposed between a predetermined plurality of second conductivity type emitter layers of the second conductivity type emitter layers between the grooves and the second main electrode. BecauseMentioned aboveIn addition to the function, the amount of injected carriers can be controlled more easily and accurately according to the arrangement of the insulating layer.
[0020]
  And claims2In addition to the same action as that of the first aspect, the invention corresponding to the second aspect provides a second second-conductivity-type emitter layer having a low impurity density in order to control the amount of injected holes. Since the second conductivity type emitter layer is surrounded by the groove and is not easily depleted, the leakage current can be reduced as compared with the conventional structure.
  Claims3The invention corresponding to2In addition, the first and second second conductivity type emitter layers are formed in a stripe shape in parallel with each other, and each groove is the length of the first and second second conductivity type emitter layers. Since it is formed along a direction substantially orthogonal to the direction, it is possible to facilitate patterning.
  And claims4In the invention corresponding to, after the second second conductivity type emitter layer having a low impurity density is formed on the entire surface, the regions of the first second conductivity type emitter layer and the first conductivity type source layer are partially alternated. The hole injection from the first second-conductivity-type emitter layer is limited thereby, and3The same action as that corresponding to can be achieved.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, each embodiment according to the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a diode according to a first embodiment of the present invention. The same parts as those in FIG. 18 are denoted by the same reference numerals and detailed description thereof is omitted, and different parts will be described here. . In the following embodiments, the description of the same parts is also omitted.
[0022]
That is, in this embodiment, unlike the prior art, the p + -type emitter layer 3 for injecting holes on the anode side is separated by the trench structure, and is configured without using the low-concentration p − -type layer 4. .
[0023]
Specifically, instead of selectively forming the p + -type emitter layer 3 and the p − -type emitter layer 4 on the n − -type base layer 2, the p + -type emitter layer 3 is formed on the entire surface of the n − -type base layer 2. A plurality of grooves 21 having a width T are formed on the surface of the p + -type emitter layer 3 at intervals W, and a filler 23 is embedded in each groove 21 with an insulating film 22 interposed therebetween.
[0024]
Here, each groove 21 is formed by a known RIE (Riactive Ion Etching) apparatus, and has a depth that penetrates the p + type emitter layer and reaches the middle of the n − type base layer. If the width T of the groove 21 is increased, the ON voltage is increased. The interval W between the grooves 21 is preferably about 4 μm or less in order to achieve a desired breakdown voltage.
[0025]
As the filler 23, for example, polycrystalline silicon can be used. However, as long as the groove 21 can be formed, it may or may not be filled by another method.
[0026]
With the above configuration, holes injected from the p + -type emitter layer 3 during forward bias can be limited by the trench structure, so that carriers can be discharged at high speed during turn-off.
[0027]
In addition, since the hole injection amount is limited by the trench structure, it is not necessary to reduce the concentration of the p + -type emitter layer 3 unlike the conventional case, so that an increase in leakage current can be prevented.
[0028]
FIG. 2 is a diagram showing the distribution of on-state hole density in comparison with the presence of trench (this embodiment) and the absence of trench (conventional structure). As shown in the figure, it can be seen that the amount of holes injected from the p + -type emitter layer 3 is reduced in the trench structure according to the present embodiment. Such a reduction in the amount of hole injection is realized due to a reduction in the area of the p + -type emitter layer 3 due to the groove and a reduction in the lifetime of the groove peripheral portion due to the groove 21.
[0029]
As described above, according to the present embodiment, by dividing the p + -type emitter layer 3 for injecting holes as an anode into a trench structure, the holes from the p + -type emitter layer are not increased without increasing leakage current. The injection amount is limited, and the carrier can be discharged at a high speed at the time of turn-off.
[0030]
In addition, since the diode according to the present embodiment has a trench structure, it can be easily integrated when the switching elements to be integrated have a trench structure.
(Second Embodiment)
FIG. 3 is a cross-sectional view showing a configuration of a diode according to the second embodiment of the present invention. The present embodiment is a modified configuration of the first embodiment and is intended to limit the amount of hole injection. Specifically, a portion between the p + -type emitter layer 3 and the anode electrode 5 is used. In addition, an insulating film 24 such as an oxide film is formed.
[0031]
Thereby, since holes are not injected from the p + -type emitter layer 3 on which the insulating film 24 is formed, the amount of holes injected as a whole can be reduced. Moreover, according to such a structure, hole injection can be controlled more easily and accurately.
(Third embodiment)
FIG. 4 is a sectional view showing a configuration of a diode according to the third embodiment of the present invention. This embodiment is a modified configuration of the first embodiment, in which a part of the p + -type emitter layer 3 between the grooves 21 is replaced with a p − -type emitter layer 25.
[0032]
Thus, the amount of holes injected from the p + -type emitter layer 3 can be controlled without using the insulating film 24 as in the second embodiment.
In this embodiment, since the p − type emitter layer 25 is surrounded by the groove 21 with the interval W of 4 μm or less described in the first embodiment, even if a reverse voltage is applied, the p − type emitter layer 25 is used. It is difficult for an electric field to be applied to the layer 25, and thus the p − -type emitter layer 25 is difficult to be depleted. That is, the p − -type emitter layer 25 is provided to control the amount of injected holes, but the leakage current can be reduced as compared with the conventional structure.
(Fourth embodiment)
FIG. 5 is a perspective sectional view showing the structure of a diode according to the fourth embodiment of the present invention. This embodiment is a modified configuration of the third embodiment, in which the p + -type emitter layer 3 and the p − -type emitter layer 25 are arranged in a two-dimensional direction. Although the anode electrode 5 is omitted for easy viewing, it is formed on the upper surface.
[0033]
With the configuration as described above, in addition to the effects of the third embodiment, the patterning can be facilitated.
(Fifth embodiment)
FIG. 6 is a perspective sectional view showing the structure of a diode according to the fifth embodiment of the present invention. This embodiment is a modified configuration of the fourth embodiment, and after the p− type emitter layer 26 is formed on the entire surface, the regions of the p + type emitter layer 27 and the n + type source layer 28 are partially alternated. Thus, the injection of holes from the p + -type emitter layer 27 is limited. As in FIG. 5, the anode electrode 5 is omitted for the sake of clarity, but is formed on the upper surface.
[0034]
Even with the configuration as described above, the same effects as those of the fourth embodiment can be obtained.
(Sixth embodiment)
FIG. 7 is a sectional view showing a configuration of a semiconductor device in which a diode and a switching element according to the sixth embodiment of the present invention are integrated. In this semiconductor device, the n − -type base layer is divided into an IGBT region as a switching element and a diode region. Of one surface of the n− type base layer 2, a p type base layer 31 is formed in the IGBT region, and an n + type source layer 32 is selectively formed on the surface of the p type base layer 31, and a diode. A p + -type emitter layer 33 is formed in the region.
[0035]
In the n + -type source layer 32 and the p + -type emitter layer 33, a plurality of grooves 21 penetrate the n + -type source layer 32 and the p + -type base layer 31 or the p + -type emitter layer 3, respectively. The base layer 2 is selectively formed to a depth in the middle. Each trench 21 is filled with a polysilicon filler 23 with a gate insulating film 22 interposed therebetween. Of the polysilicon filler 23, those in the IGBT region are electrically connected to the gate terminal G and function as a gate electrode. A K / A electrode 34 is formed on the n + -type source layer 32 and the p + -type emitter layer 3. The K / A electrode 34 is an electrode on the side that becomes a cathode in the IGBT and an anode in the diode.
[0036]
On the other hand, of the other surface of the n− type base layer 2, a p + type collector layer 33 is formed in the IGBT region, and an n + type emitter layer 1 is formed in the diode region. An A / K electrode 35 is formed on the n + -type emitter layer 1. The A / K electrode 35 is an electrode 35 that serves as an anode for the IGBT and a cathode for the diode.
[0037]
According to the above configuration, as easily understood from the figure, the diode of the present invention uses the gate portion made of the IGBT trench 21, the insulating film 22 and the filler 23 for injection control. In comparison, the integration can be remarkably simple.
[0038]
For this reason, a trial production process can be shortened and cost reduction can be realized. In the present embodiment, the IGBT is shown as the switching element. However, it is obvious that an element having another trench structure, such as a trench MOSFET, may be used. In the case of a trench MOSFET, the p + -type collector layer 33 is not necessary and can be manufactured more easily.
[0039]
Furthermore, although the diode of the first embodiment is used in the present embodiment, it is obvious that any diode of the second to fifth embodiments can be easily integrated.
(Seventh embodiment)
FIG. 8 is a sectional view showing a configuration of a semiconductor device in which a diode and a switching element according to the seventh embodiment of the present invention are integrated. This embodiment is a modification of the sixth embodiment, and prevents mutual interference between the IGBT region and the diode region. Specifically, the p + of the diode region in contact with the end of the IGBT region is used. An insulating layer 24 is formed between the mold emitter layer 3 and the K / A electrode 34.
[0040]
With the above configuration, an isolation region that does not operate as a diode is formed at the end of the diode region that is in contact with the end of the IGBT region, so that mutual interference between the IGBT and the diode is suppressed, and safer operation is realized. be able to.
(Eighth embodiment)
FIG. 9 is a sectional view showing a configuration of a semiconductor device in which a diode and a switching element according to the eighth embodiment of the present invention are integrated. This embodiment is a modified configuration of the sixth embodiment, and a termination structure is provided outside the IGBT region.
[0041]
This termination structure has a p + -type layer 41 formed in the n − -type base layer 2 so as to surround the trench 21 in which the outermost gate electrode of the IGBT region is buried, and the A / K electrode 35 And an n + -type layer 42 formed between the n--type base layer 2.
[0042]
Here, the diode region is arranged directly inside the IGBT region without being directly connected to the termination structure. If the diode is connected to the termination structure, the carrier in the on state flows to the termination structure, causing a problem that current concentration occurs at the turn-off and easily breaks down. No diode can be realized.
(Ninth embodiment)
FIG. 10 is a sectional view showing a configuration of a semiconductor device in which a diode and a switching element according to the ninth embodiment of the present invention are integrated.
[0043]
In this semiconductor device, one surface of the n − -type base layer has a structure in which a p-type base layer 31 and an n + -type source layer 32 are sandwiched between the grooves 21 as in the IGBT region described above. Each groove 21 is embedded with a polysilicon filler 23 functioning as a gate electrode through an insulating film 22 as described above.
[0044]
Here, on the other surface of the n− type base layer 2, a p + type collector layer 33 is formed in the IGBT region corresponding to each groove 21, and an n + type emitter is formed in the diode region corresponding to each groove 21 width T. Layer 1 is formed. An A / K electrode 35 is formed on the p + type collector layer 33 and the n + type emitter layer 1.
[0045]
With the above configuration, the IGBT p-type base layer 31 is used as the p-type layer of the diode, and the structure of the IGBT cathode side and the diode anode side (K / A electrode 34 side) is completely integrated. ing. Thereby, the chip area can be used effectively, and integration of the diode and the switching element can be realized with a smaller area. This structure can suppress problems such as mutual interference between the IGBT region and the diode region by appropriately setting the element design conditions such as the carrier lifetime in the n − -type base layer 2. Needless to say.
(Tenth embodiment)
FIG. 11 is a sectional view showing a configuration of a semiconductor device in which a diode and a switching element according to the tenth embodiment of the present invention are integrated. This semiconductor device has a modified configuration of the ninth embodiment. Specifically, as shown in the figure, a p + type collector layer 33 corresponding to the IGBT region and an n + type emitter layer 1 corresponding to the diode region. Are formed on the n− type base layer 2 without being mixed.
[0046]
That is, according to the above configuration, the structure of the n-type source layer 32 portion of the IGBT is used for the p-type layer in the diode region. This eliminates the need for mask alignment between the n + -type emitter layer 1 in the diode region and the p + -type collector layer 33 in the IGBT region, and is easy to manufacture. Also, the diode region can be used as a MOSFET, and in this case, a larger amount of current can flow than when only the IGBT region is used.
(Eleventh embodiment)
The above is the description of the semiconductor device including the diode according to the present invention. Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to eleventh and twelfth embodiments. According to the following eleventh or twelfth embodiment, an integrated structure of a planar structure IGBT and a normal diode shown in FIG. 12, or an integration of a trench structure IGBT and a trench structure diode shown in FIG. The structure can be realized. That is, this manufacturing process can be applied to all structures having the p + -type layer 33 that becomes the collector layer of the IGBT and the n + -type layer 1 that becomes the emitter layer of the diode.
[0047]
Next, FIGS. 14 and 15 are manufacturing process diagrams showing a manufacturing method for manufacturing an integrated structure of an IGBT and a diode according to the eleventh embodiment of the present invention.
Now, as shown in FIG. 14 (a), the n + -type layer 1a as a diode is selectively formed on the surface of the n--type substrate 51 by diffusion or the like. Subsequently, as shown in FIG. 14B, an n @-type layer 2a is epitaxially grown on the entire surface of the n @ + type substrate having the n @ + type layer 1a. At this time, the thickness of the n + type substrate 51 can be arbitrarily increased to 500 μm or more, and there is no problem in manufacturing.
[0048]
Thereafter, as shown in FIG. 15A, after the cathode structure of the IGBT is formed on the surface of the n− type layer 2a by a known manufacturing process, the n− type substrate 51 is formed from the back surface of the n + type layer 1a. Polished halfway.
[0049]
Subsequently, as shown in FIG. 15B, a thin p + type collector layer 33 is formed on the back surface of the n− type substrate 51 by an ion implantation process and a heat treatment process of the p + type dopant, and finally A / K. Electrode 35 and K / A electrode 34 are formed. The process shown in FIG. 15B after polishing hardly requires a PEP process, and even if the wafer is thin, it is not difficult to manufacture.
[0050]
As described above, according to the present embodiment, instead of the substrate serving as the p + -type collector layer 33, the n + -type layer 1a is selectively formed on the n − -type substrate 51 in advance by diffusion or the like, and then the n + After forming the n − type base layer 2a on the surface of the mold layer 1a by an epitaxial method or the like and forming the cathode structure of the IGBT (the anode side of the diode), the n − type substrate 51 is thinned by polishing or the like, Further, by forming the p + -type collector layer 33, the diode can be integrated with the thin n − -type base layer 2a.
(Twelfth embodiment)
16 and 17 are manufacturing process diagrams for explaining a manufacturing method for integrating the IGBT and the diode according to the twelfth embodiment of the present invention. Unlike the eleventh embodiment, this embodiment has a procedure for forming the anode side of the IGBT first and then thinning the wafer by polishing.
[0051]
Now, as shown in FIG. 16A, p @ + -type layer 33a and n @ + -type layer 1a are selectively formed on one surface of the n @-type substrate by selective ion implantation or heat treatment. Subsequently, as shown in FIG. 16B, the surface of the n + -type substrate 51 on the p + -type layer 33a and the n + -type layer 1a side and the oxide film 52 side of the silicon substrate 53 having the oxide film 52 on the surface. The surface is bonded. Thereafter, the n− type substrate 51 is thinned by polishing and formed on the n− type layer 2a.
[0052]
Hereinafter, as shown in FIG. 17A, an IGBT cathode structure is formed on the surface of the n − -type layer 2a by a known manufacturing process. Thereafter, as shown in FIG. 17B, the silicon substrate 53 and the oxide film 52 are removed by polishing or the like, and the A / K electrode 34 is formed on the exposed surfaces of the p + type layer 33a and the n + type layer 1a. Is formed. Thereafter, the device is completed by forming the K / A electrode 34 and the like.
[0053]
As described above, according to the present embodiment, the IGBT and the diode can be integrated while having the thin n − -type base layer 2a as in the eleventh embodiment.
In the eleventh and twelfth embodiments, the manufacturing method in which the IGBT and the diode are integrated is shown as an example. However, the manufacturing method described in this embodiment is not limited to this, and has a thin active layer. It is clear that it can be generally used as a semiconductor manufacturing method.
In addition, the present invention can be implemented with various modifications without departing from the gist thereof.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor device that can reduce leakage current and can be easily integrated in a trench structure.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a diode according to a first embodiment of the present invention.
FIG. 2 is a graph showing the distribution of on-state hole density in the same embodiment as compared with that without trenches
FIG. 3 is a cross-sectional view showing a configuration of a diode according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a diode according to a third embodiment of the present invention.
FIG. 5 is a perspective sectional view showing a configuration of a diode according to a fourth embodiment of the present invention.
FIG. 6 is a perspective sectional view showing the configuration of a diode according to a fifth embodiment of the invention.
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a ninth embodiment of the invention.
FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a tenth embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a configuration of a semiconductor device manufactured by the manufacturing method according to the eleventh or twelfth embodiment.
FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device manufactured by the manufacturing method according to the eleventh or twelfth embodiment.
FIG. 14 is a manufacturing process diagram showing a manufacturing method according to the eleventh embodiment of the present invention;
FIG. 15 is a manufacturing process diagram according to the embodiment.
FIG. 16 is a manufacturing process diagram showing a manufacturing method according to a twelfth embodiment of the present invention;
FIG. 17 is a manufacturing process diagram according to the embodiment.
FIG. 18 is a sectional view showing a configuration of a conventional diode.
FIG. 19 is a cross-sectional view showing a configuration of a conventional IGBT.
[Explanation of symbols]
1,1a ... n + type emitter layer
2,2a ... n-type base layer
3, 27, 33, 33a... P @ + type emitter layer
5 ... Anode electrode
6 ... Cathode electrode
21 ... Groove
22, 24 ... Insulating film
23. Filler
25, 26 ... p-type emitter layer
28, 32 ... n + type source layer
31 ... p-type base layer
34 ... K / A electrode
35 ... A / K electrode
41 ... p + type layer
42 ... n + type layer
51 ... n-type substrate
52 ... Oxide film
53. Silicon substrate

Claims (4)

A high resistance first conductivity type base layer;
A first conductivity type emitter layer formed on one surface of the first conductivity type base layer;
A second conductivity type emitter layer formed on the other surface of the first conductivity type base layer;
A plurality of grooves formed at a depth penetrating the second conductivity type emitter layer and reaching the middle of the first conductivity type base layer;
A first main electrode formed on the first conductivity type emitter layer;
A semiconductor device comprising: a second main electrode formed on the second conductivity type emitter layer;
An insulating layer selectively provided between a plurality of predetermined second conductivity type emitter layers among the second conductivity type emitter layers between the grooves and the second main electrode is provided. A semiconductor device. A high resistance first conductivity type base layer;
A first conductivity type emitter layer formed on one surface of the first conductivity type base layer;
A first second conductivity type emitter layer selectively formed on the other surface of the first conductivity type base layer;
The first conductive type base layer has an impurity density lower than that of the first second conductive type emitter layer, and is formed in a region without the first second conductive type emitter layer in the other surface of the first conductive type base layer. A second second conductivity type emitter layer;
A plurality of grooves formed to a depth reaching the middle of the first conductive type base layer through the first and second second conductive type emitter layers;
A first main electrode formed on the first conductivity type emitter layer;
And a second main electrode formed on the first and second second conductivity type emitter layers. The semiconductor device according to claim 2 ,
The first and second second conductivity type emitter layers are formed in stripes in parallel with each other,
Each of the grooves is formed along a direction substantially perpendicular to the longitudinal direction of the first and second second-conductivity-type emitter layers. A high resistance first conductivity type base layer;
A first conductivity type emitter layer formed on one surface of the first conductivity type base layer;
A second second conductivity type emitter layer formed on the other surface of the first conductivity type base layer;
A first second conductivity type emitter layer having an impurity density higher than that of the second second conductivity type emitter layer and selectively formed in a stripe shape on the surface of the second second conductivity type emitter layer. When,
A first conductivity type source layer selectively formed in a region of the surface of the second second conductivity type emitter layer without the first second conductivity type emitter layer;
Depth reaching the middle of the first conductivity type base layer through both layers along a direction substantially perpendicular to the longitudinal direction of the first second conductivity type emitter layer and the first conductivity type source layer A plurality of grooves formed in the
A first main electrode formed on the first conductivity type emitter layer;
And a second main electrode formed on the first second conductivity type emitter layer and the first conductivity type source layer, and operating as a diode .

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