JP2012190873A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
JP2012190873A
JP2012190873A JP2011050995A JP2011050995A JP2012190873A JP 2012190873 A JP2012190873 A JP 2012190873A JP 2011050995 A JP2011050995 A JP 2011050995A JP 2011050995 A JP2011050995 A JP 2011050995A JP 2012190873 A JP2012190873 A JP 2012190873A
Authority
JP
Japan
Prior art keywords
type
layer
impurity concentration
voltage
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011050995A
Other languages
Japanese (ja)
Inventor
Akito Nishii
昭人 西井
Katsumitsu Nakamura
勝光 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2011050995A priority Critical patent/JP2012190873A/en
Priority to US13/237,309 priority patent/US20120228700A1/en
Priority to DE102011089452.7A priority patent/DE102011089452B4/en
Priority to KR1020120022160A priority patent/KR101329613B1/en
Priority to CN201210071923.7A priority patent/CN102683427B/en
Publication of JP2012190873A publication Critical patent/JP2012190873A/en
Priority to US14/336,800 priority patent/US9202936B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows controlling the trade-off characteristics between on-voltage and recovery loss without lifetime control by controlling the on voltage by the impurity concentration of a P-type anode layer and allows preventing snap-off phenomenon, while maintaining the withstand voltage without depending on the impurity concentration of the P-type anode layer.SOLUTION: A P-type anode layer 2 is provided above an N-type drift layer 1. Trenches 3 are provided so as to penetrate through the P-type anode layer. In each trench 3, a conductive material 5 is buried via an insulating film 4. An N-type buffer layer 6 is provided between the N-type drift layer 1 and the P-type anode layer 2. The N-type buffer layer 6 has a higher impurity concentration than the N-type drift layer 1.

Description

本発明は、６００Ｖ以上の高耐圧パワーモジュールを構成する半導体装置の１つであるダイオードに関し、特に発振耐量やリカバリー耐量を向上させることができ、かつスナップオフ現象を抑制できる半導体装置及びその製造方法に関する。   The present invention relates to a diode that is one of semiconductor devices constituting a high-withstand-voltage power module of 600 V or more, and in particular, a semiconductor device that can improve oscillation resistance and recovery resistance and can suppress a snap-off phenomenon, and a manufacturing method thereof. About.

図３０は、ダイオードのオン電圧ＶＦとリカバリー損失Ｅｒｅｃの関係を示す図である。両者の間にはレードオフの関係がある。応用する製品に応じて、トレードオフカーブ上の任意の点を利用する。従来はトレードオフカーブ上の任意の点の特性を持つダイオードを得るために、Ｐ型アノード層の不純物濃度を制御するか、又は電子線照射によりライフタイムを制御していた。   FIG. 30 is a diagram illustrating the relationship between the diode on-voltage VF and the recovery loss Erec. There is a raid-off relationship between the two. Any point on the trade-off curve is used depending on the product to be applied. Conventionally, in order to obtain a diode having characteristics at an arbitrary point on the trade-off curve, the impurity concentration of the P-type anode layer is controlled, or the lifetime is controlled by electron beam irradiation.

ダイオードに逆バイアスを印加した場合、空乏層がアノードとカソードの両側に伸びていく。Ｐ型アノード層の不純物濃度を低くすると、高電圧を印加した際に空乏層がアノード側に伸びやすくなるため、電界がアノード側でリーチスルーを起こして耐圧の低下を招くという問題がある。ただし、Ｐ型アノード層の不純物濃度を低くすると、リカバリー動作時の逆回復電流Ｉｒｒを小さくできるため、リカバリー損失を低減することができる。そこで、従来は、Ｉｒｒを小さくするためにＰ型アノード層の不純物濃度を耐圧保持可能な範囲で低くし、ライフタイムを制御してトレードオフカーブ上の任意の特性を得てきた。また、これまでに低リーク電流化、低Ｉｒｒ化等を目的として、アノード側にトレンチを形成したダイオードが提案されてきている（例えば、特許文献１参照）。   When a reverse bias is applied to the diode, the depletion layer extends on both sides of the anode and the cathode. If the impurity concentration of the P-type anode layer is lowered, the depletion layer tends to extend to the anode side when a high voltage is applied, so that there is a problem that the electric field causes reach-through on the anode side and the breakdown voltage is lowered. However, if the impurity concentration of the P-type anode layer is lowered, the reverse recovery current Irr during the recovery operation can be reduced, so that the recovery loss can be reduced. Therefore, conventionally, in order to reduce Irr, the impurity concentration of the P-type anode layer is lowered within a range where the withstand voltage can be maintained, and the lifetime is controlled to obtain an arbitrary characteristic on the trade-off curve. In addition, a diode having a trench formed on the anode side has been proposed for the purpose of reducing leakage current, reducing Irr, and the like (see, for example, Patent Document 1).

特開平１１−９７７１５号公報JP-A-11-97715

従来技術では、ＶＦ−Ｅｒｅｃトレードオフ特性をライフタイム制御技術により制御しているため、クロスポイントが大きく変化し、並列動作時に制御しにくいという問題がある。また、Ｉｒｒを小さくするためにＰ型アノード層の不純物濃度を低くしたいが、耐圧保持の観点より、濃度を低くできないという問題がある。   In the prior art, since the VF-Erec trade-off characteristic is controlled by the lifetime control technology, there is a problem that the cross point changes greatly and is difficult to control during parallel operation. Further, it is desired to reduce the impurity concentration of the P-type anode layer in order to reduce Irr. However, there is a problem that the concentration cannot be lowered from the viewpoint of maintaining the breakdown voltage.

厳しい条件（電源電圧Ｖｃｃが高く、電流密度Ｊｃが低く、浮遊インダクタンスＬｓが高い）下でリカバリー動作させた場合、その動作終端において逆回復電流が０になる際にカソード付近のキャリア密度が急激に変化する。それによって電流密度変化率ｄｊｒ／ｄｔが大きくなることで、アノード−カソード間電圧が電源電圧よりも跳ね上がるスナップオフ現象が発生する。その時のスナップオフ電圧Ｖｓｎａｐ−ｏｆｆがダイオードの耐圧を越える場合、デバイス破壊に至るという問題がある。従って、スナップオフ現象を抑制させる必要がある。   When recovery operation is performed under severe conditions (power supply voltage Vcc is high, current density Jc is low, and stray inductance Ls is high), the carrier density near the cathode rapidly increases when the reverse recovery current becomes zero at the end of the operation. Change. As a result, the current density change rate djr / dt increases, and a snap-off phenomenon occurs in which the anode-cathode voltage jumps higher than the power supply voltage. When the snap-off voltage Vsnap-off at that time exceeds the breakdown voltage of the diode, there is a problem that the device is destroyed. Therefore, it is necessary to suppress the snap-off phenomenon.

また、リカバリー動作における破壊として、電圧破壊と熱破壊がある。熱破壊の一つのモデルでは、終端領域内の残留キャリアがリカバリー動作時にアノード終端部に集中することで、当該箇所で温度が上昇し、熱破壊に至る。従って、キャリアがアノード終端部に集中するような構造では、リカバリー耐量が小さいという問題があった。   Moreover, there are voltage breakdown and thermal breakdown as breakdown in the recovery operation. In one model of thermal breakdown, residual carriers in the termination region concentrate on the anode termination portion during the recovery operation, so that the temperature rises at that location, leading to thermal breakdown. Therefore, there is a problem that the recovery tolerance is small in the structure in which the carriers are concentrated on the anode terminal portion.

本発明は、上述のような課題を解決するためになされたもので、第１の目的はＰ型アノード層の不純物濃度に依存せずに耐圧を保持しながら、Ｐ型アノード層の不純物濃度によってオン電圧を制御してライフタイム制御無しでオン電圧とリカバリー損失のトレードオフ特性を制御することができ、かつスナップオフ現象を抑制できる半導体装置及びその製造方法を得るものである。第２の目的は、リカバリー耐量を向上させることができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems. The first object is to maintain the withstand voltage without depending on the impurity concentration of the P-type anode layer, and to adjust the impurity concentration of the P-type anode layer. It is possible to obtain a semiconductor device and a manufacturing method thereof that can control a trade-off characteristic between an on-voltage and a recovery loss without controlling lifetime by controlling the on-voltage and can suppress a snap-off phenomenon. The second object is to obtain a semiconductor device capable of improving the recovery tolerance.

第１の発明に係る半導体装置は、Ｎ型ドリフト層と、前記Ｎ型ドリフト層上に設けられたＰ型アノード層と、前記Ｐ型アノード層を貫通するトレンチと、前記トレンチ内に絶縁膜を介して埋め込まれた導電性物質と、前記Ｎ型ドリフト層と前記Ｐ型アノード層の間に設けられ、前記Ｎ型ドリフト層よりも高い不純物濃度を持つＮ型バッファ層とを備えることを特徴とする。   A semiconductor device according to a first aspect of the present invention includes an N-type drift layer, a P-type anode layer provided on the N-type drift layer, a trench penetrating the P-type anode layer, and an insulating film in the trench. And an N-type buffer layer provided between the N-type drift layer and the P-type anode layer and having an impurity concentration higher than that of the N-type drift layer. To do.

第２の発明に係る半導体装置は、Ｎ型ドリフト層と、前記Ｎ型ドリフト層上の一部に設けられたＰ型アノード層と、前記Ｐ型アノード層に接続されたアノード電極と、Ｐ型アノード層の外端部と前記アノード電極との間に設けられた絶縁膜とを備え、前記Ｐ型アノード層の外端と前記絶縁膜の内端との間の長さが１００μｍ以上であることを特徴とする。   A semiconductor device according to a second invention includes an N-type drift layer, a P-type anode layer provided in a part on the N-type drift layer, an anode electrode connected to the P-type anode layer, and a P-type An insulating film provided between the outer end of the anode layer and the anode electrode, and the length between the outer end of the P-type anode layer and the inner end of the insulating film is 100 μm or more It is characterized by.

第１の発明により、Ｐ型アノード層の不純物濃度に依存せずに耐圧を保持しながら、Ｐ型アノード層の不純物濃度によってオン電圧を制御してライフタイム制御無しでオン電圧とリカバリー損失のトレードオフ特性を制御することができ、かつスナップオフ現象を抑制できる。第２の発明により、リカバリー耐量を向上させることができる。   According to the first invention, while maintaining the breakdown voltage without depending on the impurity concentration of the P-type anode layer, the on-voltage is controlled by the impurity concentration of the P-type anode layer, and the trade-off between the on-voltage and the recovery loss without lifetime control. The off characteristics can be controlled and the snap-off phenomenon can be suppressed. According to the second invention, the recovery tolerance can be improved.

本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. トレンチが有る場合と無い場合におけるアノード部の電界強度分布を示す図である。It is a figure which shows the electric field strength distribution of the anode part in the case where there is a trench and it is not. Ｐ型アノード層の不純物濃度とオン電圧ＶＦ及び耐圧ＢＶｒｒｍの関係を示す図である。It is a figure which shows the relationship between the impurity concentration of a P-type anode layer, ON voltage VF, and the proof pressure BVrrm. 従来のダイオード構造を示す断面図である。It is sectional drawing which shows the conventional diode structure. 従来技術と本発明のそれぞれのトレードオフ制御方法によるＶＦ−Ｅｒｅｃトレードオフ特性の違いを示す図である。It is a figure which shows the difference in the VF-Erec trade-off characteristic by each trade-off control method of a prior art and this invention. トレンチが有る場合と無い場合におけるＮ型バッファ層の不純物濃度と耐圧ＢＶｒｒｍの関係を示す図である。It is a figure which shows the relationship between the impurity concentration of an N type buffer layer, and the proof pressure BVrrm with and without a trench. オン電圧ＶＦとクロスポイントの関係を示す図である。It is a figure which shows the relationship between ON voltage VF and a cross point. トレンチの深さと耐圧の関係を示す図である。It is a figure which shows the relationship between the depth of a trench, and a proof pressure. アノード幅及びトレンチ幅とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆの関係を示す図である。It is a figure which shows the relationship between an anode width | variety and a trench width | variety, and the snap-off voltage Vsnap-off. Ｎ型バッファ層の不純物濃度とオン電圧ＶＦの関係を示す図である。It is a figure which shows the relationship between the impurity concentration of an N type buffer layer, and ON voltage VF. Ｎ型バッファ層の不純物濃度とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆの関係を示す図である。It is a figure which shows the relationship between the impurity concentration of a N-type buffer layer, and snap-off voltage Vsnap-off. Ｐ＋型コンタクト層が有る場合と無い場合におけるＰ型アノード層の不純物濃度とオン電圧の関係を示す図である。It is a figure which shows the relationship between the impurity concentration of a P-type anode layer, and an on-voltage in the case where a P + type contact layer exists and does not exist. 図１１及び図１３のシミュレーションに用いた回路及びその回路のパラメータを示す図である。It is a figure which shows the circuit used for the simulation of FIG.11 and FIG.13, and the parameter of the circuit. 本発明の実施の形態１に係る半導体装置を示す上面図である。It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. 比較例１に係る半導体装置を示す上面図である。7 is a top view showing a semiconductor device according to Comparative Example 1. FIG. 比較例２に係る半導体装置の製造方法を示す断面図である。10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Comparative Example 2. FIG. 比較例２に係る半導体装置の製造方法を示す断面図である。10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Comparative Example 2. FIG. 本発明の実施の形態１と比較例２に係る製造方法によりそれぞれ製造したダイオードのリーク電流密度Ｊｒｒｍを示す図である。It is a figure which shows the leakage current density Jrrm of the diode each manufactured with the manufacturing method which concerns on Embodiment 1 and Comparative Example 2 of this invention. Ｐ型カソード層のドーズ量とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆとの関係を示す図である。It is a figure which shows the relationship between the dose amount of a P-type cathode layer, and the snap-off voltage Vsnap-off. Ｐ型カソード層のドーズ量とリカバリー動作時のオフ時間ｔｒｒとの関係を示す図である。It is a figure which shows the relationship between the dose amount of a P-type cathode layer, and the off time trr at the time of a recovery operation. 本発明の実施の形態１に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 長さＬａｂｒとチップ内最大温度の関係をシミュレーションした結果を示す図である。It is a figure which shows the result of having simulated the relationship between length Labr and the maximum temperature in a chip | tip. 図２６のシミュレーションに用いた回路及びその回路のパラメータを示す図である。It is a figure which shows the circuit used for the simulation of FIG. 26, and the parameter of the circuit. ダイオードのリカバリーＳＯＡ（Safety Operation Area）を示す図である。It is a figure which shows the recovery SOA (Safety Operation Area) of a diode. 本発明の実施の形態２に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on Embodiment 2 of this invention. ダイオードのオン電圧ＶＦとリカバリー損失Ｅｒｅｃの関係を示す図である。It is a figure which shows the relationship between the ON voltage VF of a diode, and the recovery loss Erec.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。Ｎ−型ドリフト層１上にＰ型アノード層２が設けられている。Ｐ型アノード層を貫通するようにトレンチ３が設けられている。トレンチ３内に絶縁膜４を介して導電性物質５が埋め込まれている。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. A P-type anode layer 2 is provided on the N − -type drift layer 1. A trench 3 is provided so as to penetrate the P-type anode layer. A conductive substance 5 is embedded in the trench 3 via an insulating film 4.

また、ＯＮ状態でのホールの注入を抑制することでリカバリー動作時の逆回復電流Ｉｒｒを低下させるために、Ｎ−型ドリフト層１とＰ型アノード層２の間にＮ型バッファ層６が設けられている。Ｎ型バッファ層６は、Ｐ型アノード層２よりも低く、Ｎ−型ドリフト層１よりも高い不純物濃度を持つ。 In addition, an N-type buffer layer 6 is provided between the N − -type drift layer 1 and the P-type anode layer 2 in order to reduce the reverse recovery current Irr during the recovery operation by suppressing the injection of holes in the ON state. It has been. N-type buffer layer 6 has an impurity concentration lower than that of P-type anode layer 2 and higher than that of N − -type drift layer 1.

トレンチ３内の導電性物質５はアノード電極７に接続され、アノード電極７と同電位になっている。これによって、逆バイアス印加時にトレンチ３がＧＮＤとなり、フィールドプレート効果によって、Ｐ型アノード層２とＮ型バッファ層６のＰＮ接合部の電界上昇を抑制することができる。   The conductive material 5 in the trench 3 is connected to the anode electrode 7 and has the same potential as the anode electrode 7. As a result, the trench 3 becomes GND when a reverse bias is applied, and an increase in the electric field at the PN junction between the P-type anode layer 2 and the N-type buffer layer 6 can be suppressed by the field plate effect.

さらに、アノード電極７とのオーミックコンタクトを確保するために、Ｐ型アノード層２とアノード電極７との間にＰ型アノード層２よりも高濃度（≧１×１０１９ｃｍ−３）なＰ＋型コンタクト層８が設けられている。 Furthermore, in order to ensure ohmic contact with the anode electrode 7, P + having a higher concentration (≧ 1 × 10 19 cm −3 ) than the P-type anode layer 2 between the P-type anode layer 2 and the anode electrode 7. A mold contact layer 8 is provided.

Ｎ−型ドリフト層１の下面には、Ｎ＋型カソード層９とＰ型カソード層１０がそれぞれ設けられている。Ｐ型カソード層１０は、所望の電気特性になるように適切な濃度に設計される。また、Ｎ＋型カソード層９とＰ型カソード層１０の直上にそれぞれＮ型層１１，１２が形成される。このＮ型層１１，１２により、順バイアス印加時のキャリア注入をしやすくすることができ、逆バイアス印加時のパンチスルーを防止することができ、リカバリー動作時のホール注入を制御することができる。なお、各層の不純物濃度をＮ型層１２≦Ｎ型層１１＜Ｐ型カソード層１０＜Ｎ＋型カソード層９にする。 On the lower surface of the N − type drift layer 1, an N + type cathode layer 9 and a P type cathode layer 10 are provided. The P-type cathode layer 10 is designed to have an appropriate concentration so as to obtain desired electrical characteristics. In addition, N-type layers 11 and 12 are formed immediately above the N + -type cathode layer 9 and the P-type cathode layer 10, respectively. The N-type layers 11 and 12 can facilitate carrier injection during forward bias application, can prevent punch-through during reverse bias application, and can control hole injection during recovery operation. . The impurity concentration of each layer is N type layer 12 ≦ N type layer 11 <P type cathode layer 10 <N + type cathode layer 9.

続いて、本発明の実施の形態１に係る半導体装置の製造方法について説明する。図２，３は本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。まず、Ｎ−型ドリフト層１の上面にＰ型アノード層２等を形成する。次に、図２に示すように、マスク１３を用いてＮ−型ドリフト層１の下面の第１の領域にＮ＋型カソード層９を選択的に形成する。次に、図３に示すように、マスク１４を用いてＮ−型ドリフト層１の下面の第１の領域とは異なる第２の領域にＰ型カソード層１０を選択的に形成する。 Subsequently, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described. 2 and 3 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. First, the P-type anode layer 2 and the like are formed on the upper surface of the N − -type drift layer 1. Next, as shown in FIG. 2, an N + type cathode layer 9 is selectively formed in the first region on the lower surface of the N − type drift layer 1 using a mask 13. Next, as shown in FIG. 3, a P-type cathode layer 10 is selectively formed in a second region different from the first region on the lower surface of the N − -type drift layer 1 using a mask 14.

図４は、トレンチが有る場合と無い場合におけるアノード部の電界強度分布を示す図である。トレンチ３が有る場合、トレンチ３によるフィールドプレート効果により、ＰＮ接合部の電界をＮ−型ドリフト層１側に伸ばす。これにより、ＰＮ接合部の電界強度の上昇を抑制することができる。 FIG. 4 is a diagram showing the electric field intensity distribution in the anode portion with and without the trench. When the trench 3 is present, the electric field at the PN junction is extended to the N − type drift layer 1 side by the field plate effect of the trench 3. Thereby, the raise of the electric field strength of a PN junction part can be suppressed.

Ｐ型アノード層の不純物濃度を低くすると、逆バイアス印加時に空乏層がＰ型アノード層２側に伸びやすくなり、ＰＮ接合部の電界強度が上昇しやすくなる。従って、トレンチ３が無い場合、ＰＮ接合部において低電圧でアバランシェ降伏を起こすため、耐圧が低下する。一方、トレンチ３を設けることによって、ＰＮ接合部の電界を低下できるため、Ｐ型アノード層２の不純物濃度を低くしても耐圧の低下を防ぐことができる。   When the impurity concentration of the P-type anode layer is lowered, the depletion layer tends to extend toward the P-type anode layer 2 when a reverse bias is applied, and the electric field strength at the PN junction portion is likely to increase. Therefore, in the absence of the trench 3, the breakdown voltage is lowered because avalanche breakdown occurs at a low voltage at the PN junction. On the other hand, since the electric field at the PN junction can be reduced by providing the trench 3, the breakdown voltage can be prevented from being lowered even if the impurity concentration of the P-type anode layer 2 is lowered.

図５は、Ｐ型アノード層の不純物濃度とオン電圧ＶＦ及び耐圧ＢＶｒｒｍの関係を示す図である。Ｐ型アノード層の不純物濃度によって順バイアス印加時の正孔注入量が変化するため、オン電圧が変化する。Ｐ型アノード層の不純物濃度が低下した場合に、図６に示す従来構造では前述したように耐圧が低下するのに対して、実施の形態１の構造では耐圧を保持することができる。   FIG. 5 is a diagram showing the relationship between the impurity concentration of the P-type anode layer, the ON voltage VF, and the withstand voltage BVrrm. Since the amount of hole injection during forward bias application varies depending on the impurity concentration of the P-type anode layer, the on-voltage varies. When the impurity concentration of the P-type anode layer decreases, the breakdown voltage decreases as described above in the conventional structure shown in FIG. 6, whereas the breakdown voltage can be maintained in the structure of the first embodiment.

図７は、従来技術と本発明のそれぞれのトレードオフ制御方法によるＶＦ−Ｅｒｅｃトレードオフ特性の違いを示す図である。ライフタイム制御による従来の制御方法では、Ｐ型アノード層の不純物濃度で決まる高いＶＦの範囲でしかトレードオフ特性を制御できない。これに対し、トレンチ構造を用いたＰ型アノード層の不純物濃度による本発明の制御方法では、Ｐ型不純物濃度を低くしても、耐圧保持が可能である。このため、Ｐ型アノード層の不純物濃度に依存せずに耐圧を保持しながら、Ｐ型アノード層の不純物濃度によってＶＦを制御してトレードオフ特性を制御することができる。   FIG. 7 is a diagram illustrating a difference in VF-Erec trade-off characteristics between the conventional technique and the trade-off control methods of the present invention. With the conventional control method based on lifetime control, the trade-off characteristics can be controlled only within a high VF range determined by the impurity concentration of the P-type anode layer. On the other hand, with the control method of the present invention based on the impurity concentration of the P-type anode layer using the trench structure, the breakdown voltage can be maintained even if the P-type impurity concentration is lowered. For this reason, it is possible to control the trade-off characteristics by controlling VF according to the impurity concentration of the P-type anode layer while maintaining the breakdown voltage without depending on the impurity concentration of the P-type anode layer.

図８は、トレンチが有る場合と無い場合におけるＮ型バッファ層の不純物濃度と耐圧ＢＶｒｒｍの関係を示す図である。トレンチ３が無い場合、Ｎ型バッファ層６の不純物濃度が高くなると、ＰＮ接合部の電界が上昇しやすくなり、耐圧が低下する。一方、トレンチ３がある場合、ＰＮ接合部の電界上昇は緩和されるため、Ｎ型バッファ層６を設けても耐圧が保持される。また、Ｎ型バッファ層６の不純物濃度が高くなると、相対的にＰ型アノード層２の不純物濃度が低くなる。   FIG. 8 is a diagram showing the relationship between the impurity concentration of the N-type buffer layer and the breakdown voltage BVrrm with and without a trench. When the trench 3 is not provided, when the impurity concentration of the N-type buffer layer 6 is increased, the electric field at the PN junction portion is likely to increase and the breakdown voltage is decreased. On the other hand, when the trench 3 is present, the electric field rise at the PN junction is alleviated, so that the breakdown voltage is maintained even if the N-type buffer layer 6 is provided. Further, when the impurity concentration of the N-type buffer layer 6 is increased, the impurity concentration of the P-type anode layer 2 is relatively lowered.

図９は、オン電圧ＶＦとクロスポイントの関係を示す図である。ライフタイム制御によりオン電圧ＶＦを変化させた場合に比べて、Ｐ型アノード層２の不純物濃度制御によりオン電圧ＶＦを変化させた方が、クロスポイントの増大を抑制できる。ここで、ダイオードを搭載するパワーモジュールではチップを並列動作させるため、クロスポイントが定格電流密度より高いチップが搭載されると、そのチップに電流集中し並列動作の制御がしづらくなる。従って、クロスポイントの増大を抑制できる本実施の形態のダイオードは有効である。   FIG. 9 is a diagram illustrating the relationship between the on-voltage VF and the cross point. Compared with the case where the ON voltage VF is changed by lifetime control, the increase of the cross point can be suppressed by changing the ON voltage VF by controlling the impurity concentration of the P-type anode layer 2. Here, in a power module equipped with a diode, since chips are operated in parallel, if a chip whose cross point is higher than the rated current density is mounted, current is concentrated on the chip, making it difficult to control the parallel operation. Therefore, the diode of the present embodiment that can suppress the increase of the cross point is effective.

以上説明したように、トレンチ３を設けることにより、Ｐ型アノード層の不純物濃度を低くしても耐圧の低下を防ぐことができる。従って、Ｐ型アノード層の不純物濃度によるＶＦ−Ｅｒｅｃトレードオフ制御が可能になる。よって、ライフタイム制御を行う必要が無いため、ライフタイム制御によるクロスポイントの増加も防ぐことができる。   As described above, by providing the trench 3, it is possible to prevent the breakdown voltage from being lowered even if the impurity concentration of the P-type anode layer is lowered. Therefore, VF-Erec trade-off control based on the impurity concentration of the P-type anode layer is possible. Therefore, since it is not necessary to perform lifetime control, it is possible to prevent an increase in cross points due to lifetime control.

図１０〜図１４は、アノード側の各設計パラメータによる電気特性への影響をシミュレーションした結果である。図１５は、図１１及び図１３のシミュレーションに用いた回路及びその回路のパラメータを示す図である。   10 to 14 show the results of simulating the influence of each design parameter on the anode side on the electrical characteristics. FIG. 15 is a diagram showing a circuit used in the simulations of FIGS. 11 and 13 and parameters of the circuit.

図１０は、トレンチの深さと耐圧ＢＶｒｒｍの関係を示す図である。トレンチ３の深さがＰＮ接合部の深さ（１．６６μｍ）より浅くなるとトレンチ３によるフィールドプレート効果がなくなり、耐圧が低下する。従って、トレンチ３の深さをＰＮ接合部よりも深くする必要がある。   FIG. 10 is a diagram showing the relationship between the depth of the trench and the breakdown voltage BVrrm. If the depth of the trench 3 is shallower than the depth of the PN junction (1.66 μm), the field plate effect by the trench 3 is lost and the breakdown voltage is lowered. Therefore, it is necessary to make the depth of the trench 3 deeper than that of the PN junction.

図１１は、アノード幅及びトレンチ幅とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆの関係を示す図である。アノード幅は、（トレンチ３のピッチ）−（トレンチ３の幅×２）である。アノード幅が一定でトレンチ３の幅を大きくすると、アノード電極７のコンタクト面積が減少する。従って、キャリアのパスが狭まるため、リカバリー動作終端（電流が０になる直前）でもトレンチ３の間には多くのキャリアが存在し、トレンチ３の幅が小さい場合と比べて電流の変化が大きくなる。スナップオフ電圧Ｖｓｎａｐ−ｏｆｆは電流の変化率に依存して増加するため、発振特性が悪化する。従って、トレンチ３の幅を１．２μｍ以下にする必要がある。なお、アノード幅は発振特性に影響を与えないため、任意の値に設計してよい。   FIG. 11 is a diagram illustrating the relationship between the anode width and the trench width and the snap-off voltage Vsnap-off. The anode width is (pitch of trench 3) − (width of trench 3 × 2). When the anode width is constant and the width of the trench 3 is increased, the contact area of the anode electrode 7 is reduced. Therefore, since the carrier path is narrowed, many carriers exist between the trenches 3 even at the end of the recovery operation (immediately before the current becomes 0), and the change in current becomes larger than when the width of the trench 3 is small. . Since the snap-off voltage Vsnap-off increases depending on the rate of change of current, the oscillation characteristics deteriorate. Therefore, the width of the trench 3 needs to be 1.2 μm or less. Since the anode width does not affect the oscillation characteristics, it may be designed to an arbitrary value.

図１２は、Ｎ型バッファ層６の不純物濃度とオン電圧ＶＦの関係を示す図である。図１３は、Ｎ型バッファ層６の不純物濃度とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆの関係を示す図である。Ｎ型バッファ層６の不純物濃度を高くすると、オン電圧ＶＦが上昇し、スナップオフ電圧Ｖｓｎａｐ−ｏｆｆが増加する。従って、Ｎ型バッファ層６の不純物濃度を１×１０１７ｃｍ−３以下にする必要がある。また、Ｎ型バッファ層６は、Ｎ型バッファ層６中のキャリアの再結合をコントロールして、リカバリー動作時の逆回復電流Ｉｒｒを低下させる効果を持つ。Ｎ型バッファ層６の不純物濃度が高いほど、その効果は大きくなる。 FIG. 12 is a diagram showing the relationship between the impurity concentration of the N-type buffer layer 6 and the ON voltage VF. FIG. 13 is a diagram showing the relationship between the impurity concentration of the N-type buffer layer 6 and the snap-off voltage Vsnap-off. When the impurity concentration of the N-type buffer layer 6 is increased, the ON voltage VF increases and the snap-off voltage Vsnap-off increases. Therefore, the impurity concentration of the N-type buffer layer 6 needs to be 1 × 10 17 cm −3 or less. Further, the N-type buffer layer 6 has an effect of controlling the recombination of carriers in the N-type buffer layer 6 and reducing the reverse recovery current Irr during the recovery operation. The higher the impurity concentration of the N-type buffer layer 6, the greater the effect.

図１４は、Ｐ＋型コンタクト層８が有る場合と無い場合におけるＰ型アノード層の不純物濃度とオン電圧の関係を示す図である。本実施の形態のダイオードでは、トレンチ３を設けたため、アノード電極７との接触面積が小さい。従って、Ｐ＋型コンタクト層８が無いとオン電圧ＶＦが上昇するため、Ｐ＋型コンタクト層８を設ける必要がある。 FIG. 14 is a diagram showing the relationship between the impurity concentration of the P-type anode layer and the on-voltage when the P + -type contact layer 8 is present and absent. In the diode of the present embodiment, since the trench 3 is provided, the contact area with the anode electrode 7 is small. Therefore, if the P + -type contact layer 8 is not provided, the on-voltage VF increases, so that it is necessary to provide the P + -type contact layer 8.

図１６は、本発明の実施の形態１に係る半導体装置を示す上面図である。図１７は、比較例１に係る半導体装置を示す上面図である。比較例１のようにコンタクト部全領域にわたってＰ＋型コンタクト層８を形成すると、アノード電極７からのホール注入がＰ＋型コンタクト層８の不純物濃度によって決定され、Ｐ型アノード層２の不純物濃度によるＶＦ−Ｅｒｅｃトレードオフ特性制御ができなくなる。そこで、本実施の形態のようにＰ＋型コンタクト層８の幅を適切に設計する必要がある。 FIG. 16 is a top view showing the semiconductor device according to the first embodiment of the present invention. FIG. 17 is a top view showing a semiconductor device according to Comparative Example 1. FIG. When the P + -type contact layer 8 is formed over the entire contact portion as in Comparative Example 1, hole injection from the anode electrode 7 is determined by the impurity concentration of the P + -type contact layer 8, and the impurity concentration of the P-type anode layer 2 VF-Erec trade-off characteristic control due to is impossible. Therefore, it is necessary to appropriately design the width of the P + -type contact layer 8 as in the present embodiment.

また、本実施の形態では、ダイオードのカソード側にＰ型カソード層１０を設けている。これにより、リカバリー動作時に、Ｐ型カソード層１０からホールが注入され、カソードのキャリア密度の急激な低下を抑制し、スナップオフ電圧Ｖｓｎａｐ−ｏｆｆを低下させることができる。従って、発振耐量を向上させることができる。   In the present embodiment, the P-type cathode layer 10 is provided on the cathode side of the diode. Thereby, holes are injected from the P-type cathode layer 10 during the recovery operation, and a rapid decrease in the carrier density of the cathode can be suppressed, and the snap-off voltage Vsnap-off can be reduced. Therefore, the oscillation tolerance can be improved.

続いて、本発明の実施の形態１に係る半導体装置の製造方法の効果について比較例２と比較して説明する。図１８，１９は比較例２に係る半導体装置の製造方法を示す断面図である。比較例２では、図１８に示すように、Ｎ−型ドリフト層１の下面全面にＰ型カソード層１０を形成する。次に、図１９に示すように、マスク１３を用いてＮ−型ドリフト層１の下面の一部の領域にＮ＋型カソード層９を選択的に形成する。 Next, the effect of the method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described in comparison with Comparative Example 2. 18 and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to Comparative Example 2. In Comparative Example 2, as shown in FIG. 18, the P-type cathode layer 10 is formed on the entire lower surface of the N − -type drift layer 1. Next, as shown in FIG. 19, an N + type cathode layer 9 is selectively formed in a partial region of the lower surface of the N − type drift layer 1 using a mask 13.

図２０〜図２２は、Ｐ型カソード層１０の形成プロセスや不純物濃度と電気特性との関係を測定した結果である。ここで、図２１及び図２２における測定条件は、電源電圧Ｖｃｃが２５００Ｖ、電流密度Ｊｃが０．７×定格電流密度、浮遊インダクタンスＬｓが４．６μＨ、リカバリー動作開始時の電流密度変化率ｄｊ／ｄｔが１３５０Ａ／μｓｅｃ・ｃｍ−２である。 20 to 22 show the results of measuring the formation process of the P-type cathode layer 10 and the relationship between the impurity concentration and the electrical characteristics. Here, the measurement conditions in FIGS. 21 and 22 are that the power supply voltage Vcc is 2500 V, the current density Jc is 0.7 × the rated current density, the floating inductance Ls is 4.6 μH, and the current density change rate dj / at the start of the recovery operation. The dt is 1350 A / μsec · cm −2 .

図２０は、本発明の実施の形態１と比較例２に係る製造方法によりそれぞれ製造したダイオードのリーク電流密度Ｊｒｒｍを示す図である。比較例２ではリーク電流が増加して耐圧が低下する。従って、実施の形態１のようにＰ型カソード層１０とＮ＋型カソード層９をそれぞれ選択的に形成して、互いの影響を受けないようにする必要がある。 FIG. 20 is a diagram showing the leakage current density Jrrm of the diodes manufactured by the manufacturing methods according to Embodiment 1 and Comparative Example 2 of the present invention. In Comparative Example 2, the leakage current increases and the breakdown voltage decreases. Therefore, it is necessary to selectively form the P-type cathode layer 10 and the N + -type cathode layer 9 as in the first embodiment so as not to be affected by each other.

図２１は、Ｐ型カソード層のドーズ量とスナップオフ電圧Ｖｓｎａｐ−ｏｆｆとの関係を示す図である。図２２は、Ｐ型カソード層のドーズ量とリカバリー動作時のオフ時間ｔｒｒとの関係を示す図である。Ｐ型カソード層１０のドーズ量が高いほど、スナップオフ電圧Ｖｓｎａｐ−ｏｆｆ抑制効果が高くなる。ただし、ドーズ量が高すぎるとリカバリー動作時のオフ時間ｔｒｒが長くなり、リカバリー耐量の低下につながる。従って、Ｐ型カソード層１０のドーズ量を１×１０１３〜１×１０１４ｃｍ−３の範囲にする必要がある。 FIG. 21 is a diagram illustrating the relationship between the dose amount of the P-type cathode layer and the snap-off voltage Vsnap-off. FIG. 22 is a diagram showing the relationship between the dose amount of the P-type cathode layer and the off time trr during the recovery operation. The higher the dose amount of the P-type cathode layer 10, the higher the snap-off voltage Vsnap-off suppression effect. However, if the dose amount is too high, the off time trr during the recovery operation becomes long, leading to a reduction in recovery tolerance. Therefore, the dose of the P-type cathode layer 10 needs to be in the range of 1 × 10 13 to 1 × 10 14 cm −3 .

図２３は、本発明の実施の形態１に係る半導体装置の変形例を示す断面図である。このようにＰ型カソード層１０を設けない場合でも、上述のトレンチ構造の効果は得ることができる。   FIG. 23 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention. Thus, even when the P-type cathode layer 10 is not provided, the above-described effect of the trench structure can be obtained.

図２４は、本発明の実施の形態１に係る半導体装置の変形例を示す断面図である。このようにカソード側のＮバッファ層が均一な濃度であっても、前述のＰ型カソード層によるスナップオフ電圧Ｖｓｎａｐ−ｏｆｆ抑制の効果を得ることができる。   FIG. 24 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention. Thus, even when the N buffer layer on the cathode side has a uniform concentration, the effect of suppressing the snap-off voltage Vsnap-off by the P-type cathode layer can be obtained.

なお、本実施の形態では３３００Ｖクラス以上の耐圧クラスのデバイスを例にとって説明したが、３３００Ｖ未満の耐圧クラスにおいても同様な効果を得ることができる。   In this embodiment, a device having a withstand voltage class of 3300 V class or higher has been described as an example. However, a similar effect can be obtained even with a withstand voltage class of less than 3300 V.

実施の形態２．
図２５は、本発明の実施の形態２に係る半導体装置を示す断面図である。ダイオードの有効領域の外側に終端領域が設けられている。有効領域において、Ｎ−型ドリフト層１上の一部にＰ型アノード層２，１５が設けられている。Ｐ型アノード層２にアノード電極７が接続されている。Ｐ型アノード層２，１５の外端部とアノード電極７との間に絶縁膜１６が設けられている。終端領域において、Ｎ−型ドリフト層１の外端部にチャネルストッパ１７が設けられている。終端領域上に絶縁膜１８が設けられている。 Embodiment 2. FIG.
FIG. 25 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. A termination region is provided outside the effective region of the diode. P-type anode layers 2 and 15 are provided in part on the N − -type drift layer 1 in the effective region. An anode electrode 7 is connected to the P-type anode layer 2. An insulating film 16 is provided between the outer ends of the P-type anode layers 2 and 15 and the anode electrode 7. A channel stopper 17 is provided at the outer end of the N − -type drift layer 1 in the termination region. An insulating film 18 is provided on the termination region.

図２６は、長さＬａｂｒとチップ内最大温度の関係をシミュレーションした結果を示す図である。図２７は、図２６のシミュレーションに用いた回路及びその回路のパラメータを示す図である。長さＬａｂｒは、Ｐ型アノード層２の外端と絶縁膜１６の内端との間の長さである。絶縁膜１６を有効領域側に伸ばすことで、アノード有効領域の端部に抵抗成分が形成される。   FIG. 26 is a diagram illustrating a result of simulating the relationship between the length Labr and the maximum temperature in the chip. FIG. 27 is a diagram illustrating a circuit used in the simulation of FIG. 26 and parameters of the circuit. The length Labr is a length between the outer end of the P-type anode layer 2 and the inner end of the insulating film 16. By extending the insulating film 16 toward the effective region, a resistance component is formed at the end of the anode effective region.

リカバリー動作時、終端領域内の残留キャリアはアノード有効領域の端部に集中しコンタクトを通して外部回路に抜けていく。この際に大きな電流が流れて温度上昇を引き起こす。従って、長さＬａｂｒが小さいと、狭い範囲で温度が急激に上昇し、熱によってリカバリー破壊が起こる。そこで、本実施の形態では、Ｐ型アノード層２の外端と絶縁膜１６の内端との間の長さＬａｂｒを１００μｍ以上にする。これにより、抵抗成分で熱が分散化し温度上昇を抑制することができる。   During the recovery operation, residual carriers in the termination region concentrate on the end of the anode effective region and escape to the external circuit through the contact. At this time, a large current flows, causing a temperature rise. Therefore, when the length Labr is small, the temperature rises rapidly in a narrow range, and recovery destruction occurs due to heat. Therefore, in the present embodiment, the length Labr between the outer end of the P-type anode layer 2 and the inner end of the insulating film 16 is set to 100 μm or more. Thereby, heat is dispersed by the resistance component, and the temperature rise can be suppressed.

図２８は、ダイオードのリカバリーＳＯＡ（Safety Operation Area）を示す図である。リカバリーＳＯＡとは、ダイオードの動作を保証する電源電圧Ｖｃｃと電流密度Ｊｃとの関係を示したものである。本実施の形態のようにアノード有効領域の端部に抵抗成分を設けることにより、リカバリー耐量を図中の破線で示したように向上させることができる。   FIG. 28 is a diagram showing a diode recovery SOA (Safety Operation Area). The recovery SOA indicates the relationship between the power supply voltage Vcc that guarantees the operation of the diode and the current density Jc. By providing a resistance component at the end of the anode effective region as in the present embodiment, the recovery tolerance can be improved as shown by the broken line in the figure.

図２９は、本発明の実施の形態２に係る半導体装置の変形例を示す断面図である。終端領域においてＰ型カソード層１０が設けられている。この場合でも本発明の効果を得ることができる。これに限らず、アノード有効領域、カソード有効領域、又はカソード終端領域がどのような構造でも、本発明の効果を得ることができる。   FIG. 29 is a sectional view showing a modification of the semiconductor device according to the second embodiment of the present invention. A P-type cathode layer 10 is provided in the termination region. Even in this case, the effect of the present invention can be obtained. The present invention is not limited to this, and the effect of the present invention can be obtained with any structure of the anode effective region, the cathode effective region, or the cathode termination region.

１ Ｎ−型ドリフト層
２，１５ Ｐ型アノード層
３ トレンチ
４，１６ 絶縁膜
５ 導電性物質
６ Ｎ型バッファ層
９ Ｎ＋型カソード層
７ アノード電極
１０ Ｐ型カソード層 1 N − type drift layer 2, 15 P type anode layer 3 Trench 4, 16 Insulating film 5 Conductive material 6 N type buffer layer 9 N + type cathode layer 7 Anode electrode 10 P type cathode layer

Claims (5)

Ｎ型ドリフト層と、
前記Ｎ型ドリフト層上に設けられたＰ型アノード層と、
前記Ｐ型アノード層を貫通するトレンチと、
前記トレンチ内に絶縁膜を介して埋め込まれた導電性物質と、
前記Ｎ型ドリフト層と前記Ｐ型アノード層の間に設けられ、前記Ｎ型ドリフト層よりも高い不純物濃度を持つＮ型バッファ層とを備えることを特徴とする半導体装置。 An N-type drift layer;
A P-type anode layer provided on the N-type drift layer;
A trench penetrating the P-type anode layer;
A conductive material embedded in the trench through an insulating film;
A semiconductor device comprising: an N-type buffer layer provided between the N-type drift layer and the P-type anode layer and having a higher impurity concentration than the N-type drift layer. 前記トレンチの幅を１．２μｍ以下にすることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a width of the trench is 1.2 μm or less. 前記Ｎ型バッファ層の不純物濃度を１×１０１７ｃｍ−３以下にすることを特徴とする請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1, wherein an impurity concentration of the N-type buffer layer is 1 × 10 17 cm −3 or less. Ｎ型ドリフト層の上面にＰ型アノード層を形成する工程と、
前記Ｎ型ドリフト層の下面の第１の領域にＮ＋型カソード層を選択的に形成する工程と、
前記Ｎ型ドリフト層の下面の前記第１の領域とは異なる第２の領域にＰ型カソード層を選択的に形成する工程とを備えることを特徴とする半導体装置の製造方法。 Forming a P-type anode layer on the upper surface of the N-type drift layer;
Selectively forming an N + type cathode layer in a first region of the lower surface of the N type drift layer;
And a step of selectively forming a P-type cathode layer in a second region different from the first region on the lower surface of the N-type drift layer. Ｎ型ドリフト層と、
前記Ｎ型ドリフト層上の一部に設けられたＰ型アノード層と、
前記Ｐ型アノード層に接続されたアノード電極と、
Ｐ型アノード層の外端部と前記アノード電極との間に設けられた絶縁膜とを備え、
前記Ｐ型アノード層の外端と前記絶縁膜の内端との間の長さが１００μｍ以上であることを特徴とする半導体装置。 An N-type drift layer;
A P-type anode layer provided in part on the N-type drift layer;
An anode electrode connected to the P-type anode layer;
An insulating film provided between an outer end of a P-type anode layer and the anode electrode;
A semiconductor device, wherein a length between an outer end of the P-type anode layer and an inner end of the insulating film is 100 μm or more.
JP2011050995A 2011-03-09 2011-03-09 Semiconductor device and method of manufacturing the same Pending JP2012190873A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2011050995A JP2012190873A (en) 2011-03-09 2011-03-09 Semiconductor device and method of manufacturing the same
US13/237,309 US20120228700A1 (en) 2011-03-09 2011-09-20 Semiconductor device and method for manufacturing the same
DE102011089452.7A DE102011089452B4 (en) 2011-03-09 2011-12-21 semiconductor device
KR1020120022160A KR101329613B1 (en) 2011-03-09 2012-03-05 Semiconductor device and method for manufacturing the same
CN201210071923.7A CN102683427B (en) 2011-03-09 2012-03-07 Semiconductor device and manufacture method thereof
US14/336,800 US9202936B2 (en) 2011-03-09 2014-07-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011050995A JP2012190873A (en) 2011-03-09 2011-03-09 Semiconductor device and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015034040A Division JP6065035B2 (en) 2015-02-24 2015-02-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2012190873A true JP2012190873A (en) 2012-10-04

Family

ID=46705499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011050995A Pending JP2012190873A (en) 2011-03-09 2011-03-09 Semiconductor device and method of manufacturing the same

Country Status (5)

Country Link
US (2) US20120228700A1 (en)
JP (1) JP2012190873A (en)
KR (1) KR101329613B1 (en)
CN (1) CN102683427B (en)
DE (1) DE102011089452B4 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014154849A (en) * 2013-02-13 2014-08-25 Toshiba Corp Semiconductor device
JP2016062926A (en) * 2014-09-12 2016-04-25 株式会社東芝 Semiconductor device
JP2016100464A (en) * 2014-11-21 2016-05-30 三菱電機株式会社 Reverse conducting type semiconductor device
JP2016162897A (en) * 2015-03-02 2016-09-05 株式会社豊田中央研究所 Diode and reverse conduction igbt incorporating the diode

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064887B2 (en) * 2012-09-04 2015-06-23 Infineon Technologies Austria Ag Field-effect semiconductor device and manufacturing method therefor
US8710585B1 (en) * 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US9634128B2 (en) 2014-03-17 2017-04-25 Kabushiki Kaisha Toshiba Semiconductor device
JP7077648B2 (en) * 2017-02-16 2022-05-31 富士電機株式会社 Semiconductor device
JP6643382B2 (en) 2017-03-20 2020-02-12 インフィニオン テクノロジーズ オーストリア アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｕｓｔｒｉａ ＡＧ Power semiconductor device
DE102017105895B4 (en) 2017-03-20 2019-07-04 Infineon Technologies Austria Ag Surge protection power semiconductor device
EP3948956A1 (en) * 2019-04-02 2022-02-09 Hitachi Energy Switzerland AG Segmented power diode structure with improved reverse recovery

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004519100A (en) * 2001-02-03 2004-06-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Bipolar diode
JP2004186413A (en) * 2002-12-03 2004-07-02 Toshiba Corp Semiconductor device
JP2010283132A (en) * 2009-06-04 2010-12-16 Mitsubishi Electric Corp Semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969400A (en) * 1995-03-15 1999-10-19 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
JP3409503B2 (en) 1995-05-22 2003-05-26 株式会社日立製作所 Diode, diode driving method, and semiconductor circuit
JP3444081B2 (en) * 1996-02-28 2003-09-08 株式会社日立製作所 Diode and power converter
JPH1093113A (en) 1996-09-19 1998-04-10 Hitachi Ltd Diode
JP4351745B2 (en) 1997-09-19 2009-10-28 株式会社東芝 Semiconductor device
JP4017258B2 (en) * 1998-07-29 2007-12-05 三菱電機株式会社 Semiconductor device
JP2000299476A (en) 1999-04-15 2000-10-24 Toshiba Corp Semiconductor device
JP3968912B2 (en) 1999-05-10 2007-08-29 富士電機デバイステクノロジー株式会社 diode
JP4678077B2 (en) 1999-07-21 2011-04-27 株式会社豊田中央研究所 diode
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP2006210667A (en) * 2005-01-28 2006-08-10 Mitsubishi Electric Corp Semiconductor device
JP5617175B2 (en) * 2008-04-17 2014-11-05 富士電機株式会社 Wide band gap semiconductor device and manufacturing method thereof
JP4743447B2 (en) * 2008-05-23 2011-08-10 三菱電機株式会社 Semiconductor device
JP5003598B2 (en) 2008-06-05 2012-08-15 富士電機株式会社 Semiconductor device
JP5607720B2 (en) * 2010-02-23 2014-10-15 良孝 菅原 Semiconductor device
JP5434961B2 (en) * 2010-08-04 2014-03-05 株式会社デンソー Semiconductor device having lateral diode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004519100A (en) * 2001-02-03 2004-06-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Bipolar diode
JP2004186413A (en) * 2002-12-03 2004-07-02 Toshiba Corp Semiconductor device
JP2010283132A (en) * 2009-06-04 2010-12-16 Mitsubishi Electric Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014154849A (en) * 2013-02-13 2014-08-25 Toshiba Corp Semiconductor device
JP2016062926A (en) * 2014-09-12 2016-04-25 株式会社東芝 Semiconductor device
JP2016100464A (en) * 2014-11-21 2016-05-30 三菱電機株式会社 Reverse conducting type semiconductor device
JP2016162897A (en) * 2015-03-02 2016-09-05 株式会社豊田中央研究所 Diode and reverse conduction igbt incorporating the diode

Also Published As

Publication number Publication date
DE102011089452A1 (en) 2012-09-13
DE102011089452B4 (en) 2022-05-25
KR101329613B1 (en) 2013-11-15
CN102683427B (en) 2015-08-05
US20120228700A1 (en) 2012-09-13
US20140327072A1 (en) 2014-11-06
CN102683427A (en) 2012-09-19
KR20120103459A (en) 2012-09-19
US9202936B2 (en) 2015-12-01

Similar Documents

Publication Publication Date Title
JP2012190873A (en) Semiconductor device and method of manufacturing the same
CN109964317B (en) Semiconductor device with a plurality of semiconductor chips
JP6459791B2 (en) Semiconductor device and manufacturing method thereof
JP5256357B2 (en) Semiconductor device
US10170607B2 (en) Semiconductor device
JP6181597B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2010283132A (en) Semiconductor device
US20170222029A1 (en) Semiconductor device
WO2014199465A1 (en) Semiconductor apparatus
JP6662393B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2014160841A (en) Method for producing semiconductor device structure
JP2017208413A (en) Semiconductor device
JP2014053409A (en) Mos semiconductor device
JPWO2014087543A1 (en) Manufacturing method of semiconductor device
JP6750668B2 (en) Semiconductor device
JP2020155581A (en) Semiconductor device
JP6065035B2 (en) Semiconductor device
CN104779279A (en) RC-IGBT (reverse-conducting insulated gate bipolar translator) capable of inhibiting snapback effect
JP6739659B2 (en) Semiconductor device
JP2008147318A (en) High breakdown strength semiconductor device, and manufacturing method thereof
CN105830220B (en) The manufacturing method of semiconductor device
WO2018230312A1 (en) Semiconductor device
JP2010206111A (en) Semiconductor device
JP2008182032A (en) Semiconductor device
JP2021174796A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130612

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140610

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140714

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20150113