JPH0758783B2 - Conduction modulation type MOSFET - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a conductive modulation type semiconductor device used as a power switching element.

[Prior art and its problems]

In recent years, an element called an insulated gate transistor or a conductive modulation type MOSFET has attracted attention as a power switching element. The basic structure of this element is shown in FIG.

It can be said that this structure replaces the n ⁺ layer, which is the drain region of the power MOSFET called vertical DMOS, with the p ⁺ layer. That is, a low impurity concentration on the p ⁺ substrate 1 (first layer)
An n ⁻ layer 2 is formed, a p layer region 3 is selectively formed on the surface of the n ⁻ layer 2, and an n ⁺ layer region 4 is selectively formed on the surface of the p layer 3 to form ap layer. A surface region sandwiched by the n ⁻ layer 2 and the n ⁺ layer region 4 in the region 3 is used as a channel forming region 11, and a gate electrode 6 is formed on the surface forming region 11 via a gate insulating film 5. Then, the short-circuited source electrode 7 is formed so as to straddle the p layer region 3 and the n ⁺ layer region 4, and the drain electrode 8 is formed on the surface of the p ⁺ substrate (first layer) 1. The operation of this element is as follows.

When the source electrode 7 is grounded and a positive voltage is applied to the gate electrode 6 and the drain electrode 8, p just below the gate electrode 6
Since the surface portion of the layer region 3 is inverted to form an n-type channel (not shown), an electron current flows from the source to the drain through this channel. At this time, drain side p ⁺
Due to the so-called conductivity modulation effect caused by the injection of holes, which is a minority carrier, from the layer 1 to the n ^- layer 2, the n ^- layer 2
Lower the resistance in the area. Although this element provides such a low on-resistance in the on state, on the other hand, since the phenomenon of latching is likely to occur due to its parasitic pnpn structure, the n ⁺ source region 4 and the p-layer region 3 are conventionally used as electrodes on the surface. Although a short circuit was made to prevent latching from occurring, the holes accumulated in the n ⁻ layer 2 flow laterally in the p layer region 3 particularly at turn-off to promote injection of electrons from the n ⁺ source region 4 and parasitic effect. There was a problem that the thyristor was latched. The reason will be described below.

FIG. 4 shows an equivalent circuit of this element.

There are two parasitic transistors Tr1 and Tr2 in this element. In the thyristor made up of Tr1 and Tr2, the sum of the current amplification factor α _{1 of} Tr1 and the current amplification factor α ₂ of Tr2 is α ₁ + α ₂ ≧ 1
When it hits, it will be latched. When the parasitic thyristor will be Ratsuchingu current p ⁺ n other than channel region ^- can not current controlled by the gate voltage flows through the in the region of the p layer region 3 of the pn ⁺ layer portion from the through connexion the drain to the source. In order to prevent such a phenomenon from occurring easily, it is effective to reduce the resistance Rb in FIG. By lowering the resistance Rb, it is possible to make α ₂ small and to make the device hard to be latched. For that purpose, it is effective to make the p-layer region 3 have a high impurity concentration to reduce the resistance of the lateral current. However, if the channel region is made to have a high impurity concentration, the gate threshold voltage rises and the on-resistance rises. Is also big. As a method for solving this, a structure shown in FIG. 5 has already been proposed. According to this, by forming the p ⁺ layer region 9 so as not to cover the channel forming region 11, the resistance Rb, that is, the n ⁺ layer region 4 without increasing the impurity concentration of the channel forming region 11.
The lateral resistance of the underlying p-layer region can be reduced.

However, with this method, the distance between the p layer region 3 and the p ⁺ layer region 9 is limited due to the precision of photoetching, and therefore it cannot be made so small, and there is a limit to the reduction of the lateral resistance Rb.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a conduction modulation type MOSFET which eliminates the above-mentioned drawbacks and enables a sufficiently large latching current while maintaining a low gate threshold voltage and a low ON voltage.

[Main points of the invention]

The present invention focuses on the fact that, in the equivalent circuit of the conductivity modulation type MOSFET, if the lateral resistance Rb is lowered, a high latching current that makes it difficult for the parasitic thyristor to ratchet occurs can be obtained. By evenly eliminating the holes accumulated in the nearby n ^- high resistance layer from the periphery of the channel, the current density at which these holes would have flowed through the p region under the source region is reduced, which Thus, the lateral resistance Rb is reduced to prevent the parasitic thyristor from being latched.

To this end, the present invention provides a conductivity modulation type MOSFET including a first layer of one conductivity type with a high impurity concentration, a second layer of another conductivity type with a low impurity concentration in contact with one surface of the first layer, and a second layer of the other conductivity type. It has a base layer region of one conductivity type selectively formed on the surfaces of the two layers and a source layer region of another conductivity type selectively formed on the surface of the base layer region. A drain electrode is formed on the surface and a second electrode is formed adjacent to the base layer region.
In order to form a channel region near the surface of the base layer region sandwiched between the layer surface and the source layer region, a gate electrode is provided on this region via an insulating film, and the base layer region and the source layer region are formed. A source electrode short-circuited to each other is provided on the region, one conductivity type high impurity concentration region surrounding the channel region at equal intervals is provided, and the one conductivity type high impurity concentration region is provided on the one conductivity type high impurity concentration region. The above object is achieved by providing an electrode having the same potential as the source electrode.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings. The same reference numerals in the respective drawings indicate common points.

FIG. 1 is a sectional view of an essential part of an embodiment of the same electric modulation type MOSFET of the present invention, and FIG. 2 is an equivalent circuit of FIG. In the present invention, similar to the structure of the device shown in FIG. 3, the p ⁺ layer 1 is provided with a high resistance n ⁻ layer 2 in contact with the layer 1 and p layer regions 3 and n ⁺ source regions 4. Further, as in the case shown in FIG. 5, a high concentration p ⁺ region 9 formed to overlap the p-layer region 3 except the channel forming region 11 and a high resistance n ⁻ outside the channel forming region 11.
On the surface of layer 2, the p ⁺ region is equally spaced from and surrounds region 11.
By providing 10, the transistor Tr3 in the equivalent circuit shown in FIG. 2 is formed. The transistor Tr3 is composed of the p ⁺ layer 1, the n ⁻ layer 2 and the p ⁺ layer 10 in FIG. This transistor Tr3 passes from the source through the channel forming region 11 to n
^- electron current flowing through the layer 2 as a base current, hole current injected from the p ⁺ layer 1 is operated by flowing through the p ⁺ region 10.

Due to the existence of such a transistor Tr3, the holes accumulated in the n ⁻ layer 2 at the time of turn-off are eliminated through the p ⁺ layer 10, so that the hole current density in the vicinity of the channel forming region 11 is reduced. As a result, the hole current flowing in the p layer 3 and the p ⁺ layer 9 in the lateral direction is reduced, and the voltage drop due to the lateral resistance Rb can be reduced. For this reason, it is considered that the latching phenomenon is unlikely to occur.

Since the structure of the channel forming region 11 of the device structure shown in FIG. 1 is the same as the conventional structure, no demerit such as increase of the gate threshold voltage occurs. Further, since the drain current also flows in the p ⁺ region 10, the on-state voltage can be further reduced. Further, the p ⁺ region 10 is arranged so as to surround the hole at the same distance from the channel region 11 for the purpose of uniformly eliminating the holes accumulated in the n ⁻ layer 2 from the periphery of the channel. Further, the p ⁺ region 10 is required to be connected to the source electrode 7 at the same potential on the electrode in order to exert its effect.

〔The invention's effect〕

According to the present invention, in the structure of the conductivity modulation type MOSFET, the high impurity concentration region surrounding the channel region is formed at equal intervals, and the electrode on the region is connected to the same potential as the source electrode. , Evenly eliminating holes accumulated in the n ^- high resistance layer near the channel from the periphery of the channel enables a sufficiently large latching current while maintaining a low gate threshold voltage and a low on-voltage, that is, parasitic It is possible to make the thyristor latch less likely to occur.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a conductivity modulation type MOSFET showing an embodiment of the present invention, FIG. 2 is a view showing an equivalent circuit of FIG. 1, and FIG. 3 is a cross section of a main part of a conventional conductivity modulation type MOSFET. Fig. 4 and Fig. 3
Fig. 5 is an equivalent circuit diagram, and Fig. 5 is a conventional different conductivity modulation type MOSF.
FIG. 3 is a cross-sectional view of a main part of ET. 1 ... First layer (p ⁺ substrate), 2 ... Second layer (n ^- layer), 3 ...
… P base layer region, 4 …… n ⁺ source layer region, 5 …… insulating film, 6 …… gate electrode, 7 …… source electrode, 8 …… drain electrode, 9 …… p ⁺ region, 10 …… p ⁺ Region, 11 …… Channel formation region.

Claims (1)

[Claims] 1. A first layer of one conductivity type having a high impurity concentration,
A second layer of low conductivity and another conductivity type in contact with one surface of the first layer, one conductivity type base layer region selectively formed on the surface of the second layer, and the base layer region A source layer region of another conductivity type selectively formed on the surface of the first layer, a drain electrode is formed on the other surface of the first layer, and the second layer surface adjacent to the base layer region and the source layer region. In the vicinity of the surface of the base layer region sandwiched between and, in order to form a channel region, an insulating film is formed on this region,
A gate electrode is provided, source electrodes that are in short-circuit contact with each other are provided on the base layer region and the source layer region, and one conductivity type high impurity concentration region that surrounds the channel region at equal intervals is provided, and A conductivity modulation type MOSFET characterized in that an electrode having the same potential as the source electrode is provided on one of the conductivity type high impurity concentration regions.