JP2817147B2 - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JP2817147B2 JP2817147B2 JP26538588A JP26538588A JP2817147B2 JP 2817147 B2 JP2817147 B2 JP 2817147B2 JP 26538588 A JP26538588 A JP 26538588A JP 26538588 A JP26538588 A JP 26538588A JP 2817147 B2 JP2817147 B2 JP 2817147B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- region
- base region
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に伝導度変調型電界効
果トランジスタに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a conductivity modulation type field effect transistor.
従来の伝導度変調型電界効果トランジスタを第３図に
基づいて説明する。従来の伝導度変調型電界効果トラン
ジスタは、第１導電型の半導体層１上に第２導電型の低
濃度層３を有する半導体基板の表面部に互いに離れて設
けられた第１導電型ベース領域４とこのベース領域４内
に設けられた第２導電型ソース領域５及びこのソース領
域５の相互間の半導体基板上にゲート酸化膜６を介して
設けられたポリシリコンによるゲート電極７を有し、ソ
ース領域５及び基板下部より、それぞれソース電極8,ド
レイン電極９を有し、下部第１導電型半導体層１は基板
と平行である。A conventional conductivity modulation type field effect transistor will be described with reference to FIG. A conventional conductivity-modulated field-effect transistor includes a first conductivity type base region which is provided apart from each other on a surface portion of a semiconductor substrate having a second conductivity type low concentration layer 3 on a first conductivity type semiconductor layer 1. 4, a second conductivity type source region 5 provided in the base region 4 and a gate electrode 7 made of polysilicon provided on the semiconductor substrate between the source regions 5 with a gate oxide film 6 interposed therebetween. A source electrode 8 and a drain electrode 9 from the source region 5 and the lower part of the substrate, respectively, and the lower first conductivity type semiconductor layer 1 is parallel to the substrate.
上述した従来の伝導度変調型電界効果トランジスタに
おいて、ゲート電極７に正の電圧を加えるとゲート電極
７直下のＰベース領域４の表面が反転しｎチャネルが生
じる。ｎチャネルが生じるとn+ソース領域５、−ｎチャ
ネル−n-層３−p+ドレイン層１からなるPINダイオード
と同一の構造が形成されていると考えられるようにな
る。そしてn+ソース領域５よりN-層３にｎチャネルを介
して電子が流入し、N-層３の電位を下げる。従って、こ
のPINダイオードが順バイアスされてp+ドレイン層１か
らホールが注入される。このように、n-層３はp+ドレイ
ン層１から注入されたホールとソース領域５から注入さ
れた電子が蓄積し導伝変調をうけ、オン抵抗が低下す
る。In the conventional conductivity-modulated field effect transistor described above, when a positive voltage is applied to the gate electrode 7, the surface of the P base region 4 immediately below the gate electrode 7 is inverted, and an n-channel is generated. When the n-channel is generated, it can be considered that the same structure as the PIN diode including the n + source region 5 and the -n channel -n - layer 3-p + drain layer 1 is formed. Then N from n + source region 5 - electrons flows through the n-channel in the layer 3, N - lowering the potential of the layer 3. Therefore, the PIN diode is forward-biased and holes are injected from the p + drain layer 1. As described above, the n − layer 3 is subjected to conduction modulation due to accumulation of holes injected from the p + drain layer 1 and electrons injected from the source region 5, and the ON resistance is reduced.
このとき、ホールは矢印11,12で示したような通路を
経てベース領域４に集められ、ソース電極５にぬけ出て
いく。そして、大電流駆動となった場合、素子の電流密
度が高くなりソース領域５の下のＰベース層４に存在す
る抵抗成分13のためにこの部分を通る時に電圧降下が生
じる。この電圧降下によりこの部分のn+ソース領域５と
Ｐベース領域４との間のPN接合を順バイアスする結果と
なるので、この電圧降下が高いと電子は直接ソース領域
５よりＰベース領域４中へ注入され寄生NPNトランジス
タがオンし寄生サイリスタのラッチアップが生じてしま
う。At this time, the holes are collected in the base region 4 through the passages indicated by arrows 11 and 12, and pass through the source electrode 5. In the case of driving with a large current, the current density of the element increases, and a voltage drop occurs when passing through this portion due to the resistance component 13 existing in the P base layer 4 below the source region 5. This voltage drop results in a forward biasing of the PN junction between the n + source region 5 and the P base region 4 in this part, so that if this voltage drop is high, electrons will be more directly in the P base region 4 than in the source region 5. And the parasitic NPN transistor is turned on, causing latch-up of the parasitic thyristor.
本発明の目的はラッチアップを生じにくく大電流を駆
動させることのできる伝導度変調型電界効果トランジス
タを提供することである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a conductivity modulation type field effect transistor which does not easily cause latch-up and can drive a large current.
本発明によれば、第１導電型の半導体層上に第２導電
型の低濃度層を有する半導体基板の表面部に互いに離れ
て設けられた第１導電型ベース領域とこのベース領域内
に設けられた第２導電型ソース領域及びこのソース領域
の相互間の半導体基板上にゲート酸化膜を介して設けら
れたポリシリコンによるゲート電極を有し、ソース領域
及び基板下部よりそれぞれソース電極，ドレイン電極を
有する伝導度変調型電界効果トランジスタにおいて、ベ
ース領域直下では基板表面から第１導電型層までの距離
を短く形成した電界効果トランジスタを得る。According to the present invention, a first conductivity type base region is provided on a surface portion of a semiconductor substrate having a second conductivity type low-concentration layer on a first conductivity type semiconductor layer and is provided in the base region. A second conductive type source region and a polysilicon gate electrode provided on the semiconductor substrate between the source regions via a gate oxide film, and a source electrode and a drain electrode from the source region and the lower portion of the substrate, respectively. A field effect transistor having a short distance from the substrate surface to the first conductivity type layer immediately below the base region.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示したもので、伝導度変
調型電界効果トランジスタの断面図である。第１図にお
いて第１導電型の半導体層１上に第２導電型の低濃度層
３を有する半導体基板の表面部に互いに離れて設けられ
た第１導電型ベース領域４とこのベース領域内に設けら
れた第２導電型ソース領域５及びこのソース領域の相互
間の前記半導体基板上にゲート酸化膜６を介して設けら
れたポリシリコンによるゲート電極７を有しソース領域
５及び基板下部よりソース電極8,ドレイン電極９を有し
ている。そして本実施例においては、ベース領域４のソ
ース領域５の囲まれた部分の直下において、第１導電型
層１上に第１導電型層10を設け、この部分における第１
導電型層とベース領域４との距離を短くしている。FIG. 1 shows an embodiment of the present invention and is a cross-sectional view of a conductivity modulation type field effect transistor. In FIG. 1, a first conductivity type base region 4 is provided on a surface portion of a semiconductor substrate having a second conductivity type low-concentration layer 3 on a first conductivity type semiconductor layer 1 and separated from each other. The semiconductor device has a second conductivity type source region 5 provided and a gate electrode 7 made of polysilicon provided on the semiconductor substrate via a gate oxide film 6 between the source regions. It has an electrode 8 and a drain electrode 9. In this embodiment, the first conductivity type layer 10 is provided on the first conductivity type layer 1 immediately below the portion of the base region 4 surrounded by the source region 5, and the first conductivity type layer 10 in this portion is provided.
The distance between the conductive layer and the base region 4 is reduced.
伝導度変調型電界効果トランジスタのオン状態では前
述したように、P+領域１からN-領域３への正孔の注入が
生じ非常に低いオン抵抗を有するが、電流が大きくなる
につれベース領域４のソース領域５直下の抵抗13による
電圧降下が無視できなくなりベース領域４の電位を上昇
せしめ寄生NPNトランジスタがオンしてしまいラッチア
ップが生じる。そこでこのベース領域４直下、特に、ソ
ース領域５に囲まれたベース領域４の下に第１導電型層
10を設け、基板表面からの距離を短くすることにより
（通常10〜100μｍ程度）、ベース抵抗13による電圧降
下に寄与しない部分のみホールの注入効率を上げその他
の部分は逆に注入効率を下げる。このようにしてオン抵
抗の増大を抑制しつつラッチアップ耐量の増大を図るこ
とができる。In the on state of the conductivity modulation type field effect transistor, as described above, holes are injected from the P + region 1 to the N − region 3 and have a very low on-resistance, but as the current increases, the base region 4 The voltage drop due to the resistor 13 immediately below the source region 5 cannot be ignored and the potential of the base region 4 rises, turning on the parasitic NPN transistor and causing latch-up. Therefore, the first conductivity type layer is provided directly under the base region 4, in particular, under the base region 4 surrounded by the source region 5.
By providing 10 and shortening the distance from the substrate surface (usually about 10 to 100 μm), the hole injection efficiency is increased only in the portion that does not contribute to the voltage drop due to the base resistor 13, and the injection efficiency is reduced in the other portions. In this way, it is possible to increase the latch-up resistance while suppressing the increase in the on-resistance.
すなわち、抵抗部分13を経る通路12を流れるホールの
量を小さくしこの抵抗13を経ない通路11を流れるホール
の量を多くすることによってオン電圧の上昇を防止しラ
ッチアップ耐量を向上させる。そのためには通路12の第
１導電層からベース４までの距離を長く、通路11の第１
導電層からベース４までの距離を短くしN-領域３中での
ホールの再結合割合を制御する。N-領域３の距離が長け
ればホールの再結合の割合は大きく短かければ再結合の
割合は小さいので、同一の構造で同一電流の場合、P+層
（１）が平坦な従来の場合と比較して通路11を経て流れ
るホールの量は多く、通路12を経て流れるホールの量は
少なくなり、内部抵抗13が存在する部分の電圧降下が小
さくなってPN接合が順バイアスされにくくなる結果、ラ
ッチアップで生じにくくなる。That is, by reducing the amount of holes flowing through the passage 12 passing through the resistor portion 13 and increasing the amount of holes flowing through the passage 11 not passing through the resistor 13, an increase in on-voltage is prevented and the latch-up resistance is improved. To do so, the distance from the first conductive layer of the passage 12 to the base 4 is increased, and the first
The distance from the conductive layer to the base 4 is reduced to control the recombination ratio of holes in the N − region 3. N - the ratio of recombination by multiplying the recombination rate of the large short hole Longer distance region 3 is small, if the same current with the same structure, and if the P + layer (1) is flat prior In comparison, the amount of holes flowing through the passage 11 is large, the amount of holes flowing through the passage 12 is small, the voltage drop in the portion where the internal resistance 13 exists is small, and the PN junction is less likely to be forward biased, Latch-up is less likely to occur.
第２図は本発明の他の実施例の断面図である。第１導
電型の半導体層１上に第２導伝型の高濃度層２さらに低
濃度層３を有する半導体基板の表面部に互いに離れて設
けられた第一導伝型ベース領域４とベース領域４内に設
けられた第二導電型ソース領域５及びソース領域５の間
の半導体基板上にゲート酸化膜６を介して設けられたポ
リシリコンによるゲート電極７を有し前記ソース領域５
及び基板下部よりソース電極８ドレイン電極９を有して
いる。FIG. 2 is a sectional view of another embodiment of the present invention. A first conductive type base region 4 and a base region provided on a surface portion of a semiconductor substrate having a second conductive type high-concentration layer 2 and a low-concentration layer 3 on a first conductive type semiconductor layer 1 and separated from each other. And a gate electrode 7 made of polysilicon provided on a semiconductor substrate between the source region 5 and the source region 5 with a gate oxide film 6 interposed therebetween.
And a source electrode 8 and a drain electrode 9 from below the substrate.
この実施例では基板内に数μｍから20μｍ程度の高濃
度層２を有している。この層の存在により少数キャリア
の注入効率が下がるためラッチアップ耐量が増加し、タ
ーンが時間が短くなりスイッチングスピードが速くなる
という利点がある。In this embodiment, the substrate has a high concentration layer 2 of about several μm to about 20 μm. The presence of this layer has the advantage that the injection efficiency of minority carriers is reduced, the latch-up withstand capability is increased, the turn time is shortened, and the switching speed is increased.
以上説明したように本発明は、ベース領域下では基板
表面から第一導電型層までの距離を短くすることにより
ラッチ耐量を増加させることができる。As described above, according to the present invention, the latch resistance can be increased by shortening the distance from the substrate surface to the first conductivity type layer under the base region.
第１図は本発明による伝導度変調型電界効果トランジス
タの第１の実施例の断面図、第２図は本発明の第２の実
施例の断面図、第３図は従来の伝導度変調型電界効果ト
ランジスタの断面図である。 1,10……第一導電型層、２……高濃度第二導電型層、３
……低濃度第二導電型層、４……ベース領域、５……ソ
ース領域、６……ゲート酸化膜、７……ゲート電極、８
……ソース電極、９……ドレイン電極。FIG. 1 is a cross-sectional view of a first embodiment of a conductivity modulation type field effect transistor according to the present invention, FIG. 2 is a cross-sectional view of a second embodiment of the present invention, and FIG. It is sectional drawing of a field effect transistor. 1,10 ... first conductivity type layer, 2 ... high concentration second conductivity type layer, 3
... Low-concentration second-conductivity-type layer, 4. Base region, 5 Source region, 6 Gate oxide film, 7 Gate electrode, 8
... source electrode, 9 ... drain electrode.
Claims (1)
濃度層を有する半導体基板の表面部に互いに離れて設け
られた第１導電型ベース領域と該ベース領域内に設けら
れた第２導電型ソース領域及び該ソース領域の間の前記
基板上にゲート酸化膜を介して設けられたゲート電極を
有し前記ソース領域及び基板下部よりそれぞれソース電
極、ドレイン電極を有する電界効果トランジスタにおい
て、該ベース領域直下の前記第１導電型の半導体層上に
更に第１導電型の凸部領域を設けたことを特徴とした電
界効果トランジスタ。A first conductive type base region provided on a surface portion of a semiconductor substrate having a second conductive type low-concentration layer on a first conductive type semiconductor layer, and a first conductive type base region provided in the base region; A field effect transistor having a second conductivity type source region and a gate electrode provided on the substrate between the source region via a gate oxide film, and having a source electrode and a drain electrode below the source region and the substrate, respectively. 3. The field effect transistor according to claim 1, further comprising a first conductivity type convex region provided on the first conductivity type semiconductor layer immediately below the base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26538588A JP2817147B2 (en) | 1988-10-20 | 1988-10-20 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26538588A JP2817147B2 (en) | 1988-10-20 | 1988-10-20 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02111074A JPH02111074A (en) | 1990-04-24 |
| JP2817147B2 true JP2817147B2 (en) | 1998-10-27 |
Family
ID=17416442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26538588A Expired - Lifetime JP2817147B2 (en) | 1988-10-20 | 1988-10-20 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2817147B2 (en) |
-
1988
- 1988-10-20 JP JP26538588A patent/JP2817147B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02111074A (en) | 1990-04-24 |
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