JP3114317B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an MO having a high withstand voltage, low on-resistance and excellent turn-off characteristics.
The present invention relates to a semiconductor device in which SFETs are integrated.

[0002]

2. Description of the Related Art A conventional semiconductor device, for example, a power bipolar transistor has a structure as shown in FIG. 10, and the structure thereof will be described.
A low concentration N-type epitaxial layer 2 is formed on the surface. Base region 3 having a predetermined concentration and thickness is formed on the surface of epitaxial layer 2, and high concentration N-type emitter region 5 is formed at a predetermined position on the surface of base region 3. Emitter region 5 is connected to emitter electrode 7 via polycrystalline Si emitter lead-out region 6. The base region 3 is connected to a base electrode 8 via a high-concentration base extraction region 4. The insulating layer 9 is formed to separate the base electrode 8 from the polycrystalline Si emitter extraction region 6. FIG. 10B is an equivalent circuit diagram when a plurality of the bipolar transistor cells shown in FIG. 10A are connected in parallel.

The operation will be described. When the bipolar transistor is off, a collector voltage is applied to the epitaxial layer 2. Since the epitaxial layer 2 has a low concentration and a sufficient thickness, the withstand voltage is high. Next, a case where a base current is supplied to turn on a bipolar transistor will be described. A large amount of holes are injected into the epitaxial layer 2 from the base region 3 or the high-concentration base extraction region 4, and the conductivity of the epitaxial layer 2 is modulated. As a result, the resistance of the epitaxial layer 2 decreases. Bipolar with particularly high breakdown voltage due to conductivity modulation effect
Transistors have lower on-resistance than MOSFETs with equivalent breakdown voltage.

FIG. 1 shows another example of a semiconductor device.
2 shows a cross section of a vertical power MOSFET, in which a low-concentration drift region 32 is formed on a high-concentration substrate 31, and a channel forming surface is formed at a predetermined position on the drift region 32 in accordance with a gate voltage. Body region 33 is formed, and source region 34 and body contact region 35 are formed at predetermined positions on body region 33. Further, a gate electrode 37 is formed on the surface of the body region 33 sandwiched between the low concentration drift region 32 and the source region 34 via a gate insulating film 36. The high concentration substrate 31 is connected to the drain electrode, and the source region 34 and the body contact region 35 are all connected to the source electrode.

Next, the operation will be described. When a gate voltage is applied, an inversion layer 38 serving as a channel is formed on the surface of the body region 33, and current flows from the drain electrode 31 → 32 →
It flows to the source electrode via 38 → 34. Accordingly, the on-resistance at this time decreases as the concentration of the low-concentration drift region 32 increases and as the thickness of the low-concentration drift region 32 decreases. However, if the concentration of the low concentration drift region 32 is increased or the thickness of the low concentration drift region 32 is reduced, the breakdown voltage between the drain and the source is reduced. Therefore, the on-resistance of a MOSFET having a predetermined withstand voltage cannot be reduced to a certain fixed value or less, and the on-resistance of the MOSFET increases when the withstand voltage is increased. For this reason, especially high-voltage MOSFET of several hundred V or more
Has not been put to practical use.

[0006]

The conventional power bipolar transistor has the following problems.

(A) As the temperature rises, the collector current increases and the power consumption also increases. As a result, there is a possibility that the temperature will further rise and local destruction due to current concentration will occur.

(B) When the bipolar transistor is turned off, the collector current flows until the holes accumulated in the epitaxial layer 2 recombine with the electrons and disappear, so that the turn-off time becomes longer.

Conventionally, in order to prevent the above-mentioned current concentration, a ballast resistor _RE is connected to the emitter, whereby the emitter potential of the bipolar transistor cell through which the current flows in a concentrated manner rises. And the base and collector currents decrease.
In the example shown in FIG.
The resistance acts as a ballast resistor R _E.

[0010] In order to improve the turn-off characteristics of the bipolar transistor, a circuit shown in FIG. 11 has been proposed. (For example, “MOS-Controlled Thyristors-A New Clas
s ofPower Devices ”, VAKTemple, IEEE-ED vol.33
No.10, Oct.1986, p.1609) The structure is
A low breakdown voltage power MOSFET 11 is connected in series to the emitter of the bipolar transistor 10 to form a cascode configuration. The operation of this configuration will be described. In the ON state, the bipolar transistor 10 and the low breakdown voltage power M
A current flows through the OSFET 11. The on-resistance of the bipolar transistor 10 is small due to the conductivity modulation effect.
Further, since the low breakdown voltage power MOSFET 11 may have a low breakdown voltage, the channel can be shortened, and the on-resistance can be designed to be sufficiently small. When the high withstand voltage power bipolar transistor 10 and the low withstand voltage power MOSFET 11 are turned off, the low withstand voltage power MOSFET 11 is turned off first, and as a result, no current can flow, and the turn-off time is shortened. In the off state, the withstand voltage is high because the emitter of the bipolar transistor 10 is floating.

The present invention relates to a high voltage power bipolar transistor 10 and a low voltage power MOSFET 1 shown in FIG.
A single cascode connection on the same semiconductor substrate to provide a configuration in which a parasitic device caused by the integration does not adversely affect the operation;
It is an object of the present invention to make the OSFET 11 work as a ballast resistor of the high withstand voltage power bipolar transistor 10, eliminate the need for the ballast resistor of the bipolar transistor 10, and simplify the configuration. FIG.
Another object of the present invention is to increase the breakdown voltage of the vertical power MOSFET as shown in FIG.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor substrate having a first conductivity type, and a base having a second conductivity type formed on one main surface of the semiconductor substrate. A region, a base extraction region and a first cathode region having the same conductivity type as the base region and independently formed in contact with the base region, respectively, and formed at predetermined locations in the base region; A high impurity concentration floating emitter region having a first conductivity type, a second cathode region, and a main surface of the base region sandwiched between the floating emitter region and the second cathode region via a gate insulating layer. A gate electrode connected to the high impurity concentration base extraction region, the first cathode region and the second cathode region. There composed of a cathode electrode which are both short-circuited. According to a second aspect of the present invention, there is provided a semiconductor substrate having a first conductivity type, a base region having a second conductivity type formed on one main surface of the semiconductor substrate, and a high impurity concentration having the same conductivity type as the base region. A base extraction region and a body contact region formed in contact with the base region, a source region having a high impurity concentration of a first conductivity type formed at a predetermined position in the base region, and one of the base region A gate electrode is formed on the main surface via a gate insulating film in contact with the source region, and a cathode electrode is formed by short-circuiting the body contact region and the source region.

[0013]

According to the first aspect of the present invention, a bipolar transistor cell is formed by a semiconductor substrate, an epitaxial layer, a base region, and a floating emitter region, and a floating emitter region, a second cathode region, and a gate electrode. A MOSFET cell is formed, and the base region is configured to also serve as a base region of the bipolar transistor cell and the MOSFET cell. Bipolar transistor cell and MOSFET
The integration of the cell allows the semiconductor substrate, the epitaxial layer, the first
A parasitic diode is constituted by the cathode region of the semiconductor substrate, the epitaxial layer, the base region, and the second cathode region.
Two kinds of parasitic bipolar transistors are generated by the base region and the second cathode region.

When a voltage is applied to the gate electrode, the low voltage power MOSFET cell is turned on, and a current flows from the base electrode, the high voltage bipolar transistor cell is turned on and current flows to the anode and the cathode. At this time, the parasitic bipolar transistor Is lower than the potential of the bipolar transistor cell and the parasitic bipolar
If the base resistance of the transistor is small enough, none of the parasitic bipolar transistors can be turned on. At turn-on, current flows through the power bipolar transistor cell and the MOSFET cell. The on-resistance of the bipolar transistor cell has a small resistance value due to the conductivity modulation effect. Since the on-resistance of the MOSFET cell is small, the overall on-resistance is also small. Also, MOS
Because the emitter of the FET cell is connected to the bipolar transistor cell, the bipolar transistor cell acts as an emitter ballast resistor for the MOSFET cell to mitigate current crowding effects.

When the application of the base current and the gate voltage is stopped, the bipolar transistor cell MOSFET cell is turned off. Due to the slow turn-off of the bipolar transistor cell, first the MOSFET cell is turned off. When the MOSFET cell is turned off due to the flow through the bipolar transistor cell and the MOSFET cell, no current can flow, and the turn-off time as a whole is short.

The parasitic diode does not affect the characteristics during normal operation. During abnormal operation when the potential of the cathode becomes higher than the potential of the anode, the parasitic diode conducts current by acting as a flywheel diode, so that a high voltage is not applied to the MOSFET cell and the MOSFET cell is protected from destruction due to the high voltage. I do.

Further, according to the second invention, a base region and a base extraction region are newly provided so that the inversion layer of the MOSFET substantially functions as an emitter and is connected to the body region, and minority carriers are injected from the base and the base extraction region. This modulates the conductivity of the low concentration drift region.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing a first embodiment of the present invention,
First, the structure will be described. A low-concentration N-type epitaxial layer 2 is formed on a high-concentration N-type semiconductor substrate 1, and a P-type base region 3 having a predetermined concentration and thickness is formed on the epitaxial layer 2. A high concentration N-type floating emitter region 12 and an N + cathode region 14 are provided at predetermined locations on the base region 3.
Are formed. On the surface of P type base region 3 between floating emitter region 12 and N + cathode region 14, gate polycrystalline Si film 15 is formed via gate insulating film insulating layer 16. The P + base region 3 is connected to the base electrode 8 via the high-concentration P-type base extraction region 4 and to the cathode electrode 17 via the P + cathode region 13. Cathode electrode 17 is insulating layer 1
6 and is insulated from the gate polycrystalline Si film 15 by N +.
It is connected to the cathode region 14.

The features of the above configuration are summarized as follows. (A) The floating emitter region 12 is not directly connected to an external terminal.

(B) Floating emitter region 12
Is an N + NPN + bipolar transistor cell 1 comprising a semiconductor substrate 1, an epitaxial layer 2, a base region 3, and a floating emitter region 12.
At the same time as constituting the emitters 9, the drains also serve as the drains of the low breakdown voltage power MOSFET cell 20 constituted by the floating emitter region 12, the gate polycrystalline Si film 15, and the N + cathode region 14.

(C) The base region 3 is a base region of the high withstand voltage power bipolar transistor cell 19 and also a base region of the low withstand voltage power MOSFET cell 20.

(D) The P + cathode region 13 and the N + cathode region 14 are both connected to the cathode electrode 17.

FIG. 1 (b) is an equivalent circuit diagram of FIG. 1 (a). FIG. 1B also shows a parasitic device caused by the integration. That is, as a result of integrating the high withstand voltage power bipolar transistor cell 19 and the low withstand voltage power MOSFET cell 20, the parasitic diode 21 constituted by the semiconductor substrate 1, the epitaxial layer 2 and the P + cathode region 13, the semiconductor substrate 1, Layer 2,
A parasitic bipolar transistor 22a constituted by the base region 3 and the N + cathode region 14 and a parasitic bipolar transistor 22b constituted by the floating emitter region 12, the base region 3 and the N + cathode region 14 are generated. The base electrode 8 is connected to the cathode electrode 17 through the resistor R _1, which is constituted by the base region 3.

Next, the operation will be described. When a voltage is applied to the gate G to turn on the low withstand voltage power MOSFET cell 20 and a current flows from the base B, the high withstand voltage bipolar transistor cell 19 is turned on and current flows through the anode A and the cathode K. In this case the parasitic bipolar transistor 22a, the base potential of 22b is lower than the potential of the high voltage power bipolar transistor cell 19 by R _1, the parasitic bipolar transistor 22a, 22
If the base resistance of b is designed to be sufficiently small, both the parasitic bipolar transistors 22a and 22b cannot be turned on. Parasitic bipolar transistor 22
In order to reduce the base resistances of the transistors a and 22b, the impurity concentration of the P + cathode region 13 may be increased so as to diffuse deeply.

Therefore, at the time of turn-on, current always flows through the high-voltage power bipolar transistor cell 19 and the low-voltage power MOSFET cell 20. The on-resistance of the high withstand voltage power bipolar transistor cell 19 has a small resistance value due to the conductivity modulation effect, and the low withstand voltage power MOSF
Since the ON resistance of the ET cell 20 is small, the overall ON resistance is also small. In addition, the low-voltage power MOSFET cell 20
Is connected to the high withstand voltage power bipolar transistor cell 19, the high withstand voltage power bipolar transistor cell 19 is connected to the low withstand voltage power MOSFE.
It acts as an emitter ballast resistor of the T cell 20 and reduces the current concentration effect. Therefore, in the case of this structure, no other ballast resistor is required.

Next, when the application of the base current and the gate voltage is stopped, the high withstand voltage power bipolar transistor cell 19 and the low withstand voltage power MOSFET cell 20 are turned off. High voltage power bipolar transistor cell 1
9 has a slow turn-off, so first the low voltage power MOS
The FET cell 20 turns off. Since the current always flows through the high-voltage power bipolar transistor cell 19 and the low-voltage power MOSFET cell 20, the current cannot flow when the low-voltage power MOSFET cell 20 is turned off. Therefore, the turn-off time as a whole is short.

The parasitic diode 21 does not affect the above-mentioned characteristics during normal operation. During an abnormal operation in which the potential of the cathode K becomes higher than the potential of the anode A, the parasitic diode 21 causes a current to flow by acting as a flywheel diode.
The low-voltage power MOSFET cell 20 is not applied to the FET cell 20 and thus can be protected from destruction by a high voltage.

FIG. 2 is a diagram showing an embodiment of a plane layout pattern. In the case of this pattern, the high-concentration base extraction region 4, floating emitter region 12, N + cathode region 14, P + cathode region 13 and gate 15 all have a stripe shape. The cathode region 13 and the P + cathode region 14 are connected to the cathode electrode 17, and the high-concentration base extraction region 4 is connected to the base electrode 8.

FIG. 3 is an embodiment diagram of another planar layout pattern. This is one in which an N + cathode region 14 and a P + cathode region 13 are concentrically formed to form a cathode cell. The base extraction region 4 and the floating emitter region 12 are also arranged concentrically to form a base cell. The base cell is located at the center of the regular hexagon, and the cathode cells are located at each vertex of the regular hexagon. With this regular hexagonal arrangement, the circular cells can be arranged in the closest density, so that the on-resistance can be further reduced. Even in a regular hexagonal arrangement, FIG.
Conversely, a layout pattern in which a base cell is arranged at each vertex with the cathode cell as the center can also be applied as the application example of FIG.

As a planar layout pattern of the cathode electrode 17 and the base electrode 8, there is an embodiment using a finger pattern shown in FIG.

Furthermore, it is possible to arrange the cathode electrode 17 and the base electrode 8 by using a multilayer metal wiring technique. For example, FIG. 5 shows an embodiment in which metal wiring is performed in two layers. In this embodiment, the first metal layer 24 is used as the base electrode, and the first metal layer 24 and the second metal layer 26 are used as the cathode electrode. The cathode electrode and the base electrode are insulated by the interlayer insulating film 25. ing. As described above, by using the multi-layer metal wiring technique, the cathode cells and the base cells can be arranged more densely, so that the on-resistance can be further reduced as compared with the single-layer wiring.

FIG. 6 shows a second embodiment of the present invention. In this embodiment, a UMOS is integrated in each bipolar transistor cell. Also in this case, the floating emitter region 12 serves as the emitter of the bipolar transistor and also serves as the drain of the UMOSFET. The base region 3 serves as the base of the bipolar transistor and also serves as the base of the UMOSFET, and a channel of the UMOSFET is formed on the groove side surface of the base region 3. Further, one of the base regions 3 is connected to the cathode electrode 17 via the P + cathode region 13, and the other of the base regions 3 is connected to the base electrode 8 via the base extraction region 4. UMOS MOSFET
As a result, the surface MOS transistor shown in FIG.
It can be arranged more densely than in the case of FET. Further, when UMOS is used, the parasitic bipolar transistors 22a and 22b
Has the effect that the base resistance of the substrate can be easily reduced.

In the above embodiments, the structure in which the NPN-type bipolar transistor and the N-type MOSFET are integrated has been described. However, the present invention is applicable to the case where the PNP-type bipolar transistor and the P-type MOSFET are integrated. Can also be applied.

FIG. 7 is a view showing a third embodiment. First, the structure will be described. First, a low-concentration drift region 32 and a body region 3 are formed on a high-concentration substrate 31 similarly to the prior art shown in FIG.
3, a source region 34, a body contact region 35, a gate insulating film 36, and a gate electrode 7 are formed. Further, base region 39 is formed on the surface of low concentration drift region 32 so as to be connected to body region 33. Finally, a base extraction region 40 for connecting the base region 39 and the base external terminal is formed independently of the body region 33 and the body contact region 35.

In order to turn on the semiconductor device shown in FIG. 7, a gate voltage is applied, and a base current flows from the base electrode B. The inversion layer 38 changes the gate G by the gate voltage.
It is formed directly below. Since the inversion layer 38 functions as a substantial emitter of the bipolar transistor consisting of the high-concentration substrate 31, the drift region 32, the base region 39, and the inversion layer 38, a bipolar transistor is formed immediately below the gate.
The base transistor turns on the bipolar transistor formed immediately below the gate G near the base extraction region side, and a current flows from the drain D to the source electrode through the bipolar transistor and the inversion layer 38. At this time, minority carriers are injected into the drift region 32 by the base current, and the conductivity of the drift region 32 is modulated. As a result, the resistance of the drift region 32 decreases, and the on-resistance of the semiconductor device has the same withstand voltage as the MOSFET.
Smaller than.

At this time, the base of the bipolar transistor formed immediately below the gate G near the body contact region 35 side or the parasitic bipolar transistor constituted by the substrate 31 → the drift region 32 → the body region 33 → the source region 34 -These bipolar transistors cannot be turned on because they are short-circuited to the source region 34 serving as the emitter via the contact region 35. As a result, the current flowing between the drain D and the source S of the semiconductor device always flows through the inversion layer 38. When the temperature rises, the resistance of the inversion layer 38 increases,
The current flowing through the semiconductor device decreases. Therefore, in this case, unlike the bipolar transistor, the current does not concentrate on the temperature rising part and the local destruction does not occur.

FIG. 8 shows the body region 3 of the embodiment shown in FIG.
4 shows a cross-sectional view of the fourth embodiment in which 3 is omitted. In this case, the operation is similar to that of FIG.
It becomes smaller than T.

FIG. 9 is a diagram showing a fifth embodiment. In this embodiment, the gate electrode of the embodiment shown in FIG. 8 is formed in a groove. In the case of this structure, the parasitic bipolar transistor constituted by the substrate 31, the drift region 32, the base region 39, and the source region 34 is harder to turn on than that of the structure shown in FIG.

[0039]

As described above, according to the first aspect, the structure is such that the emitter of each bipolar transistor cell is made to be floating, and the floating emitter is made to be the drain of the MOSFET cell (the carrier suction port).
The base of the bipolar transistor and the base of the MOSFET in which the channel is formed on the surface thereof are constituted by a common region.
Since the source (carrier supply source) of the T cell is short-circuited and connected to the cathode electrode, the bipolar transistor and the MOSFET are cascode-connected monolithically, and the parasitic bipolar transistor cannot be turned on. Therefore, the turn-off characteristics can be improved, the structure is simplified because the MOSFET cell acts as a ballast resistor, and the flywheel diode can be integrated between the anode and the cathode at the same time. Further, according to the second aspect, the structure is such that a base region and a base extraction region are provided adjacent to the body contact region or the body region, a base current flows from the base extraction region, and the inversion layer of the MOSFET operates substantially as an emitter. As a result, minority carriers are injected into the drift region by the base current, the conductivity of the drift region is modulated, and the effect that the on-resistance can be made smaller than that of a MOSFET having the same withstand voltage can be obtained.

[Brief description of the drawings]

FIG. 1A is a diagram of a first embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram thereof.

FIG. 2 is a diagram showing an embodiment of a planar layout pattern of the present invention.

FIG. 3 is a diagram showing another embodiment of the planar layout pattern of the present invention.

FIG. 4 is a diagram showing an embodiment of an electrode layout using a finger pattern according to the present invention.

FIG. 5 is a diagram using a two-layer metal wiring in the first embodiment of the present invention.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a third embodiment of the present invention.

FIG. 8 is a diagram showing a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a conventional power bipolar transistor.

FIG. 11 shows a power bipolar transistor and a MOS.
It is a conventional circuit configuration diagram in which FETs are cascode-connected.

FIG. 12 is a diagram showing another conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Epitaxial layer 3
... Base area 4 ... High concentration base extraction area 5
... Emitter region 6 ... Polycrystalline Si emitter extraction region 7
... Emitter electrode 8 ... Base electrode 9 ... Insulating layer R _E ... Emitter ballast resistance 10 ... High voltage power bipolar transistor 11 ... Low voltage power MOSFET 12 ... Floating emitter region 13 ... P + cathode region 14 ... N + cathode region 1
5 gate polycrystalline Si film 16 insulating layer 17 cathode electrode 1
Reference Signs List 8: base electrode 19: high withstand voltage power bipolar transistor cell 20: low withstand voltage power MOSFET cell 21: parasitic diode 22: parasitic bipolar transistor 23: contact hole 24: first metal layer 2
5 Interlayer insulating layer 26 Second metal layer 31 High-concentration substrate 32 Low-concentration drift region 33 Body region 34 Source region 35 Body contact region 3
6 gate insulating film 37 gate electrode 38 inversion layer 3
9 Base area 40 Base extraction area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 656

Claims (2)

(57) [Claims] A semiconductor substrate having a first conductivity type; a base region having a second conductivity type formed on one principal surface of the semiconductor substrate; and a base region formed independently of and in contact with the base region. A high impurity concentration base extraction region and a first cathode region having the same conductivity type as the base region; a high impurity concentration floating emitter region having a first conductivity type and formed at a predetermined location in the base region; A second cathode region, a gate electrode formed on one main surface of the base region sandwiched between the floating emitter region and the second cathode region via a gate insulating layer, and a base extraction region having a high impurity concentration. A connected base electrode; and a cathode electrode in which the first cathode region and the second cathode region are short-circuited together. A semiconductor device characterized by the above-mentioned. 2. A semiconductor substrate having a first conductivity type, a base region having a second conductivity type formed on one principal surface of the semiconductor substrate, and a high impurity concentration having the same conductivity type as the base region. A base extraction region and a body contact region formed in contact with the base region; a source region having a high impurity concentration of a first conductivity type formed at a predetermined position in the base region; and one main surface of the base region A semiconductor device, comprising: a gate electrode formed thereon via a gate insulating film in contact with the source region; and a cathode electrode in which the body contact region and the source region are short-circuited together.