JP2903452B2 - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JP2903452B2 JP2903452B2 JP5162469A JP16246993A JP2903452B2 JP 2903452 B2 JP2903452 B2 JP 2903452B2 JP 5162469 A JP5162469 A JP 5162469A JP 16246993 A JP16246993 A JP 16246993A JP 2903452 B2 JP2903452 B2 JP 2903452B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- divided
- base
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 description 34
- 230000003071 parasitic effect Effects 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、スイッチング電源など
に使用されるパワー用縦型の電界効果トランジスタ（以
下、ＦＥＴと称する）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical power field effect transistor (hereinafter referred to as "FET") used for a switching power supply or the like.
【０００２】[0002]
【従来の技術】パワー用縦型ＦＥＴは、例えば図３
（ａ）（ｂ）に示す構造が一般的である。図３（ａ）は
ｎチャネル型の縦型ＦＥＴの断面が示され、ドレイン領
域ＤとなるＮ型の半導体基板（1）の表面側にＰ型のベ
ース領域ＢとＮ+型のソース領域Ｓが不純物選択拡散で
形成され、半導体基板（1）の表面上にゲート酸化膜
（2）、ゲート電極Ｇ、層間絶縁膜（3）、ゲート電極パ
ターン（4）、ソース電極パターン（5）が形成される。2. Description of the Related Art A vertical power FET is shown in FIG.
The structures shown in (a) and (b) are general. FIG. 3A shows a cross section of an n-channel type vertical FET, in which a P-type base region B and an N + -type source region S are formed on the surface side of an N-type semiconductor substrate (1) serving as a drain region D. Are formed by impurity selective diffusion, and a gate oxide film (2), a gate electrode G, an interlayer insulating film (3), a gate electrode pattern (4), and a source electrode pattern (5) are formed on the surface of the semiconductor substrate (1). Is done.
【０００３】半導体基板（1）は、例えばＮ+型サブスト
レート（1'）上にＮ-型エピタキシャル成長層（1"）を
積層したもので、エピタキシャル成長層（1"）の表層部
に複数のベース領域Ｂが所定の配列ピッチと形状、例え
ば図３（ｂ）に示すように、同一サイズの略正方形のも
のが、縦横に定ピッチで碁盤の目配列で形成される。各
ベース領域ＢにＮ+型不純物を選択拡散してソース領域
Ｓが形成され、各ソース領域Ｓの中央部を貫通させてベ
ースコンタクト領域Ｂａが形成される。ベース領域Ｂの
外周とソース領域Ｓの外周の間にソース・ドレイン導通
用チャネル部Ｃが形成される。A semiconductor substrate (1) is, for example, a structure in which an N − type epitaxial growth layer (1 ″) is laminated on an N + type substrate (1 ′), and a plurality of bases are provided on a surface portion of the epitaxial growth layer (1 ″). The area B has a predetermined arrangement pitch and shape, for example, as shown in FIG. 3B, a substantially square one having the same size is formed in a grid pattern at a constant pitch vertically and horizontally. A source region S is formed by selectively diffusing an N + -type impurity into each base region B, and a base contact region Ba is formed so as to penetrate a central portion of each source region S. A source / drain conduction channel portion C is formed between the outer periphery of the base region B and the outer periphery of the source region S.
【０００４】半導体基板（1）の隣接するベース領域Ｂ
間とチャネル部Ｃ上にゲート酸化膜（2）が形成され、
その上にゲートポリシリコンのゲート電極Ｇが形成され
る。ゲート電極Ｇを覆うように層間絶縁膜（3）が形成
され、最後にアルミニウムの配線パターンであるゲート
電極パターン（4）とソース電極パターン（5）が形成さ
れる。A base region B adjacent to a semiconductor substrate (1)
A gate oxide film (2) is formed between and on the channel portion C,
A gate electrode G of gate polysilicon is formed thereon. An interlayer insulating film (3) is formed so as to cover the gate electrode G, and finally, a gate electrode pattern (4) and a source electrode pattern (5), which are aluminum wiring patterns, are formed.
【０００５】ゲート電極Ｇに正電圧を印加すると、チャ
ネル部ＣがＮ型に反転してソース領域Ｓとドレイン領域
Ｄ間が導通し、ソース領域Ｓからチャネル部Ｃを経てド
レイン領域Ｄに縦型の電子流Ｉｄが流れる。このとき、
ドレイン領域Ｄは不純物濃度が低く、電子流Ｉｄの導通
抵抗が大きくなるため、予め基板の極表面付近に高濃度
のＮ型不純物領域を薄く形成したものもある。When a positive voltage is applied to the gate electrode G, the channel portion C is inverted to N-type, and conduction between the source region S and the drain region D is established. Electron flow Id flows. At this time,
Since the drain region D has a low impurity concentration and a high conduction resistance of the electron current Id, a thin high-concentration N-type impurity region is formed in advance near the extreme surface of the substrate.
【０００６】[0006]
【発明が解決しようとする課題】図３（ａ）のＦＥＴに
おいては、ソース領域Ｓとベース領域Ｂ及びドレイン領
域Ｄの間で、図３（ｃ）に示されるような寄生トランジ
スタＱが形成される。この寄生トランジスタＱのエミッ
タとベース間は、ソース領域Ｓの真下のベース領域Ｂ内
に形成された拡散抵抗（ベース抵抗）Ｒａで電気的接続
される。拡散抵抗Ｒａは、ソース領域Ｓの真下のベース
領域Ｂが薄く、かつ、不純物濃度が低いために大きく
て、平均値は１０００Ω／□を超えている。In the FET shown in FIG. 3A, a parasitic transistor Q as shown in FIG. 3C is formed between the source region S, the base region B and the drain region D. You. The emitter and the base of the parasitic transistor Q are electrically connected by a diffusion resistance (base resistance) Ra formed in the base region B immediately below the source region S. The diffusion resistance Ra is large because the base region B immediately below the source region S is thin and has a low impurity concentration, and the average value exceeds 1000Ω / □.
【０００７】ベース領域Ｂの拡散抵抗Ｒａの平均値が大
きくなるほど、小さいベース電流で寄生トランジスタＱ
にベース・エミッタ間電圧が生じてコレクタ電流が流れ
易くなる。そこで、ソース・ドレイン間が導通から遮断
する瞬間にインダクタンス負荷（Ｌ負荷）で高い衝撃電
圧が加わると、ドレイン電流と異なる不所望な寄生コレ
クタ電流が流れて、トランジスタ素子が破壊に到る不具
合が生じることがある。このような不具合の発生率は、
拡散抵抗Ｒａの平均値が大きく、Ｌ負荷耐量が小さくな
るほど高い。つまり、１０００Ω／□を超える拡散抵抗
Ｒａのある現状のＦＥＴにおいては、ベース電圧オフ時
に寄生トランジスタＱがオンし易くて、Ｌ負荷耐量が小
さく、寄生コレクタ電流で破壊される確率が高い問題が
あった。As the average value of the diffusion resistance Ra in the base region B increases, the parasitic transistor Q
, A base-emitter voltage is generated and the collector current easily flows. Therefore, when a high impact voltage is applied with an inductance load (L load) at the moment when the source-drain is cut off from conduction, an undesirable parasitic collector current different from the drain current flows, and the transistor element is damaged. May occur. The incidence of such defects is
The larger the average value of the diffusion resistance Ra is, the higher the L load withstand capacity becomes. That is, in the current FET having a diffusion resistance Ra exceeding 1000 Ω / □, there is a problem that the parasitic transistor Q is easily turned on when the base voltage is off, the L load tolerance is small, and the probability of being destroyed by the parasitic collector current is high. Was.
【０００８】また、ソース領域Ｓの中心にベースコンタ
クト領域Ｂａを目合わせして形成しているが、目合わせ
時の目ずれでソース領域Ｓの中心とベースコンタクト領
域Ｂａの中心がずれ、例えば図３（ｂ）の鎖線に示すよ
うに、ベースコンタクト領域Ｂａがソース領域Ｓの中心
部から外れることがある。このように目ずれを起こす
と、ソース領域Ｓの真下のベース領域Ｂのベースコンタ
クト領域Ｂａを中心とする放射方向での拡散抵抗値分布
が、目ずれをした図３（ｂ）のｍ側より反対のｎ側で高
くなり、拡散抵抗Ｒａの最大値が増大して、上記不具合
の発生率を尚更に高くしていた。Further, the base contact region Ba is aligned with the center of the source region S, but the center of the source region S and the center of the base contact region Ba are shifted due to misalignment at the time of alignment. 3B, the base contact region Ba may deviate from the center of the source region S. When such misalignment occurs, the diffusion resistance distribution in the radial direction centering on the base contact region Ba of the base region B immediately below the source region S becomes closer to the misaligned m-side in FIG. On the other hand, it becomes higher on the n side, and the maximum value of the diffusion resistance Ra is increased, thereby further increasing the occurrence rate of the above-mentioned problem.
【０００９】本発明の目的は、ベース領域の実質上の拡
散抵抗を下げてＬ負荷耐量を大きくしたパワー用縦型Ｆ
ＥＴを提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to reduce the substantial diffusion resistance of the base region to increase the L load withstand capability.
To provide ET.
【００１０】[0010]
【課題を解決するための手段】本発明は、ドレイン領域
となる一導電型半導体基板の表面の所定領域に他導電型
不純物を選択拡散して形成した略正方形のベース領域の
中央部分に、同ベース領域と異なる一導電型不純物を選
択拡散して形成される全体が略正方形のソース領域が、
幅狭で一定幅の他導電型ソース分割ベース領域により略
４等分に分割された４分割ソース領域である構造にて、
上記目的を達成するものである。According to the present invention, there is provided a semiconductor device having a substantially square base region formed by selectively diffusing impurities of another conductivity type into a predetermined region on the surface of a semiconductor substrate serving as a drain region. A source region having a substantially square shape formed by selectively diffusing one conductivity type impurity different from the base region,
Narrow, constant width, other conductivity type
In a structure that is a four-divided source region divided into four equal parts ,
The above object is achieved.
【００１１】上記ソース領域は、具体的には対角線で４
等分されていてもよい。 [0011] Specifically, the source region has a diagonal line of 4
It may be equally divided.
【００１２】[0012]
【作用】ソース領域を複数に分割し、分割された複数の
分割ソース領域間をベース領域にしておくと、分割ソー
ス領域間のベース領域での拡散抵抗がソース領域真下の
ベース領域の拡散抵抗より大幅に小さくなり、この小さ
な拡散抵抗の存在でベース領域全体の実質上の拡散抵抗
が減少して、寄生トランジスタがオンし難くなり、Ｌ負
荷耐量を大きくすることが可能となる。When a source region is divided into a plurality of divided source regions and the base region is set between the divided source regions, the diffusion resistance in the base region between the divided source regions is smaller than the diffusion resistance of the base region immediately below the source region. The diffusion resistance is greatly reduced, and the substantial diffusion resistance of the entire base region is reduced due to the presence of the small diffusion resistance, so that the parasitic transistor is hardly turned on, and the L load tolerance can be increased.
【００１３】[0013]
【実施例】本発明の図３のパワー用縦型のＦＥＴに適用
した実施例を、図１（ａ）（ｂ）及び図２を参照して説
明する。なお、図１と図２の各実施例の図３と同一、又
は、相当部分には同一符号を付して、説明は省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a vertical power FET shown in FIG. 3 will be described with reference to FIGS. 1 (a) and 1 (b) and FIG. The same reference numerals are given to the same or corresponding parts as in FIG. 3 of each embodiment of FIGS. 1 and 2, and the description is omitted.
【００１４】図１（ａ）（ｂ）に示されるように、本発
明は１ベース領域Ｂに形成されるソース領域Ｓを複数に
分割したことを特徴とする。図１の実施例のソース領域
Ｓは、全体が略正方形であり、その各辺の中央と直交す
る十文字状の分割線で互いに離隔させて４等分された４
分割ソース領域Ｓ'…で構成される。各分割ソース領域
Ｓ'…間は、分割ソース領域Ｓ'…の真下のベース領域Ｂ
と同一の十文字状のソース分割ベース領域Ｂ'である。
ソース分割ベース領域Ｂ'は半導体基板（1）の表面に露
呈して、その十文字中央部がベースコンタクト領域Ｂａ
となる。As shown in FIGS. 1A and 1B, the present invention is characterized in that a source region S formed in one base region B is divided into a plurality. The source region S of the embodiment of FIG. 1 is substantially square in its entirety, and is divided into four equal parts at a cross-shaped dividing line perpendicular to the center of each side.
It is composed of divided source areas S '. Between the divided source regions S ', the base region B immediately below the divided source regions S'.
This is the same cross-shaped source division base area B ′.
The source divided base region B 'is exposed on the surface of the semiconductor substrate (1), and the center of the cross is located at the base contact region Ba.
Becomes
【００１５】図１のＦＥＴにおいても、ソース領域Ｓと
ベース領域Ｂ及びドレイン領域Ｄの間で寄生トランジス
タＱが形成される。この寄生トランジスタＱのエミッタ
とベース間は、４分割ソース領域Ｓ'…の真下のベース
領域Ｂ中の拡散抵抗Ｒａと、４分割ソース領域Ｓ'…の
間のソース分割ベース領域Ｂ'中の拡散抵抗Ｒｂで電気
的接続される。拡散抵抗Ｒａは、ソース領域Ｓの真下の
ベース領域Ｂが薄く、かつ、不純物濃度が低いために大
きいが、ソース分割ベース領域Ｂ'の拡散抵抗Ｒｂは、
拡散抵抗Ｒａより大幅に小さい。すなわち、ソース分割
ベース領域Ｂ'は、ソース領域Ｓ真下のベース領域Ｂよ
りソース領域Ｓの厚さ分だけ厚く形成され、かつ、ソー
ス分割ベース領域Ｂ'の表層部の不純物濃度がソース領
域Ｓ真下のベース領域Ｂの不純物濃度より高いので、こ
この拡散抵抗Ｒｂが小さくなる。実験によると、拡散抵
抗Ｒａが１０００Ω／□を超えるものにおいて、拡散抵
抗Ｒｂは５０〜１００Ω／□であり、拡散抵抗Ｒａの約
１／１０まで小さくなることが分かっている。In the FET of FIG. 1, a parasitic transistor Q is formed between the source region S, the base region B, and the drain region D. Between the emitter and the base of the parasitic transistor Q, the diffusion resistance Ra in the base region B directly below the four-divided source region S ', and the diffusion in the source-divided base region B' between the four divided source regions S '. They are electrically connected by a resistor Rb. The diffusion resistance Ra is large because the base region B immediately below the source region S is thin and has a low impurity concentration, but the diffusion resistance Rb of the source divided base region B ′ is
It is significantly smaller than the diffusion resistance Ra. That is, the source divided base region B ′ is formed to be thicker than the base region B immediately below the source region S by the thickness of the source region S, and the impurity concentration of the surface layer portion of the source divided base region B ′ is directly below the source region S. Is higher than the impurity concentration of the base region B, the diffusion resistance Rb here becomes small. According to an experiment, when the diffusion resistance Ra exceeds 1000 Ω / □, the diffusion resistance Rb is 50 to 100 Ω / □, which is reduced to about 1/10 of the diffusion resistance Ra.
【００１６】したがって、小さいベース電流で寄生トラ
ンジスタＱにベース・エミッタ間電圧が生じてコレクタ
電流が流れるとき、コレクタ電流は拡散抵抗値の小さい
ソース分割ベース領域Ｂ'を主として流れて、拡散抵抗
値の大きい分割ソース領域Ｓ'の真下のベース領域Ｂの
拡散抵抗Ｒａの影響力を弱める。かつ、分割ベース領域
Ｂ…を含むベース領域Ｂの全体の平均的拡散抵抗値が、
拡散抵抗Ｒｂのために小さくなり、その結果、図１のＦ
ＥＴの寄生トランジスタＱがベース電圧オフ時に導通し
難くなり、Ｌ負荷耐量が上がる。Accordingly, when a base-emitter voltage is generated in the parasitic transistor Q with a small base current and a collector current flows, the collector current mainly flows through the source divided base region B 'having a small diffusion resistance value, and The influence of the diffusion resistance Ra of the base region B directly below the large divided source region S ′ is reduced. And the average diffusion resistance of the entire base region B including the divided base regions B.
It becomes smaller due to the diffusion resistance Rb, and as a result, F
When the base voltage is off, the ET parasitic transistor Q becomes difficult to conduct, and the L load tolerance increases.
【００１７】また、ソース領域Ｓを４分割するソース分
割ベース領域Ｂ'の中心と全体のソース領域Ｓの中心が
目ずれを起こして、拡散抵抗Ｒａに場所的なバラツキが
生じても、これはソース分割ベース領域Ｂ'の小さな拡
散抵抗Ｒａの存在で無視できる。Further, even if the center of the source divided base region B 'which divides the source region S into four and the center of the entire source region S are misaligned, a local variation occurs in the diffusion resistance Ra. It can be neglected due to the presence of the small diffusion resistance Ra in the source division base region B ′.
【００１８】図２に示される実施例のＦＥＴは、略正方
形のソース領域Ｓを対角線方向に４分割している。４つ
の分割ソース領域Ｓ'…は略扇形をなし、それぞれの間
のソース分割ベース領域Ｂ'の拡散抵抗Ｒｂが５０〜１
００Ω／□と小さくなって、上記実施例と同様な作用効
果を発揮する。In the FET of the embodiment shown in FIG. 2, a substantially square source region S is divided into four in a diagonal direction. The four divided source regions S 'have a substantially sector shape, and the diffusion resistance Rb of the source divided base region B' between them is 50 to 1
It becomes as small as 00 Ω / □, and the same operation and effect as in the above embodiment are exhibited.
【００１９】以上の実施例におけるソース分割ベース領
域Ｂ'の幅Ｗは任意であるが、ソース領域Ｓが１μｍ程
度の深さで形成されているものにおいては、幅Ｗは２〜
３μｍが適当である。また、ソース領域Ｓを４等分に分
割したもので説明したが、２等分に分割したもの、或い
は５等分以上に分割することも可能である。このソース
領域Ｓの分割数は、多くなるほど各々の分割ソース領域
の面積が少なくなり、ＦＥＴ本来の特性を変えることに
なるので、４分割程度が望ましい。In the above embodiment, the width W of the source divided base region B 'is arbitrary, but when the source region S is formed to a depth of about 1 μm, the width W is 2 to 2.
3 μm is appropriate. Also, the source region S is described as being divided into four equal parts, but it is also possible to divide the source region S into two equal parts, or to divide it into five or more equal parts. As the number of divisions of the source region S increases, the area of each divided source region decreases and the original characteristics of the FET are changed.
【００２０】なお、本発明はｎチャネル型ＦＥＴに限ら
ず、ｐチャネル型ＦＥＴにも適用可能である。The present invention is not limited to an n-channel FET, but is applicable to a p-channel FET.
【００２１】[0021]
【発明の効果】本発明によれば、１ベース領域にソース
領域を分割して形成し、複数の分割ソース領域間をベー
ス領域にしたので、分割ソース領域間のソース分割ベー
ス領域での拡散抵抗がソース領域真下のベース領域の拡
散抵抗より大幅に小さくなって、ベース領域全体の実質
上の拡散抵抗が減少して、ソース領域とベース領域とド
レイン領域間で発生する寄生トランジスタがゲート電圧
オフ時に導通し難くなり、インダクタンス負荷耐量を大
きくすることが可能となる。According to the present invention, the source region is divided into one base region and the base region is formed between the plurality of divided source regions. Therefore, the diffusion resistance in the source divided base region between the divided source regions is reduced. Is significantly smaller than the diffusion resistance of the base region immediately below the source region, the effective diffusion resistance of the entire base region is reduced, and the parasitic transistor generated between the source region, the base region, and the drain region is turned off when the gate voltage is turned off. Conduction becomes difficult, and it becomes possible to increase the inductance load resistance.
【００２２】また、ソース領域を分割して、分割ソース
領域間の拡散抵抗を小さくすることで、ソース領域にベ
ースコンタクト領域を形成するときの目ずれの影響が少
なくできて、電界効果トランジスタの特性を安定させた
製造が容易にできるようになる。Further, by dividing the source region and reducing the diffusion resistance between the divided source regions, the influence of misalignment when forming the base contact region in the source region can be reduced, and the characteristics of the field effect transistor can be reduced. Can be easily manufactured.
【図１】（ａ）は本発明に係る電界効果トランジスタの
一実施例の要部断面図、（ｂ）は図１（ａ）の電界効果
トランジスタにおける半導体基板の部分平面図。1A is a cross-sectional view of a main part of an embodiment of a field-effect transistor according to the present invention, and FIG. 1B is a partial plan view of a semiconductor substrate in the field-effect transistor of FIG.
【図２】本発明の他の実施例の電界効果トランジスタに
おける半導体基板の部分平面図。FIG. 2 is a partial plan view of a semiconductor substrate in a field effect transistor according to another embodiment of the present invention.
【図３】（ａ）は従来のパワー用縦型電界効果トランジ
スタの要部断面図、（ｂ）は図２（ａ）の電界効果トラ
ンジスタにおける半導体基板の部分平面図、（ｃ）は図
３（ａ）（ｂ）の電界効果トランジスタに発生する寄生
トランジスタの回路図。3A is a sectional view of a main part of a conventional vertical field effect transistor for power, FIG. 3B is a partial plan view of a semiconductor substrate in the field effect transistor of FIG. 2A, and FIG. FIGS. 4A and 4B are circuit diagrams of parasitic transistors generated in the field-effect transistor of FIGS.
1 半導体基板 Ｄ ドレイン領域 Ｂ ベース領域 Ｂ' ソース分割ベース領域 Ｓ ソース領域 Ｓ' 分割ソース領域 1 Semiconductor substrate D Drain region B Base region B 'Source division base region S Source region S' Division source region
Claims (2)
の表面の所定領域に他導電型不純物を選択拡散して形成
した略正方形のベース領域の中央部分に、同ベース領域
と異なる一導電型不純物を選択拡散して形成される全体
が略正方形のソース領域が、幅狭で一定幅の他導電型ソ
ース分割ベース領域により略４等分に分割された４分割
ソース領域である電界効果トランジスタ。An impurity of one conductivity type different from that of the base region is formed at a central portion of a substantially square base region formed by selectively diffusing impurities of another conductivity type into a predetermined region on a surface of a semiconductor substrate serving as a drain region. The source region having a substantially square shape formed by selectively diffusing the source is a narrow, constant width, other conductivity type source region.
Divided into approximately four equal parts by the source divided base area
A field effect transistor that is a source region .
いる請求項１記載の電界効果トランジスタ。2. The field effect transistor according to claim 1, wherein said source region is divided into four equal parts on a diagonal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5162469A JP2903452B2 (en) | 1993-06-30 | 1993-06-30 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5162469A JP2903452B2 (en) | 1993-06-30 | 1993-06-30 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0766392A JPH0766392A (en) | 1995-03-10 |
| JP2903452B2 true JP2903452B2 (en) | 1999-06-07 |
Family
ID=15755221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5162469A Expired - Lifetime JP2903452B2 (en) | 1993-06-30 | 1993-06-30 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903452B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7705408B2 (en) | 2005-04-11 | 2010-04-27 | Nec Electronics Corporation | Vertical field effect transistor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3230504B2 (en) | 1998-12-11 | 2001-11-19 | 日本電気株式会社 | MIS type semiconductor device and method of manufacturing the same |
| JP4531861B2 (en) | 2008-07-09 | 2010-08-25 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4641162A (en) * | 1985-12-11 | 1987-02-03 | General Electric Company | Current limited insulated gate device |
| JPS63289871A (en) * | 1987-05-21 | 1988-11-28 | Hitachi Ltd | Semiconductor device |
-
1993
- 1993-06-30 JP JP5162469A patent/JP2903452B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7705408B2 (en) | 2005-04-11 | 2010-04-27 | Nec Electronics Corporation | Vertical field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766392A (en) | 1995-03-10 |
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