US20230147486A1 - Integrated freewheeling diode and extraction device - Google Patents

Integrated freewheeling diode and extraction device Download PDF

Info

Publication number
US20230147486A1
US20230147486A1 US18/090,835 US202218090835A US2023147486A1 US 20230147486 A1 US20230147486 A1 US 20230147486A1 US 202218090835 A US202218090835 A US 202218090835A US 2023147486 A1 US2023147486 A1 US 2023147486A1
Authority
US
United States
Prior art keywords
extraction
extraction device
main switch
igbt
fwd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US18/090,835
Inventor
Dumitru G. Sdrulla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MW RF Semiconductors LLC
Original Assignee
MW RF Semiconductors LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MW RF Semiconductors LLC filed Critical MW RF Semiconductors LLC
Priority to US18/090,835 priority Critical patent/US20230147486A1/en
Publication of US20230147486A1 publication Critical patent/US20230147486A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H01L27/0292—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
    • H01L27/0623—
    • H01L27/0629—
    • H01L29/7395—
    • H01L29/868—
    • H01L29/872—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H10D89/813—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements specially adapted to provide an electrical current path other than the field-effect induced current path

Definitions

  • This disclosure relates to semiconductor devices, and, more particularly, to a semiconductor structure that includes a Freewheeling Diode coupled to a forced carrier Extraction Device that improves the switching speed of a Main Switch for which the turn-off process depends on the recombination speed of charge carriers.
  • IGBTs Insulated Gate Bi-Polar Transistors
  • IGBTs include a built-in diode, but the built-in diode cannot be used as a FWD because of the P-type injector layer, which causes the built-in diode of the IGBT on the backside of the IGBT to have an orientation opposite that of a Mosfet.
  • the diode in an IGBT is formed at the intersection of the P-wells and N-type drift layer, for instance, or at the intersection of an N-well for a P-type IGBT.
  • the injector layer of the IGBT provides the conductivity modulation of the drift region while the IGBT is conducting, which makes the IGBT such a well-performing device from an on-conduction point of view. But this same injector layer prevents the built-in diode in an IGBT from acting as an FWD, which is why nearly all IGBTs are equipped with a separate FWD in most power applications.
  • SiC SBDs Silicon Carbide Schottky Barrier Diodes
  • Extraction Plugs which are described in detail in the incorporated '832 application, may be formed or placed inside the Main Switch, such as an IGBT, such that the electrical performance of the Main Switch is not degraded in any way. Although such Extraction Plugs may speed up a power semiconductor switch when coupled to an Extraction Device to remove charge in the drift region during the turn-off process of the switch, forming the Extraction Device itself may involve extra process steps compared to forming the IGBT itself.
  • Embodiments of the disclosure address these and other limitations of the prior art.
  • FIG. 1 is a conceptual schematic diagram of a switch having an Extraction terminal, connected to a voltage-controlled Extraction Device, according to embodiments of this disclosure.
  • FIG. 2 is a schematic diagram of a complementary IGBT having an injecting PNP transistor, as well as a P-channel MOSFET, and an N-channel MOSFET coupled in series, according to embodiments of the disclosure.
  • FIG. 3 is a simplified schematic diagram illustrating an IGBT switching device, having emitter, collector, and gate terminals, and further illustrating an Extraction Plug connection, to which an Extraction Device may be connected, according to embodiments of the disclosure.
  • FIG. 4 is a schematic of a known voltage-controlled Main Switch, such as an IGBT, having a free-wheeling diode connected in parallel to the switch.
  • FIG. 5 is a schematic diagram illustrating a Main Switch, a Freewheeling Diode, and an Extraction Device, according to embodiments of the invention.
  • FIG. 6 is a cross-sectional diagram of a Freewheeling Diode and an Extraction Device, according to embodiments of the invention.
  • FIG. 7 is a cross-sectional diagram illustrating a Freewheeling Diode, high-voltage termination, and a multi-cell PMOS formed on a semiconductor substrate, according to embodiments of the invention.
  • FIG. 8 is a cross-sectional diagram of a lateral PMOS Extraction Device and a high voltage capacitor according to embodiments of the invention.
  • FIG. 9 is a cross-sectional diagram of a vertical PMOS Extraction Device and a high voltage capacitor according to embodiments of the invention.
  • FIG. 10 is a top layout view of an integrated FWD with an Extraction Device, placed outside of the high voltage termination of the FWD, according to embodiments of the invention.
  • FIG. 11 is a top layout view of an integrated FWD with an Extraction Device, interspaced in the active area of the die, according to embodiments of the invention.
  • FIG. 12 is a top layout view of a voltage controlled Main Switch having an output on the backside of the die, according to embodiments of the invention.
  • FIG. 13 is a top assembly view of a voltage controlled Main Switch having Extraction Plugs formed around an edge of the die, according to embodiments of the invention.
  • the present disclosure relates to the field of power semiconductors with conductivity modulation, like IGBTs and its variants, which are structured or used to switch inductive loads.
  • a Freewheeling Diode is commonly used when the switching device, like the IGBT, has to commutate On and Off current through an inductance.
  • IGBTs remain an excellent choice for those semiconductor devices carrying relatively large amounts of current, so called power devices, the slow switching speeds caused by the slow recombination of minority carriers in conductivity-modulation bipolar devices after switching off continues to inhibit their performance.
  • Including Extraction Plugs and an Extraction Device in a three terminal device that uses conductivity modulation can greatly improve its switching speed, as described below.
  • Benefits of including an Extraction Device in conjunction with a power semiconductor device are described with reference to FIGS. 1 - 3 .
  • Benefits of including FWDs with power semiconductor devices that also include an Extraction Device are described with reference to FIGS. 4 - 13 .
  • FIG. 1 is a conceptual schematic diagram of a combined device 100 that generally includes a Main Switch 110 coupled to an Extraction Device 120 .
  • the device 100 further includes one or more Extraction Plugs 130 formed in the drift layer of the Main Switch 110 .
  • Extraction Plugs are fully described in the previously incorporated U.S. patent application Ser. No. 17/339,832.
  • Extraction Plugs may be formed in devices that use conductivity modulation to provide access to a drift layer of the device.
  • the Extraction Plugs 130 are formed and placed so that they do not degrade, in any way, the performance of the structure 100 , especially its blocking voltage.
  • An Extraction Device 120 also described in the '832 application, turns on when the Main Switch 110 turns off.
  • the Extraction Device 120 works to remove charge carriers left over in the bulk region when the Main Switch 110 turns off through the Extraction Plug 130 of the Main Switch.
  • the forced Extraction Device 120 is preferably voltage controlled, and its blocking voltage between terminals is generally the same or higher than the blocking voltage of the Main Switch 110 .
  • the structure 100 of FIG. 1 may be structured as a three-terminal device.
  • the structure 100 includes an input terminal coupled to an input 112 of the Main Switch 110 and to an input 122 of the Extraction Device 120 , and an output terminal 126 coupled to an output of the Extraction Device 120 .
  • the structure 100 further includes a ground terminal 114 coupled to the Main Switch 110 . Because the inputs 112 , 122 of the Main Switch 110 and Extraction Device 120 are tied together, the input signal driving the input 112 of the Main Switch 110 also drives the input 122 of the Extraction Device 120 .
  • the Extraction Device 120 may be integrated on the same die as the Main Switch 110 , or it may be a discrete device formed on a separate semiconductor substrate that is electrically coupled to the Main Switch. In some embodiments the semiconductor substrate for the Main Switch and a semiconductor substrate for the Extraction Device 120 may be separate substrates but assembled together in a single module or even in a single package.
  • the structure 100 of FIG. 1 conceptually operates as indicated as in Table 1:
  • the Extraction Device 120 In operation, when the Main Switch 110 is ON, the Extraction Device 120 is OFF, and vice-versa. In device operation, i.e., when the Main Switch 110 is conducting, the Extraction Device 120 does not interfere or affect the operation of the Main Switch 110 .
  • the operating parameters of a Main Switch 110 coupled to the Extraction Device 120 are the same or similar as a Main Switch that is not coupled to an Extraction Device.
  • the Main Switch 110 has a low breakdown voltage between the input and ground terminals, but a relatively high breakdown voltage between the output and ground terminals.
  • the Extraction Device 120 has a high breakdown voltage between its input and ground terminals, and a relatively low breakdown voltage between the ground and the output terminals.
  • FIG. 2 is a schematic diagram of a circuit 200 including components that may be used to form an example embodiment 200 that functions as the structure 100 of FIG. 1 .
  • the circuit 200 includes an IGBT Main Switch, which is formed of a PNP transistor 250 as an injector and an N-channel Mosfet 270 that drives the PNP transistor.
  • a P-channel Mosfet 260 functions as the Extraction Device 120 of FIG. 1 .
  • the Mosfets 260 and 270 are coupled in series.
  • the device 200 may be integrated on a single semiconductor die.
  • the P-Channel Mosfet 260 may be formed on a separate semiconductor die and electrically connected to the N-Channel Mosfet 270 .
  • the IGBT Main Switch further include a collector 216 , and an emitter 214 .
  • the P-Channel Mosfet 260 which operates as the Extraction Device, includes a source 224 and a drain 226 . Since the output terminal of the device 200 , in this configuration, is coupled to both the collector 216 of the IGBT and the drain 226 of the P-Channel Mosfet 260 , it is labeled as Output/Drain/Collector. Similarly, the ground terminal is coupled to the emitter 214 of the IGBT and the source of the N-Channel Mosfet 270 , the ground terminal is labeled Ground/Source/Emitter.
  • the input terminal of the device 200 is coupled to the gates of both the N-Channel Mosfet 270 and the P-Channel Mosfet 260 , the input terminal is labeled Input/Gate.
  • an Extraction Plug for the IGBT would be coupled to the base of the PNP transistor 250 , which is in the drift region of the IGBT, and is labeled as reference 280 .
  • the Extraction Plug, or reference 280 is electrically coupled to a source of the P-Channel Mosfet 260 .
  • the base of the PNP 250 transistor is connected to a ground at the source of the MOSFET 270 , while the device 200 is conducting. Then, when the Input/gate voltage goes LOW, to turn off the device 200 , the N-channel MOSFET 270 turns OFF, while the P-channel MOSFET 260 turns ON.
  • the P-Channel MOSFET 260 turning ON provides a path for excess charge to be removed from the drift region 280 from the source of the P-Channel Mosfet 260 to the drain of the P-Channel Mosfet, which is coupled to the output of the device 200 .
  • the P-Channel MOSFET 260 is formed so that, when the gate voltage is HIGH, the P-Channel MOSFET 260 is OFF, and turns on when the gate voltage goes LOW.
  • the P-Channel MOSFET 260 operates similar to that of a resistor, with its drain coupled to the positively bias on the collector 216 of the PNP 250 . Therefore, electrons are pulled toward the positively biased drain electrode of the P-Channel MOSFET 260 , and charge is removed from the drift region 280 at a relatively constant rate.
  • the P-Channel MOSFET 260 provides a path for the charge, carried by electrons, to be removed from the drift layer 280 through the positively charged drain.
  • the Extraction Device which here is the P-channel MOSFET 260 , extracts excess carriers relatively quickly from the bulk drift area 280 of the IGBT by conducting them to the collector through the P-channel MOSFET 260 . This action of removing the excess charge carriers when the IGBT turns off significantly decreases the turn-off time of the IGBT.
  • Extraction Plugs are used to provide access to areas of the bulk semiconductor in conductivity modulation devices. These Extraction Plugs, in turn, may be coupled to the source (i.e, the input or extraction terminal) of an Extraction Device to remove the excess carriers from the conductivity modulation device when the conductivity modulation device is being turned off. This greatly reduces the turn-off time of the conductivity modulation device. Further details of the structure of the Extraction Plugs may be obtained from the '832 application, although embodiments of the invention are applicable to other forms of Extraction Plugs providing the same function as that described herein.
  • FIG. 3 is a simple schematic diagram illustrating an IGBT switching device 300 , having emitter, collector, and gate terminals, and further illustrating an Extraction Plug terminal, also called an Extraction Terminal, to which an Extraction Device may be connected.
  • This schematic diagram neatly illustrates the concepts of including one or more Extraction Plugs in the drift region of an IGBT, which, as described above, facilitates the removal of carriers during forced carrier extraction from the drift region through the Extraction Plugs and further through the Extraction Device during turn-off of the Main Switch.
  • the Extraction Plug terminal is electrically connected to the Extraction Plug or Plugs in the IGBT.
  • the Extraction Plug terminal of the IGBT switching device 300 may be further coupled to an Extraction Device, as detailed below.
  • the Extraction Plug and Extraction Device are formed on the same semiconductor substrate, it is not strictly necessary that the Extraction Plug be coupled to an output terminal.
  • the Extraction Plug may be coupled to an Extraction Plug Terminal, which, in turn, may be coupled to an Extraction Device located on a different substrate. In this way, the process steps for forming an IGBT having an Extraction Plugs may be optimized separately from the process steps for forming an IGBT.
  • FIG. 4 is a schematic of a known voltage-controlled Main Switch 10 , such as an IGBT, having an FWD 12 connected in parallel to the switch.
  • FWD Freewheeling Diode
  • FIG. 4 is a schematic of a known voltage-controlled Main Switch 10 , such as an IGBT, having an FWD 12 connected in parallel to the switch.
  • some power semiconductor devices that carry relatively large amounts of current include an FWD, especially those that operate on inductive loads.
  • the FWD is connected in parallel to the main semiconductor switch.
  • the IGBT 10 is a bipolar semiconductor device used for carrying relatively large current loads.
  • the IGBT 10 includes emitter, collector, and gate terminals, which function as the input, output, and gate terminals of the switch.
  • the FWD 12 is coupled in parallel to the IGBT, with one terminal of the FWD coupled to the collector and the other terminal coupled to the emitter.
  • the FWD 12 shunts current from the inductive load across the IGBT 10 as the IGBT turns off, and also limits voltage across the IGBT. Otherwise, the current generated by the collapse of the magnetic field around the inductor would be applied directly to the IGBT 10 , which would likely cause damage. In this way the FWD 12 acts as a protection device for the switch 10 .
  • the FWD 12 is designed and fabricated to withstand the full rated voltage of the Main Switch 10 , including the avalanche rating, or it has to be implemented with a higher blocking voltage than the Main Switch.
  • FIG. 5 is a schematic diagram illustrating a system 500 that includes a Main Switch 510 having an Extraction Plug electrode 512 , an FWD 520 , and an Extraction Device 530 , according to embodiments of the invention.
  • a Main Switch 510 having an Extraction Plug electrode 512 , an FWD 520 , and an Extraction Device 530 , according to embodiments of the invention.
  • the FWD 520 and an Extraction Device 530 are packaged in a separate device 550 , which is electrically connected to the Main Switch 510 .
  • the Main Switch 510 may be a one semiconductor die, and the separate device 550 , including the FWD 520 and an Extraction Device 530 , is formed on another semiconductor die, but both the semiconductor dies are together in a single semiconductor module or package. More details and discussion of possible layouts is given below.
  • System 500 illustrates a three-terminal device capable of driving inductive loads, since the IGBT Main Switch 510 is electrically coupled to the FWD 520 , even though the diode 520 may be formed on a substrate separate from the IGBT Main Switch 510 . Further, since the turn-off time of an IGBT is shortened by coupling an Extraction Device 530 to the Extraction Plug 512 of the IGBT 510 , including an Extraction Device 530 in the system 500 provides the extraction function when the IGBT 510 turns off. Therefore, it may be convenient to produce the IGBT Main Switch 510 with an Extraction Plug terminal 512 separately from a device that includes both an FWD as well as an Extraction Device, such as the device 530 .
  • the system 500 may form a single package or module including one component having the IGBT Main Switch 510 and having another component 550 , which includes the FWD 520 and the Extraction Device 530 . Electrical connections are made within the system 500 as illustrated in FIG. 5 .
  • a gate of the IGBT Main Switch 510 is electrically coupled to an input of the Extraction Device 530 .
  • the Extraction Plug terminal 512 of the IGBT Main Switch 510 is electrically coupled to an extraction input 532 of the Extraction Device 530 .
  • a collector of the IGBT Main Switch 510 is coupled to an output of the Extraction Device 530 .
  • a cathode of the FWD 520 is coupled to a collector of the IGBT Main Switch 510
  • the anode of the FWD 520 is coupled to an emitter of the IGBT Main Switch 510 .
  • the system 500 is created in a discrete package 560 , it could be a three-terminal device with an input control terminal 562 , a ground terminal 564 , and an output terminal 566 .
  • a package 560 includes an IGBT 510 or Main Switch having an Extraction Plug terminal 512 that is coupled to a component 550 .
  • the component 550 includes an FWD 520 and an Extraction Device 530 .
  • This package 560 includes all of the components for a power device for driving an inductive load having a shortened turn-off time compared to typical IGBTs.
  • the FWD 520 is effectively mandatory for any power switch operating with an inductive load.
  • Embodiments of the invention further include the Extraction Device 530 to shorten the turn-off time of the voltage-controlled switch device with conductivity modulation 510 .
  • the Main Switch 510 is illustrated as being an IGBT, embodiments of the invention extend to any voltage-controlled switch device with conductivity modulation.
  • FIG. 6 is a cross-sectional diagram of an integrated device 600 including an FWD 610 and an Extraction Device 620 produced on a same semiconductor substrate, according to embodiments of the invention.
  • the FWD 610 is a merged PN-Schottky structure.
  • the FWD 610 may be any of several different types of FWDs.
  • the FWD 610 may be a PIN (p-type and n-type materials separated by an insulator) diode, and may or may not include materials for shortening carrier lifetimes, such as gold or platinum diffusions, electron or proton irradiations, etc.
  • the FWD 610 may also be a Fast Recovery Diode, for example.
  • the FWD 610 and the Extraction Device 620 of the integrated device 600 are formed on the same semiconductor die, they may be separated by a deep trench 640 , which may be formed using standard fabrication techniques.
  • the deep trench 640 separates the cathode of the FWD 520 ( FIG. 5 ) from the substrate of the lateral PMOS in the Extraction Device 530 . Such separation allows each device to operate virtually independent from one another. It is not necessary that the FWD 610 and the Extraction Device 620 be formed on the same die. In other embodiments the FWD 610 and the Extraction Device 620 may be electrically coupled to one another but formed on separate semiconductor dies.
  • the lateral PMOS Extraction Device 620 includes a thick gate oxide 105 .
  • the Extraction Device 620 is also “counter doped” at the surface of the semiconductor to create conditions for a suitable turn-on voltage, Vth. As represented in this cross section of FIG. 6 , the FWD 610 and the PMOS Extraction Device 620 structures could be formed and interspaced in the active area of the die.
  • the device 600 is an example of the type of structure that could make the component 550 part of the device 500 of FIG. 5 .
  • a polysilicon gate 103 front metal 106 , passivation layer 108 , substrate 150 , such as SiC or other wide bandgap material, N-type drift region 151 , P-Wells 160 , Schottky Metal 165 , and counter-doped region 170 .
  • FIG. 7 is a cross-sectional diagram of a device 700 illustrating an FWD 710 , high-voltage termination 750 , and a multi-cell PMOS Extraction Device 720 formed on any type of semiconductor, such as Silicon, SiC, wide-bandgap material, etc., according to embodiments of the invention.
  • the placement of the Extraction Device 720 in the illustrated embodiment of FIG. 7 is outside of the High Voltage Termination 750 of the FWD 710 , but this placement is not mandatory.
  • the P-Wells 101 of the FWD 710 and Extraction Device 720 can very well operate together to provide a blocking voltage needed for the FWD.
  • Other conventional components of the device 700 not referred to above include a gate 202 , source 203 , and drain 204 of the PMOS transistors in the Extraction Device 720 .
  • FIG. 8 is a cross-sectional diagram of a lateral PMOS Extraction Device 800 that includes a PMOS transistor 810 coupled to a high voltage capacitor 820 , according to embodiments of the invention.
  • the capacitor 820 includes electrodes 822 separated by an insulating or dielectric layer 824 .
  • the PMOS transistor 810 includes a thin gate oxide 812 . In some instances the thin gate oxide 812 is easier to produce than a thick gate oxide, used in previous examples, so the thin gate oxide may be preferable.
  • the high voltage capacitor 820 is series coupled to the built-in capacitance of the thin gate oxide 812 .
  • the Extraction Device does not have any substantive function during the DC operation of the Main Switch, i.e., while the Main Switch is fully off or fully on.
  • an external capacitor with a relatively high voltage rating it is possible for an external capacitor with a relatively high voltage rating to be used to seamlessly protect the gate oxide of the PMOS Extraction Device, even when, such as in the Extraction Device 800 , it has a thin gate oxide.
  • This series circuit configuration is possible because the PMOS Extraction Device 800 operates only during the switching on and off of the Main Device (not illustrated in FIG.
  • the switching control signals also cause the turn-on and turn-off of the PMOS transistor 810 in a seamless way.
  • the total capacitance of the series connection of these two capacitances can be tailored to adjust the voltage spikes of the gate signal. This protection is important, especially in the case when the Main Switch is made on wide bandgap semiconductors, for which the gate oxides are very thin and therefore very sensitive to voltage spikes.
  • the capacitance of the series connection of the capacitance of the gate oxide 812 of the PMOS 810 and the capacitor 820 itself may range from 1 pF to 800 pF, and more preferably from 1 pF to 100 pF. Of course, the specific values of the capacitance of the series connection will be implementation specific.
  • the Extraction Device 800 is an example type of device that may be present in the device 550 and used for the Extraction Device 530 of FIG. 5 .
  • FIG. 9 is a cross-sectional diagram of a vertical PMOS Extraction Device 900 , including a vertical PMOS transistor 910 .
  • the PMOS transistor 910 may be made on any type of semiconductor material.
  • the PMOS transistor 910 in this embodiment has a thick gate oxide 105 , which provides a high voltage rating for the PMOS transistor 910 , exceeding that of a Main Switch to which it is connected.
  • the Extraction Device 900 includes a high-voltage rated capacitor 920 that is connected in series with the Gate-Drain capacitance of the vertical PMOS transistor 910 .
  • the capacitor 920 is formed of conductive plates 922 separated by an insulator 924 .
  • the high voltage capacitor 920 has similar dimensions as does the PMOS transistor 910 , such as the Poly Gate Width of the vertical PMOS 910 , in actuality, the high voltage capacitor 920 can be placed anywhere on the top of the PMOS die, or outside of it and properly wire-bonded to the control electrode of the Extraction Device.
  • FIGS. 8 and 9 illustrate various options that may be used in implementing the Extraction Device, such as the Extraction Device 530 of FIG. 5 .
  • FIG. 10 is a top layout view of a device 1000 that includes an FWD 1010 integrated with an Extraction Device 1030 on a single semiconductor substrate.
  • the FWD 1010 may be one of the FWDs described above.
  • the FWD 1010 is surrounded by a high voltage termination 1020 .
  • An Extraction Device 1030 is placed outside the high voltage termination 1020 of the FWD 1010 .
  • the Extraction Device 1030 includes an input electrode 1032 for extraction, an output electrode 1034 , and a control electrode 1036 .
  • This device 1030 is an example layout of the device 550 of FIG. 5 .
  • the control electrode 1036 would be coupled to a gate of the IGBT
  • the input (for extraction) electrode 1032 would be coupled to the Extraction Plug terminal of the IGBT
  • the output electrode 1034 would be coupled to both a collector of the IGBT and to a cathode (not illustrated) of the FWD 1010 .
  • the anode (not illustrated) of the FWD 1010 would be coupled to the emitter of the IGBT.
  • FIG. 11 is a top layout view of a device 1100 including one or more FWDs 1110 and one or more Extraction Devices 1130 as described above.
  • the FWDs 1110 are interleaved with the Extraction Devices 1130 in the active area of the die.
  • the electrodes of the Extraction Devices 1130 are not illustrated as they may be implementation specific, and may be placed as the design dictates.
  • the FWDs 1110 illustrated in the device 1100 may be coupled together to make one or more FWDs. In other words, FWDs 1110 A and 1110 B may be coupled to one another to make a single, larger FWD.
  • all of the FWDs 1110 A, 1110 B, 1110 C, and 1110 D maybe be coupled together to make a single FWD for the entire device 1100 .
  • FIG. 11 illustrates the cellular or tessellated nature of the design in which multiple FWDs 1110 and Extraction Devices 1130 may be produced without affecting the functionality of the device.
  • the FWD 1110 and Extraction Device 1130 may be coupled to a one or more IGBTs as described above with reference to FIG. 10 .
  • FIG. 12 is a top layout view of a complete device 1200 that includes a voltage controlled Main Switch 1210 formed on a first semiconductor die coupled to an assisting device 1220 formed on a second semiconductor die.
  • the Main Switch 1210 includes Extraction Plugs 700 placed inside an active area 1250 .
  • the active area 1250 of a semiconductor device is the area within which the main electrical function of the power semiconductor device is performed.
  • Metallizations 107 connect the Extraction Plugs 700 to each other.
  • a gate terminal 1212 of the Main Switch 1210 is also illustrated within the active area 1250 .
  • the Main Switch 1210 has its output on the backside of the die.
  • the assisting device 1220 includes an FWD 1230 and a PMOS transistor 1240 , which functions as an Extraction Device, as described above.
  • the Extraction Device 1240 includes an input terminal 1242 for extraction, an output terminal 1244 , and a control terminal 1246 .
  • the Extraction Plugs 700 of the Main Switch 1210 are connected to one another through the metalizations 107 and also to the extraction input 1242 of the Extraction Device 1240 through a wire bond 1260 .
  • a wire bond electrically connects devices that are produced on two different substrates, where die metallizations cannot be used.
  • Another wire bond 1282 couples the gate terminal 1212 of the Main Switch 1210 to the control electrode 1246 of the Extraction Device 1240 .
  • the FWD 1230 has its anode coupled to an emitter of the Main Switch 1210 through a wire bond 1264 .
  • the output of the Extraction Device 1240 is coupled by a wire bond 1266 to a collector of the Main Switch 1210 , which, as described above, is located on the back side of the Main Switch 1210 , and is therefore not visible in FIG. 12 .
  • the output of the Extraction Device 1240 is also coupled to the cathode of the FWD 1230 .
  • This connection between the output of the Extraction Device 1240 and the cathode of the FWD 1230 may be an internal metallization within the assisting device 1220 , and is therefore not separately illustrated in FIG. 12 .
  • FIG. 12 is an example of a physical manifestation of the device 560 described above with reference to FIG. 5 , which includes both a Main Switch 510 and assisting device 550 .
  • the wire bond 1264 would be coupled to the ground terminal of the device, the wire bond 1266 would be coupled to the output terminal of the device, and the wire bond 1262 would be coupled to the control input terminal of the device.
  • the wire bond 1260 would not need to be connected to a terminal of the complete device 1200 because the connection between the Extraction Plug terminal of the Main Switch 1210 and the input terminal 1242 of the Extraction Device 1240 need only be an internal connection.
  • FIG. 13 is a top assembly view of a device 1300 that is similar to the device 1200 of FIG. 12 .
  • the same or similar features that were described with reference to FIG. 12 will not be repeated in the description of FIG. 13 , for brevity.
  • the main difference between devices 1200 and 1300 is that the extraction plugs 700 of the device 1300 are formed outside of the high voltage termination 1250 , whereas the Extraction Plugs 700 of the device 1300 are formed within the high voltage termination 1250 .
  • location of the Extraction Plugs 700 has little or no effect on their function to provide an access to the drift area of the semiconductor Main Switch through which the Extraction Device 1240 can expediently remove charge from while the Main Switch is turning off.
  • Power semiconductor switches having Extraction Plugs may be developed as a hybrid of the devices 1200 and 1300 , with some Extraction Plugs 700 located inside the high voltage termination area 1250 and some Extraction Plugs 700 located outside the high voltage termination area within the same device itself.
  • an IGBT or other semiconductor device may take the following forms, along with their equivalents.
  • Example 1 is a Freewheeling diode integrated with a Forced Extraction Device.
  • the Freewheeling diode may be of any kind, such as PIN, Schottky, etc.
  • Example 2 is a Freewheeling Diode coupled to an Extraction Device, which, in turn, is connected to a Main Switch that includes an Extraction Electrode or Extraction Plugs.
  • Example 3 is a Freewheeling Diode integrated with an Extraction Device, in which both the Diode and Extraction Device are made on Silicon.
  • Example 4 is a Freewheeling Diode integrated with an Extraction Device, in which both the Diode and Extraction Device are made on Wide Bandgap semiconductors.
  • Example 5 is a Freewheeling Diode integrated with a lateral PMOS Extraction Device, which, in turn, is connected to a Main Switch.
  • the lateral PMOS Extraction Device has a thick gate oxide that withstands at least the blocking voltage of the Main Switch (IGBT).
  • Example 6 is a Freewheeling Diode integrated with a lateral PMOS Extraction Device.
  • the lateral PMOS has a thin gate oxide and a high voltage rating capacitor that is connected in series with the capacitor of the controlling electrode of the Extraction Device.
  • Example 7 is a Freewheeling Diode integrated with a vertical PMOS Extraction Device which, in turn, is connected to a Main Switch.
  • the vertical PMOS Extraction Device has a thick gate oxide that withstands at least the blocking voltage of the Main Switch (IGBT).
  • Example 8 is a Freewheeling Diode integrated with a vertical PMOS Extraction Device.
  • the vertical PMOS has a thin gate oxide and a high voltage rating capacitor that is connected in series with the capacitor of the controlling electrode of the Extraction Device
  • Example 9 is a High Voltage Capacitor connected in series with the capacitor of the controlling electrode of the Extraction Device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A Freewheeling Diode of any kind (Fast Recovery Diode, Schottky Barrier Diode or other variants) is integrated with a Forced Extraction Device and in this way two entirely different functions—the Free-Wheeling function and the Forced Extraction function are combined in one device, simplifying the circuit and reducing the number of components. The FWD part of the integrated device is standard in the industry, but the Forced Extraction Device is made using a lateral or vertical PMOS with a votage capability between a control input and the output terminals that is as high or higher than the rating voltage of the Main Switch that will be used together with the FWD.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. application Ser. No. 17/496,658, filed Oct. 7, 2021, which is a non-provisional of and claims benefit to U.S. provisional patent application No. 63/093,701, filed Oct. 19, 2020, entitled SEMICONDUCTOR STRUCTURE HAVING A FORCED EXTRACTION DEVICE, the disclosure of which is incorporated herein by reference in its entirety. This application is also related to U.S. patent application Ser. No. 17/339,832, filed Jun. 4, 2021, entitled POWER SEMICONDUCTOR DEVICE WITH FORCED CARRIER EXTRACTION AND METHOD OF MANUFACTURE, which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • This disclosure relates to semiconductor devices, and, more particularly, to a semiconductor structure that includes a Freewheeling Diode coupled to a forced carrier Extraction Device that improves the switching speed of a Main Switch for which the turn-off process depends on the recombination speed of charge carriers.
    • BACKGROUND
  • The previously incorporated U.S. patent application Ser. No. 17/339,832 describes problems with long turn-off times in power semiconductor switches and a solution that uses a forced carrier Extraction Device. Some power semiconductor devices that carry relatively large amounts of current include a Freewheeling Diode (FWD), especially those that operate on inductive loads. In power circuits like push-pull, half-bridge or full-bridge modules, the Freewheeling Diode is connected in parallel to the main semiconductor switch. Some power switches, like Mosfets, have a “built in” diode, which can be used as a Freewheeling Diode. In such cases, special process steps are used to shorten the reverse recovery time and lower the reverse recovery charge of the FWD, as this charge contributes to the turn-on switching energy of the Main Switch.
  • Insulated Gate Bi-Polar Transistors (IGBTs) are widely used for a broad range of power semiconductors since their features are well suited for such roles. IGBTs include a built-in diode, but the built-in diode cannot be used as a FWD because of the P-type injector layer, which causes the built-in diode of the IGBT on the backside of the IGBT to have an orientation opposite that of a Mosfet. The diode in an IGBT is formed at the intersection of the P-wells and N-type drift layer, for instance, or at the intersection of an N-well for a P-type IGBT. The injector layer of the IGBT provides the conductivity modulation of the drift region while the IGBT is conducting, which makes the IGBT such a well-performing device from an on-conduction point of view. But this same injector layer prevents the built-in diode in an IGBT from acting as an FWD, which is why nearly all IGBTs are equipped with a separate FWD in most power applications.
  • Recently, Silicon Carbide Schottky Barrier Diodes (SiC SBDs) have been replacing Silicon FWDs in commercial products. An SBD formed on SiC has a lower forward voltage and no reverse recovery charge, and therefore its contribution to the turn-on energy loss of the Main Switch, such as when an IGBT is used for the Main Switch, is due only to the charge stored in the depletion region of the SBD.
  • Another effect of the existence of the injector layer opposite to the Mosfet makes the turn-off process of a Main Switch that employs conductivity modulation, such as an IGBT, very slow, due to the need of the injected carriers to “disappear” through recombination when the IGBT turns off.
  • Special process steps that control the level of injection or the recombination rate are widely used to speed up the turn-off time of power semiconductors that use conductivity modulation. Providing such a switch, such as an IGBT, with an ability or structure to remove excess charge in the drift region and therefore lower the turn-off energy of the power semiconductor, is a worthwhile goal.
  • State-of-the-art IGBTs lack the means to access the region where the carriers contributing to the conductivity modulation recombine. Extraction Plugs, which are described in detail in the incorporated '832 application, may be formed or placed inside the Main Switch, such as an IGBT, such that the electrical performance of the Main Switch is not degraded in any way. Although such Extraction Plugs may speed up a power semiconductor switch when coupled to an Extraction Device to remove charge in the drift region during the turn-off process of the switch, forming the Extraction Device itself may involve extra process steps compared to forming the IGBT itself.
  • Embodiments of the disclosure address these and other limitations of the prior art.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a conceptual schematic diagram of a switch having an Extraction terminal, connected to a voltage-controlled Extraction Device, according to embodiments of this disclosure.
  • FIG. 2 is a schematic diagram of a complementary IGBT having an injecting PNP transistor, as well as a P-channel MOSFET, and an N-channel MOSFET coupled in series, according to embodiments of the disclosure.
  • FIG. 3 is a simplified schematic diagram illustrating an IGBT switching device, having emitter, collector, and gate terminals, and further illustrating an Extraction Plug connection, to which an Extraction Device may be connected, according to embodiments of the disclosure.
  • FIG. 4 is a schematic of a known voltage-controlled Main Switch, such as an IGBT, having a free-wheeling diode connected in parallel to the switch.
  • FIG. 5 is a schematic diagram illustrating a Main Switch, a Freewheeling Diode, and an Extraction Device, according to embodiments of the invention.
  • FIG. 6 is a cross-sectional diagram of a Freewheeling Diode and an Extraction Device, according to embodiments of the invention.
  • FIG. 7 is a cross-sectional diagram illustrating a Freewheeling Diode, high-voltage termination, and a multi-cell PMOS formed on a semiconductor substrate, according to embodiments of the invention.
  • FIG. 8 is a cross-sectional diagram of a lateral PMOS Extraction Device and a high voltage capacitor according to embodiments of the invention.
  • FIG. 9 is a cross-sectional diagram of a vertical PMOS Extraction Device and a high voltage capacitor according to embodiments of the invention.
  • FIG. 10 is a top layout view of an integrated FWD with an Extraction Device, placed outside of the high voltage termination of the FWD, according to embodiments of the invention.
  • FIG. 11 is a top layout view of an integrated FWD with an Extraction Device, interspaced in the active area of the die, according to embodiments of the invention.
  • FIG. 12 is a top layout view of a voltage controlled Main Switch having an output on the backside of the die, according to embodiments of the invention.
  • FIG. 13 is a top assembly view of a voltage controlled Main Switch having Extraction Plugs formed around an edge of the die, according to embodiments of the invention.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • The present disclosure relates to the field of power semiconductors with conductivity modulation, like IGBTs and its variants, which are structured or used to switch inductive loads. When switching inductive loads, a Freewheeling Diode is commonly used when the switching device, like the IGBT, has to commutate On and Off current through an inductance. Thus, although IGBTs remain an excellent choice for those semiconductor devices carrying relatively large amounts of current, so called power devices, the slow switching speeds caused by the slow recombination of minority carriers in conductivity-modulation bipolar devices after switching off continues to inhibit their performance. Including Extraction Plugs and an Extraction Device in a three terminal device that uses conductivity modulation can greatly improve its switching speed, as described below.
  • Benefits of including an Extraction Device in conjunction with a power semiconductor device are described with reference to FIGS. 1-3 . Benefits of including FWDs with power semiconductor devices that also include an Extraction Device are described with reference to FIGS. 4-13 .
  • FIG. 1 is a conceptual schematic diagram of a combined device 100 that generally includes a Main Switch 110 coupled to an Extraction Device 120. The device 100 further includes one or more Extraction Plugs 130 formed in the drift layer of the Main Switch 110. Extraction Plugs are fully described in the previously incorporated U.S. patent application Ser. No. 17/339,832. In general, Extraction Plugs may be formed in devices that use conductivity modulation to provide access to a drift layer of the device. The Extraction Plugs 130 are formed and placed so that they do not degrade, in any way, the performance of the structure 100, especially its blocking voltage. An Extraction Device 120, also described in the '832 application, turns on when the Main Switch 110 turns off. If the Main Switch is embodied by a device that uses conductivity modulation, such as an IGBT, the Extraction Device 120 works to remove charge carriers left over in the bulk region when the Main Switch 110 turns off through the Extraction Plug 130 of the Main Switch. The forced Extraction Device 120 is preferably voltage controlled, and its blocking voltage between terminals is generally the same or higher than the blocking voltage of the Main Switch 110.
  • The structure 100 of FIG. 1 may be structured as a three-terminal device. The structure 100 includes an input terminal coupled to an input 112 of the Main Switch 110 and to an input 122 of the Extraction Device 120, and an output terminal 126 coupled to an output of the Extraction Device 120. The structure 100 further includes a ground terminal 114 coupled to the Main Switch 110. Because the inputs 112, 122 of the Main Switch 110 and Extraction Device 120 are tied together, the input signal driving the input 112 of the Main Switch 110 also drives the input 122 of the Extraction Device 120.
  • The Extraction Device 120 may be integrated on the same die as the Main Switch 110, or it may be a discrete device formed on a separate semiconductor substrate that is electrically coupled to the Main Switch. In some embodiments the semiconductor substrate for the Main Switch and a semiconductor substrate for the Extraction Device 120 may be separate substrates but assembled together in a single module or even in a single package.
  • The structure 100 of FIG. 1 conceptually operates as indicated as in Table 1:
  • TABLE 1
    Operational States of Main Device and Extraction Device
    Turn Turn Input-Ground Output-Ground
    Device/State On Off Voltage Voltage
    Main Device On Off Low High
    Extraction Device OFF On High Low
  • In operation, when the Main Switch 110 is ON, the Extraction Device 120 is OFF, and vice-versa. In device operation, i.e., when the Main Switch 110 is conducting, the Extraction Device 120 does not interfere or affect the operation of the Main Switch 110. In other words, the operating parameters of a Main Switch 110 coupled to the Extraction Device 120 are the same or similar as a Main Switch that is not coupled to an Extraction Device. The Main Switch 110 has a low breakdown voltage between the input and ground terminals, but a relatively high breakdown voltage between the output and ground terminals. Conversely, the Extraction Device 120 has a high breakdown voltage between its input and ground terminals, and a relatively low breakdown voltage between the ground and the output terminals.
  • FIG. 2 is a schematic diagram of a circuit 200 including components that may be used to form an example embodiment 200 that functions as the structure 100 of FIG. 1 . The circuit 200 includes an IGBT Main Switch, which is formed of a PNP transistor 250 as an injector and an N-channel Mosfet 270 that drives the PNP transistor. A P-channel Mosfet 260 functions as the Extraction Device 120 of FIG. 1 . The Mosfets 260 and 270 are coupled in series. The device 200 may be integrated on a single semiconductor die. In other embodiments, as described above, the P-Channel Mosfet 260 may be formed on a separate semiconductor die and electrically connected to the N-Channel Mosfet 270. Internal components of the IGBT Main Switch further include a collector 216, and an emitter 214. The P-Channel Mosfet 260, which operates as the Extraction Device, includes a source 224 and a drain 226. Since the output terminal of the device 200, in this configuration, is coupled to both the collector 216 of the IGBT and the drain 226 of the P-Channel Mosfet 260, it is labeled as Output/Drain/Collector. Similarly, the ground terminal is coupled to the emitter 214 of the IGBT and the source of the N-Channel Mosfet 270, the ground terminal is labeled Ground/Source/Emitter. Finally, since the input terminal of the device 200 is coupled to the gates of both the N-Channel Mosfet 270 and the P-Channel Mosfet 260, the input terminal is labeled Input/Gate. Although it is not separately shown on the schematic diagram of the circuit 200, an Extraction Plug for the IGBT would be coupled to the base of the PNP transistor 250, which is in the drift region of the IGBT, and is labeled as reference 280. Importantly, the Extraction Plug, or reference 280, is electrically coupled to a source of the P-Channel Mosfet 260.
  • In operation of the device 200, when the Input/gate voltage is HIGH, the base of the PNP 250 transistor is connected to a ground at the source of the MOSFET 270, while the device 200 is conducting. Then, when the Input/gate voltage goes LOW, to turn off the device 200, the N-channel MOSFET 270 turns OFF, while the P-channel MOSFET 260 turns ON. The P-Channel MOSFET 260 turning ON provides a path for excess charge to be removed from the drift region 280 from the source of the P-Channel Mosfet 260 to the drain of the P-Channel Mosfet, which is coupled to the output of the device 200. The P-Channel MOSFET 260 is formed so that, when the gate voltage is HIGH, the P-Channel MOSFET 260 is OFF, and turns on when the gate voltage goes LOW. At low Vgs voltages of the N-Channel Mosfet 270, when the Main Switch (IGBT) turns OFF, the P-Channel MOSFET 260 operates similar to that of a resistor, with its drain coupled to the positively bias on the collector 216 of the PNP 250. Therefore, electrons are pulled toward the positively biased drain electrode of the P-Channel MOSFET 260, and charge is removed from the drift region 280 at a relatively constant rate. The P-Channel MOSFET 260 provides a path for the charge, carried by electrons, to be removed from the drift layer 280 through the positively charged drain. Recall that one of the main problems for conventional IGBT devices to switch off quickly is that there is no access to the drain of the Mosfet. Instead, the Extraction Device, which here is the P-channel MOSFET 260, extracts excess carriers relatively quickly from the bulk drift area 280 of the IGBT by conducting them to the collector through the P-channel MOSFET 260. This action of removing the excess charge carriers when the IGBT turns off significantly decreases the turn-off time of the IGBT.
  • The aforementioned Extraction Plugs, or merely plugs, are used to provide access to areas of the bulk semiconductor in conductivity modulation devices. These Extraction Plugs, in turn, may be coupled to the source (i.e, the input or extraction terminal) of an Extraction Device to remove the excess carriers from the conductivity modulation device when the conductivity modulation device is being turned off. This greatly reduces the turn-off time of the conductivity modulation device. Further details of the structure of the Extraction Plugs may be obtained from the '832 application, although embodiments of the invention are applicable to other forms of Extraction Plugs providing the same function as that described herein.
  • FIG. 3 is a simple schematic diagram illustrating an IGBT switching device 300, having emitter, collector, and gate terminals, and further illustrating an Extraction Plug terminal, also called an Extraction Terminal, to which an Extraction Device may be connected. This schematic diagram neatly illustrates the concepts of including one or more Extraction Plugs in the drift region of an IGBT, which, as described above, facilitates the removal of carriers during forced carrier extraction from the drift region through the Extraction Plugs and further through the Extraction Device during turn-off of the Main Switch. The Extraction Plug terminal is electrically connected to the Extraction Plug or Plugs in the IGBT. In application, the Extraction Plug terminal of the IGBT switching device 300 may be further coupled to an Extraction Device, as detailed below. In embodiments where the Extraction Plug and Extraction Device are formed on the same semiconductor substrate, it is not strictly necessary that the Extraction Plug be coupled to an output terminal. In other embodiments, where the Extraction Plug and Extraction Device are formed on different substrates, the Extraction Plug may be coupled to an Extraction Plug Terminal, which, in turn, may be coupled to an Extraction Device located on a different substrate. In this way, the process steps for forming an IGBT having an Extraction Plugs may be optimized separately from the process steps for forming an IGBT.
  • Further, recall from above that power switching devices that drive inductive loads nearly always include a Freewheeling Diode (FWD) to protect the switch from over voltage as the switch turns off and the magnetic field around the inductive load collapses. To protect against damage caused by the inductor, a protective FWD is coupled in parallel to the switch. FIG. 4 is a schematic of a known voltage-controlled Main Switch 10, such as an IGBT, having an FWD 12 connected in parallel to the switch. As described above, some power semiconductor devices that carry relatively large amounts of current include an FWD, especially those that operate on inductive loads. In power circuits like push pull, half-bridge or full-bridge modules, the FWD is connected in parallel to the main semiconductor switch. With reference to FIG. 4 , the IGBT 10 is a bipolar semiconductor device used for carrying relatively large current loads. The IGBT 10 includes emitter, collector, and gate terminals, which function as the input, output, and gate terminals of the switch. The FWD 12 is coupled in parallel to the IGBT, with one terminal of the FWD coupled to the collector and the other terminal coupled to the emitter. In circuits that drive inductive loads, the FWD 12 shunts current from the inductive load across the IGBT 10 as the IGBT turns off, and also limits voltage across the IGBT. Otherwise, the current generated by the collapse of the magnetic field around the inductor would be applied directly to the IGBT 10, which would likely cause damage. In this way the FWD 12 acts as a protection device for the switch 10. Also, the FWD 12 is designed and fabricated to withstand the full rated voltage of the Main Switch 10, including the avalanche rating, or it has to be implemented with a higher blocking voltage than the Main Switch.
  • FIG. 5 is a schematic diagram illustrating a system 500 that includes a Main Switch 510 having an Extraction Plug electrode 512, an FWD 520, and an Extraction Device 530, according to embodiments of the invention. Although all of the components illustrated in FIG. 5 may be integrated on a single die, it is possible, and perhaps preferable, that the FWD 520 and an Extraction Device 530 are packaged in a separate device 550, which is electrically connected to the Main Switch 510. Also, the Main Switch 510 may be a one semiconductor die, and the separate device 550, including the FWD 520 and an Extraction Device 530, is formed on another semiconductor die, but both the semiconductor dies are together in a single semiconductor module or package. More details and discussion of possible layouts is given below.
  • System 500 illustrates a three-terminal device capable of driving inductive loads, since the IGBT Main Switch 510 is electrically coupled to the FWD 520, even though the diode 520 may be formed on a substrate separate from the IGBT Main Switch 510. Further, since the turn-off time of an IGBT is shortened by coupling an Extraction Device 530 to the Extraction Plug 512 of the IGBT 510, including an Extraction Device 530 in the system 500 provides the extraction function when the IGBT 510 turns off. Therefore, it may be convenient to produce the IGBT Main Switch 510 with an Extraction Plug terminal 512 separately from a device that includes both an FWD as well as an Extraction Device, such as the device 530. Thus the system 500 may form a single package or module including one component having the IGBT Main Switch 510 and having another component 550, which includes the FWD 520 and the Extraction Device 530. Electrical connections are made within the system 500 as illustrated in FIG. 5 . For instance, a gate of the IGBT Main Switch 510 is electrically coupled to an input of the Extraction Device 530. The Extraction Plug terminal 512 of the IGBT Main Switch 510 is electrically coupled to an extraction input 532 of the Extraction Device 530. A collector of the IGBT Main Switch 510 is coupled to an output of the Extraction Device 530. To finish the connections, a cathode of the FWD 520 is coupled to a collector of the IGBT Main Switch 510, and the anode of the FWD 520 is coupled to an emitter of the IGBT Main Switch 510.
  • If the system 500 is created in a discrete package 560, it could be a three-terminal device with an input control terminal 562, a ground terminal 564, and an output terminal 566. Such a package 560 includes an IGBT 510 or Main Switch having an Extraction Plug terminal 512 that is coupled to a component 550. The component 550 includes an FWD 520 and an Extraction Device 530. This package 560 includes all of the components for a power device for driving an inductive load having a shortened turn-off time compared to typical IGBTs. In detail, the FWD 520 is effectively mandatory for any power switch operating with an inductive load. Embodiments of the invention further include the Extraction Device 530 to shorten the turn-off time of the voltage-controlled switch device with conductivity modulation 510. Although the Main Switch 510 is illustrated as being an IGBT, embodiments of the invention extend to any voltage-controlled switch device with conductivity modulation.
  • FIG. 6 is a cross-sectional diagram of an integrated device 600 including an FWD 610 and an Extraction Device 620 produced on a same semiconductor substrate, according to embodiments of the invention. In this example, the FWD 610 is a merged PN-Schottky structure. But, the FWD 610 may be any of several different types of FWDs. For example, the FWD 610 may be a PIN (p-type and n-type materials separated by an insulator) diode, and may or may not include materials for shortening carrier lifetimes, such as gold or platinum diffusions, electron or proton irradiations, etc. The FWD 610 may also be a Fast Recovery Diode, for example. Although the FWD 610 and the Extraction Device 620 of the integrated device 600 are formed on the same semiconductor die, they may be separated by a deep trench 640, which may be formed using standard fabrication techniques. The deep trench 640 separates the cathode of the FWD 520 (FIG. 5 ) from the substrate of the lateral PMOS in the Extraction Device 530. Such separation allows each device to operate virtually independent from one another. It is not necessary that the FWD 610 and the Extraction Device 620 be formed on the same die. In other embodiments the FWD 610 and the Extraction Device 620 may be electrically coupled to one another but formed on separate semiconductor dies. In the illustrated embodiment, the lateral PMOS Extraction Device 620 includes a thick gate oxide 105. The Extraction Device 620 is also “counter doped” at the surface of the semiconductor to create conditions for a suitable turn-on voltage, Vth. As represented in this cross section of FIG. 6 , the FWD 610 and the PMOS Extraction Device 620 structures could be formed and interspaced in the active area of the die. The device 600 is an example of the type of structure that could make the component 550 part of the device 500 of FIG. 5 .
  • Other structures in the integrated device 600 are conventional, such as a polysilicon gate 103, front metal 106, passivation layer 108, substrate 150, such as SiC or other wide bandgap material, N-type drift region 151, P-Wells 160, Schottky Metal 165, and counter-doped region 170.
  • FIG. 7 is a cross-sectional diagram of a device 700 illustrating an FWD 710, high-voltage termination 750, and a multi-cell PMOS Extraction Device 720 formed on any type of semiconductor, such as Silicon, SiC, wide-bandgap material, etc., according to embodiments of the invention. The placement of the Extraction Device 720 in the illustrated embodiment of FIG. 7 is outside of the High Voltage Termination 750 of the FWD 710, but this placement is not mandatory. The P-Wells 101 of the FWD 710 and Extraction Device 720 can very well operate together to provide a blocking voltage needed for the FWD. Other conventional components of the device 700 not referred to above include a gate 202, source 203, and drain 204 of the PMOS transistors in the Extraction Device 720.
  • FIG. 8 is a cross-sectional diagram of a lateral PMOS Extraction Device 800 that includes a PMOS transistor 810 coupled to a high voltage capacitor 820, according to embodiments of the invention. The capacitor 820 includes electrodes 822 separated by an insulating or dielectric layer 824. The PMOS transistor 810 includes a thin gate oxide 812. In some instances the thin gate oxide 812 is easier to produce than a thick gate oxide, used in previous examples, so the thin gate oxide may be preferable. The high voltage capacitor 820 is series coupled to the built-in capacitance of the thin gate oxide 812. As described above, when a PMOS transistor is used as the Extraction Device, the Extraction Device does not have any substantive function during the DC operation of the Main Switch, i.e., while the Main Switch is fully off or fully on. This means the Extraction Device 800 is OFF when the Main Switch is turned ON and it is ON when the Main Switch gets turned OFF. Given these characteristics, it is possible for an external capacitor with a relatively high voltage rating to be used to seamlessly protect the gate oxide of the PMOS Extraction Device, even when, such as in the Extraction Device 800, it has a thin gate oxide. This series circuit configuration is possible because the PMOS Extraction Device 800 operates only during the switching on and off of the Main Device (not illustrated in FIG. 8 ) to which it is coupled, and the switching control signals also cause the turn-on and turn-off of the PMOS transistor 810 in a seamless way. Further, by using a high-voltage external capacitor 820 in series with the capacitor formed by a polysilicon gate and the gate oxide 812 of the lateral PMOS 810, the total capacitance of the series connection of these two capacitances can be tailored to adjust the voltage spikes of the gate signal. This protection is important, especially in the case when the Main Switch is made on wide bandgap semiconductors, for which the gate oxides are very thin and therefore very sensitive to voltage spikes. The capacitance of the series connection of the capacitance of the gate oxide 812 of the PMOS 810 and the capacitor 820 itself may range from 1 pF to 800 pF, and more preferably from 1 pF to 100 pF. Of course, the specific values of the capacitance of the series connection will be implementation specific. The Extraction Device 800 is an example type of device that may be present in the device 550 and used for the Extraction Device 530 of FIG. 5 .
  • FIG. 9 is a cross-sectional diagram of a vertical PMOS Extraction Device 900, including a vertical PMOS transistor 910. The PMOS transistor 910 may be made on any type of semiconductor material. The PMOS transistor 910 in this embodiment has a thick gate oxide 105, which provides a high voltage rating for the PMOS transistor 910, exceeding that of a Main Switch to which it is connected. Also, the Extraction Device 900 includes a high-voltage rated capacitor 920 that is connected in series with the Gate-Drain capacitance of the vertical PMOS transistor 910. The capacitor 920 is formed of conductive plates 922 separated by an insulator 924. Even though in this illustration the high voltage capacitor 920 has similar dimensions as does the PMOS transistor 910, such as the Poly Gate Width of the vertical PMOS 910, in actuality, the high voltage capacitor 920 can be placed anywhere on the top of the PMOS die, or outside of it and properly wire-bonded to the control electrode of the Extraction Device.
  • Thus, the embodiments of the Extraction Devices illustrated in FIGS. 8 and 9 illustrate various options that may be used in implementing the Extraction Device, such as the Extraction Device 530 of FIG. 5 .
  • FIG. 10 is a top layout view of a device 1000 that includes an FWD 1010 integrated with an Extraction Device 1030 on a single semiconductor substrate. The FWD 1010 may be one of the FWDs described above. The FWD 1010 is surrounded by a high voltage termination 1020. An Extraction Device 1030 is placed outside the high voltage termination 1020 of the FWD 1010. The Extraction Device 1030 includes an input electrode 1032 for extraction, an output electrode 1034, and a control electrode 1036. This device 1030 is an example layout of the device 550 of FIG. 5 . If the device 1000 were coupled to a Main Switch, such as an IGBT having an Extraction Plug terminal, the control electrode 1036 would be coupled to a gate of the IGBT, the input (for extraction) electrode 1032 would be coupled to the Extraction Plug terminal of the IGBT, and the output electrode 1034 would be coupled to both a collector of the IGBT and to a cathode (not illustrated) of the FWD 1010. Finally, the anode (not illustrated) of the FWD 1010 would be coupled to the emitter of the IGBT. When so connected, the FWD 1010 of the device 1000 provides high voltage protection to the IGBT during turn-off while the Extraction Device 1030 substantially increases the turn-off speed of the IGBT.
  • FIG. 11 is a top layout view of a device 1100 including one or more FWDs 1110 and one or more Extraction Devices 1130 as described above. In this layout, the FWDs 1110 are interleaved with the Extraction Devices 1130 in the active area of the die. The electrodes of the Extraction Devices 1130 are not illustrated as they may be implementation specific, and may be placed as the design dictates. Also, the FWDs 1110 illustrated in the device 1100 may be coupled together to make one or more FWDs. In other words, FWDs 1110A and 1110B may be coupled to one another to make a single, larger FWD. In another embodiment, all of the FWDs 1110A, 1110B, 1110C, and 1110D, maybe be coupled together to make a single FWD for the entire device 1100. The same is true for the Extraction Devices 1130A, 1130B, and 1130C, which may be variously connected to one another to make one, two, or three separate Extraction Devices 1130. FIG. 11 illustrates the cellular or tessellated nature of the design in which multiple FWDs 1110 and Extraction Devices 1130 may be produced without affecting the functionality of the device. Further, the FWD 1110 and Extraction Device 1130 may be coupled to a one or more IGBTs as described above with reference to FIG. 10 .
  • FIG. 12 is a top layout view of a complete device 1200 that includes a voltage controlled Main Switch 1210 formed on a first semiconductor die coupled to an assisting device 1220 formed on a second semiconductor die. The Main Switch 1210 includes Extraction Plugs 700 placed inside an active area 1250. The active area 1250 of a semiconductor device is the area within which the main electrical function of the power semiconductor device is performed. Metallizations 107 connect the Extraction Plugs 700 to each other. A gate terminal 1212 of the Main Switch 1210 is also illustrated within the active area 1250. The Main Switch 1210 has its output on the backside of the die. The assisting device 1220 includes an FWD 1230 and a PMOS transistor 1240, which functions as an Extraction Device, as described above. The Extraction Device 1240 includes an input terminal 1242 for extraction, an output terminal 1244, and a control terminal 1246.
  • The Extraction Plugs 700 of the Main Switch 1210 are connected to one another through the metalizations 107 and also to the extraction input 1242 of the Extraction Device 1240 through a wire bond 1260. A wire bond electrically connects devices that are produced on two different substrates, where die metallizations cannot be used. Another wire bond 1282 couples the gate terminal 1212 of the Main Switch 1210 to the control electrode 1246 of the Extraction Device 1240. With reference to FIG. 5 , the FWD 1230 has its anode coupled to an emitter of the Main Switch 1210 through a wire bond 1264. The output of the Extraction Device 1240 is coupled by a wire bond 1266 to a collector of the Main Switch 1210, which, as described above, is located on the back side of the Main Switch 1210, and is therefore not visible in FIG. 12 . The output of the Extraction Device 1240 is also coupled to the cathode of the FWD 1230. This connection between the output of the Extraction Device 1240 and the cathode of the FWD 1230 may be an internal metallization within the assisting device 1220, and is therefore not separately illustrated in FIG. 12 . Thus, FIG. 12 is an example of a physical manifestation of the device 560 described above with reference to FIG. 5 , which includes both a Main Switch 510 and assisting device 550. If the complete device 1200 is a three terminal device, then the wire bond 1264 would be coupled to the ground terminal of the device, the wire bond 1266 would be coupled to the output terminal of the device, and the wire bond 1262 would be coupled to the control input terminal of the device. The wire bond 1260 would not need to be connected to a terminal of the complete device 1200 because the connection between the Extraction Plug terminal of the Main Switch 1210 and the input terminal 1242 of the Extraction Device 1240 need only be an internal connection.
  • FIG. 13 is a top assembly view of a device 1300 that is similar to the device 1200 of FIG. 12 . The same or similar features that were described with reference to FIG. 12 will not be repeated in the description of FIG. 13 , for brevity. The main difference between devices 1200 and 1300 is that the extraction plugs 700 of the device 1300 are formed outside of the high voltage termination 1250, whereas the Extraction Plugs 700 of the device 1300 are formed within the high voltage termination 1250. As described above, location of the Extraction Plugs 700 has little or no effect on their function to provide an access to the drift area of the semiconductor Main Switch through which the Extraction Device 1240 can expediently remove charge from while the Main Switch is turning off.
  • Power semiconductor switches having Extraction Plugs may be developed as a hybrid of the devices 1200 and 1300, with some Extraction Plugs 700 located inside the high voltage termination area 1250 and some Extraction Plugs 700 located outside the high voltage termination area within the same device itself.
    • Example Embodiments
  • In accordance to the present disclosure, an IGBT or other semiconductor device may take the following forms, along with their equivalents.
  • Example 1 is a Freewheeling diode integrated with a Forced Extraction Device. The Freewheeling diode may be of any kind, such as PIN, Schottky, etc.
  • Example 2 is a Freewheeling Diode coupled to an Extraction Device, which, in turn, is connected to a Main Switch that includes an Extraction Electrode or Extraction Plugs.
  • Example 3 is a Freewheeling Diode integrated with an Extraction Device, in which both the Diode and Extraction Device are made on Silicon.
  • Example 4 is a Freewheeling Diode integrated with an Extraction Device, in which both the Diode and Extraction Device are made on Wide Bandgap semiconductors.
  • Example 5 is a Freewheeling Diode integrated with a lateral PMOS Extraction Device, which, in turn, is connected to a Main Switch. The lateral PMOS Extraction Device has a thick gate oxide that withstands at least the blocking voltage of the Main Switch (IGBT).
  • Example 6 is a Freewheeling Diode integrated with a lateral PMOS Extraction Device. The lateral PMOS has a thin gate oxide and a high voltage rating capacitor that is connected in series with the capacitor of the controlling electrode of the Extraction Device.
  • Example 7 is a Freewheeling Diode integrated with a vertical PMOS Extraction Device which, in turn, is connected to a Main Switch. The vertical PMOS Extraction Device has a thick gate oxide that withstands at least the blocking voltage of the Main Switch (IGBT).
  • Example 8 is a Freewheeling Diode integrated with a vertical PMOS Extraction Device. The vertical PMOS has a thin gate oxide and a high voltage rating capacitor that is connected in series with the capacitor of the controlling electrode of the Extraction Device
  • Example 9 is a High Voltage Capacitor connected in series with the capacitor of the controlling electrode of the Extraction Device.
  • The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
  • These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (1)

What is claimed is:
1. A semiconductor device formed on a semiconductor substrate, the semiconductor having a first, second, third, and fourth terminals, the semiconductor device comprising:
a freewheeling diode coupled between the first and second terminals; and
an Extraction Device structured to be coupled to a conductivity modulation switch device through the third terminal, the Extraction Device further coupled to the second terminal and the fourth terminal.
US18/090,835 2020-10-19 2022-12-29 Integrated freewheeling diode and extraction device Abandoned US20230147486A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/090,835 US20230147486A1 (en) 2020-10-19 2022-12-29 Integrated freewheeling diode and extraction device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202063093701P 2020-10-19 2020-10-19
US17/496,658 US20220122964A1 (en) 2020-10-19 2021-10-07 Integrated freewheeling diode and extraction device
US18/090,835 US20230147486A1 (en) 2020-10-19 2022-12-29 Integrated freewheeling diode and extraction device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US17/496,658 Continuation US20220122964A1 (en) 2020-10-19 2021-10-07 Integrated freewheeling diode and extraction device

Publications (1)

Publication Number Publication Date
US20230147486A1 true US20230147486A1 (en) 2023-05-11

Family

ID=81185523

Family Applications (4)

Application Number Title Priority Date Filing Date
US17/339,832 Active US11764209B2 (en) 2020-10-19 2021-06-04 Power semiconductor device with forced carrier extraction and method of manufacture
US17/496,658 Abandoned US20220122964A1 (en) 2020-10-19 2021-10-07 Integrated freewheeling diode and extraction device
US18/090,835 Abandoned US20230147486A1 (en) 2020-10-19 2022-12-29 Integrated freewheeling diode and extraction device
US18/465,914 Abandoned US20230420449A1 (en) 2020-10-19 2023-09-12 Power semiconductor device with forced carrier extraction and method of manufacture

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US17/339,832 Active US11764209B2 (en) 2020-10-19 2021-06-04 Power semiconductor device with forced carrier extraction and method of manufacture
US17/496,658 Abandoned US20220122964A1 (en) 2020-10-19 2021-10-07 Integrated freewheeling diode and extraction device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US18/465,914 Abandoned US20230420449A1 (en) 2020-10-19 2023-09-12 Power semiconductor device with forced carrier extraction and method of manufacture

Country Status (3)

Country Link
US (4) US11764209B2 (en)
EP (2) EP4229682A1 (en)
WO (2) WO2022086879A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7748832B2 (en) * 2021-08-26 2025-10-03 ローム株式会社 Semiconductor Devices

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3838962A1 (en) * 1987-11-18 1989-06-08 Mitsubishi Electric Corp COMPOSED SEMICONDUCTOR ARRANGEMENT
JPH053205A (en) * 1991-01-25 1993-01-08 Fuji Electric Co Ltd Insulated gate bipolar transistor
US6147368A (en) * 1997-07-15 2000-11-14 Kabushiki Kaisha Toshiba Voltage-driven power semiconductor device
US6215634B1 (en) * 1998-04-10 2001-04-10 Fuji Electric Co., Ltd. Drive circuit for power device
US6222245B1 (en) * 1995-10-31 2001-04-24 Sgs-Thomson Microelectronics S.R.L. High capacity capacitor and corresponding manufacturing process
US20020153586A1 (en) * 2001-04-18 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP3557340B2 (en) * 1998-03-04 2004-08-25 株式会社東芝 Semiconductor stack
US20070158678A1 (en) * 2005-12-30 2007-07-12 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
WO2008096709A1 (en) * 2007-02-06 2008-08-14 Kabushiki Kaisha Toshiba Semiconductor switch and power converter to which the semiconductor switch is applied
US20090057832A1 (en) * 2007-09-05 2009-03-05 Denso Corporation Semiconductor device having diode-built-in IGBT and semiconductor device having diode-built-in DMOS
CN101431075A (en) * 2007-11-07 2009-05-13 株式会社电装 Semiconductor device and inverter circiut having the same
CN201681942U (en) * 2010-04-09 2010-12-22 杭州电子科技大学 Longitudinal trench SOI LDMOS unit
US20110309874A1 (en) * 2010-06-22 2011-12-22 Kazuyasu Takimoto Semiconductor switching system
US20120217541A1 (en) * 2011-02-24 2012-08-30 Force Mos Technology Co., Ltd. Igbt with integrated mosfet and fast switching diode
DE102011087598A1 (en) * 2011-03-04 2012-09-06 Mitsubishi Electric Corporation power module
CN102779836A (en) * 2012-07-13 2012-11-14 电子科技大学 Longitudinal power device with low specific on-resistance using high dielectric constant groove structure
US20130060499A1 (en) * 2011-09-07 2013-03-07 Fuji Electric Co., Ltd. Temperature measuring device of a power semiconductor apparatus
US20130134958A1 (en) * 2011-11-29 2013-05-30 Hiroshi Mochikawa Semiconductor switch and power conversion apparatus
CN103579172A (en) * 2012-08-03 2014-02-12 三菱电机株式会社 Power semiconductor device module
CN103683866A (en) * 2012-11-26 2014-03-26 崇贸科技股份有限公司 Transistor gate driver with charge pump circuit for power converter
DE112013007102T5 (en) * 2013-05-23 2016-03-03 Toyota Jidosha Kabushiki Kaisha IGBT with built-in diode
US20160233202A1 (en) * 2013-12-04 2016-08-11 Mitsubishi Electric Corporation Semiconductor device

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433271A3 (en) * 1985-07-22 1991-11-06 Hitachi, Ltd. Semiconductor device
US5113096A (en) * 1990-06-19 1992-05-12 Intel Corporation BiCMOS circuit
DE4324519C2 (en) * 1992-11-12 1994-12-08 Hewlett Packard Co NCMOS - a high performance logic circuit
JP3256636B2 (en) 1994-09-15 2002-02-12 株式会社東芝 Pressure contact type semiconductor device
US5751024A (en) * 1995-03-14 1998-05-12 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
US5894154A (en) 1996-12-05 1999-04-13 Lucent Technologies Inc. P-channel MOS transistor
JP4156717B2 (en) * 1998-01-13 2008-09-24 三菱電機株式会社 Semiconductor device
US7132712B2 (en) 2002-11-05 2006-11-07 Fairchild Semiconductor Corporation Trench structure having one or more diodes embedded therein adjacent a PN junction
US6861711B2 (en) 2003-01-03 2005-03-01 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6864537B1 (en) 2003-01-03 2005-03-08 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
WO2004066391A1 (en) * 2003-01-20 2004-08-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US7109551B2 (en) * 2003-08-29 2006-09-19 Fuji Electric Holdings Co., Ltd. Semiconductor device
JP4457810B2 (en) * 2004-03-04 2010-04-28 富士電機システムズ株式会社 Display device drive circuit
JP3698710B1 (en) * 2004-04-28 2005-09-21 三菱電機株式会社 Gradation improvement circuit and display system
TWI401749B (en) 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc Method for terminating high voltage super junction
US7235825B2 (en) * 2005-04-22 2007-06-26 International Rectifier Corporation IGBT with injection regions between MOSFET cells
JP5186095B2 (en) 2006-10-02 2013-04-17 株式会社日立製作所 Gate drive circuit
DE102007036147B4 (en) 2007-08-02 2017-12-21 Infineon Technologies Austria Ag Method for producing a semiconductor body with a recombination zone
JP5432751B2 (en) * 2010-02-01 2014-03-05 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
US8564097B2 (en) 2010-04-15 2013-10-22 Sinopower Semiconductor, Inc. Reverse conducting IGBT
WO2011129443A1 (en) 2010-04-15 2011-10-20 富士電機株式会社 Semiconductor device
JP5170208B2 (en) 2010-10-22 2013-03-27 富士電機株式会社 Current detection circuit for power semiconductor devices
US8680645B2 (en) * 2011-08-09 2014-03-25 Infineon Technologies Austria Ag Semiconductor device and a method for forming a semiconductor device
US8860132B2 (en) 2011-11-30 2014-10-14 Infineon Technologies Austria Ag Semiconductor device arrangement comprising a semiconductor device with a drift region and a drift control region
JP5745650B2 (en) 2011-12-15 2015-07-08 株式会社日立製作所 Semiconductor device and power conversion device
US9911838B2 (en) * 2012-10-26 2018-03-06 Ixys Corporation IGBT die structure with auxiliary P well terminal
US8686513B1 (en) 2012-10-26 2014-04-01 Ixys Corporation IGBT assembly having circuitry for injecting/extracting current into/from an auxiliary P well
JP5696713B2 (en) 2012-11-06 2015-04-08 株式会社デンソー Semiconductor device and inspection method thereof
US8928037B2 (en) * 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
WO2015173862A1 (en) 2014-05-12 2015-11-19 三菱電機株式会社 Power semiconductor device and method for manufacturing same
JP6022082B2 (en) 2014-07-11 2016-11-09 新電元工業株式会社 Semiconductor device and manufacturing method of semiconductor device
TWI692090B (en) * 2014-11-05 2020-04-21 日商索尼半導體解決方案公司 Solid-state imaging element and its manufacturing method
JP6261494B2 (en) 2014-12-03 2018-01-17 三菱電機株式会社 Power semiconductor device
KR20170121224A (en) * 2015-02-27 2017-11-01 디3 세미컨덕터 엘엘씨 Surface devices in vertical power devices
DE102015118322B4 (en) 2015-10-27 2024-04-04 Infineon Technologies Ag Bipolar transistor with superjunction structure
DE102016110035B4 (en) 2016-05-31 2020-09-10 Infineon Technologies Ag An electrical assembly comprising a bipolar switching device and a normally on wide bandgap transistor, and an electrical assembly comprising a bipolar switching device and a normally on junction field effect transistor comprising a semiconductor region of silicon carbide
DE102017105712B4 (en) 2017-03-16 2025-05-22 Infineon Technologies Austria Ag Transistor component
JP6911486B2 (en) 2017-04-20 2021-07-28 富士電機株式会社 Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3838962A1 (en) * 1987-11-18 1989-06-08 Mitsubishi Electric Corp COMPOSED SEMICONDUCTOR ARRANGEMENT
JPH053205A (en) * 1991-01-25 1993-01-08 Fuji Electric Co Ltd Insulated gate bipolar transistor
US6222245B1 (en) * 1995-10-31 2001-04-24 Sgs-Thomson Microelectronics S.R.L. High capacity capacitor and corresponding manufacturing process
US6147368A (en) * 1997-07-15 2000-11-14 Kabushiki Kaisha Toshiba Voltage-driven power semiconductor device
JP3557340B2 (en) * 1998-03-04 2004-08-25 株式会社東芝 Semiconductor stack
US6215634B1 (en) * 1998-04-10 2001-04-10 Fuji Electric Co., Ltd. Drive circuit for power device
US20020153586A1 (en) * 2001-04-18 2002-10-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20070158678A1 (en) * 2005-12-30 2007-07-12 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
WO2008096709A1 (en) * 2007-02-06 2008-08-14 Kabushiki Kaisha Toshiba Semiconductor switch and power converter to which the semiconductor switch is applied
CN101414816A (en) * 2007-09-05 2009-04-22 株式会社电装 Semiconductor device having diode-built-in igbt and semiconductor device having diode-built-in DMOS
US20090057832A1 (en) * 2007-09-05 2009-03-05 Denso Corporation Semiconductor device having diode-built-in IGBT and semiconductor device having diode-built-in DMOS
CN101431075A (en) * 2007-11-07 2009-05-13 株式会社电装 Semiconductor device and inverter circiut having the same
CN201681942U (en) * 2010-04-09 2010-12-22 杭州电子科技大学 Longitudinal trench SOI LDMOS unit
US20110309874A1 (en) * 2010-06-22 2011-12-22 Kazuyasu Takimoto Semiconductor switching system
US20120217541A1 (en) * 2011-02-24 2012-08-30 Force Mos Technology Co., Ltd. Igbt with integrated mosfet and fast switching diode
DE102011087598A1 (en) * 2011-03-04 2012-09-06 Mitsubishi Electric Corporation power module
US20130060499A1 (en) * 2011-09-07 2013-03-07 Fuji Electric Co., Ltd. Temperature measuring device of a power semiconductor apparatus
US20130134958A1 (en) * 2011-11-29 2013-05-30 Hiroshi Mochikawa Semiconductor switch and power conversion apparatus
CN102779836A (en) * 2012-07-13 2012-11-14 电子科技大学 Longitudinal power device with low specific on-resistance using high dielectric constant groove structure
CN103579172A (en) * 2012-08-03 2014-02-12 三菱电机株式会社 Power semiconductor device module
CN103683866A (en) * 2012-11-26 2014-03-26 崇贸科技股份有限公司 Transistor gate driver with charge pump circuit for power converter
DE112013007102T5 (en) * 2013-05-23 2016-03-03 Toyota Jidosha Kabushiki Kaisha IGBT with built-in diode
US20160233202A1 (en) * 2013-12-04 2016-08-11 Mitsubishi Electric Corporation Semiconductor device

Also Published As

Publication number Publication date
EP4229679A1 (en) 2023-08-23
WO2022086879A1 (en) 2022-04-28
WO2022086877A1 (en) 2022-04-28
EP4229682A1 (en) 2023-08-23
US20230420449A1 (en) 2023-12-28
US20220122962A1 (en) 2022-04-21
US20220122964A1 (en) 2022-04-21
US11764209B2 (en) 2023-09-19

Similar Documents

Publication Publication Date Title
JP3262579B2 (en) Metal oxide semiconductor field effect transistor circuit
JP3203814B2 (en) Semiconductor device
US8482031B2 (en) Lateral insulated gate bipolar transistors (LIGBTS)
US9070735B2 (en) Lateral power semiconductor transistors
US11127829B2 (en) Semiconductor device
CN102760733B (en) Semiconductor device
US10529708B2 (en) Conductivity modulated drain extended MOSFET
CN112563326A (en) MOS grid-controlled thyristor with parasitic diode and manufacturing method thereof
US8120107B2 (en) Semiconductor device internally having insulated gate bipolar transistor
US20230147486A1 (en) Integrated freewheeling diode and extraction device
US20080237630A1 (en) Semiconductor switch
US8803191B2 (en) Systems, devices, and methods with integrable FET-controlled lateral thyristors
US5621229A (en) Semiconductor device and control method
US7071516B2 (en) Semiconductor device and driving circuit for semiconductor device
JPH04261065A (en) semiconductor equipment
US8222671B2 (en) Power semiconductor devices
US10217765B2 (en) Semiconductor integrated circuit
CN113421922B (en) Three-dimensional IGBT with grid self-clamping function and manufacturing method thereof
US11282954B2 (en) LDMOS device with integrated P-N junction diodes
CN111261722B (en) Low reverse recovery charge lateral diode of integrated capacitor
US20230290869A1 (en) Dual Gate Power Semiconductor Device and Method of Controlling a Dual Gate Power Semiconductor Device
CN114664921A (en) IGBT with ESD (electro-static discharge) resistance function and manufacturing method thereof
CN113437143A (en) Three-dimensional MOS grid-controlled thyristor with parasitic diode and manufacturing method thereof
JPH0360160A (en) Self-arc-supressing thyristor

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION