JPH0661479A - Mos control thyristor in planar structure - Google Patents

Abstract

PURPOSE:To improve turn-on characteristics by integrating an n-channel MOSFET for controlling the injection of electrons from a cathode region to a base and at the same time providing a channel structure which is controlled by the p base between the cathode and the base. CONSTITUTION:In a thyristor where a cathode region 8 is provided on the first main surface of a semiconductor substrate and an anode region 2 is provided on a second main surface and a gate region 6, a p-channel MOSFET, and an n-channel MOSFET are formed being adjacent to the cathode region 8 near the first main surface, a layer 7 with the same conductivity type as the cathode region 8 is included between a layer 11 with the opposite conductivity type to the cathode region 8 and the gate region 6 contacting the cathode region 8. Then, the main electrode of a p-channel MOSFET is formed by the layer 11 and the gate region 6 and an n-channel MOSFET is formed by the layer 7 and a high-resistance layer 5. Also, a channel region 12 controlling the conduction state of electrons which are injected from the cathode region 8 is formed near the cathode region 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a p-channel MOSFET and an n-channel MOSFE in a planar structure MOS control thyristor.
The present invention relates to a planar structure MOS control thyristor in which T is formed by a common gate and a main thyristor can operate by an electrostatic induction effect.

[0002]

2. Description of the Related Art The basic structure of a MOS control thyristor is shown in FIG. The structure of FIG. 8 is a structure proposed by Temple of GE. In FIG. 8, 1 is an anode electrode, 2 is an anode region, 3 is an n buffer layer, 5 is a high resistance layer, 6 is a p base layer, 7 is the same conductivity type layer, 8 is a cathode region, 9 is a cathode electrode, 10 Is a MOS gate electrode,
11 is an opposite conductivity type layer. The opposite conductivity type layer 11 and the p base layer 6 also function as the main electrode region of the p channel MOSFET, and a pMOS channel is formed near the surface of the same conductivity type layer 7. Similarly, the same conductivity type layer 7 and the high resistance layer 5 also operate as a main electrode region of an n-channel MOSFET, and an nMOS channel is formed near the surface of the p base layer 6. The MOS gate electrode is nMOSFET, p
A MOSFET ^{common, n + (8) p (} 6) by applying a pulse voltage of positive and negative directions n - (5) n
^The main thyristor composed of ⁺ (3) p ⁺ (2) has a structure that is controlled to be turned on and off. In the structure of FIG. 8, the holes as carriers accumulated in the p base layer 6 are not extracted to the external gate like GTO, but the cathode electrode 9 is used.
Is short-circuited to the opposite conductivity type layer 11 which is short-circuited via the p-channel MOSFET. In short, a cathode short circuit structure is realized between the p base layer 6 and the cathode region 8 by the p channel MOSFET. On the other hand, the role of the n-channel MOSFET is that the n ⁻ high resistance layer 5 that acts as a second base layer with electrons from the same conductivity type layer 7 as the cathode region 8 is used.
To turn on the main thyristor by injecting through the channel of the nMOSFET.

FIG. 9 is a schematic sectional structural view of another conventional MOS control thyristor. The structure of FIG. 9 is, for example, Asea B
The structure is presented by the research group of rown Boveri. That is, for example, "Cur by F Bower et al.
rent-Handling and Switching Performance of MOS-Con
"trolled Thyristor (MCT) Structures",
It is disclosed in IEEE EDL Vol.12, No.6, June 1991.
The same components as those in FIG. 8 are designated by the same reference numerals. 9 is different from the structure of FIG. 8 in that an nMOSFET is not provided for each channel.
The point is that the buffer layer 3 is not provided. The structure of FIG. 9 is, so to speak, a structure in which a pMOSFET for short-circuiting the cathode is arranged in the periphery of the cathode 8 in a wide p base layer 6. Although it is structurally easier to realize multi-channel compared to FIG. 8, n for turn-on is used.
It is necessary to build a MOSFET separately. For example, in FIG.
0 has been proposed. The structure shown in Fig. 10 is "HIGH POWER MO" by C. Ronsisvale et al.
S-CONTROLLED-THYRISTOR USING THE PARALLEL CONTACTI
This is a schematic illustration of the structure disclosed in the paper entitled "NG TECHNOLOGY FOR DEVICES ON THE SAME WAFER", EPE FIRENZE, 1991, pp.267-269. Are given the same reference numbers.

The structural feature of FIG. 10 is that an n ⁺ region 16 is provided in the peripheral portion of the p base layer 6 and an n channel MOSFET is formed in the surface region at the end of the p base layer 6.

In the prior art MOS control thyristor shown in FIGS. 8 to 10, the main thyristor has a conventional four-layer structure thyristor or SCR structure. On the other hand, when the main thyristor portion is configured as an electrostatic induction thyristor and the control system is insulation control, the operation driving method is disclosed by Nishizawa, Tamamushi, and Gozawa in JP-A-1-278.
No. 119 (filed on April 30, 1988), the insulation control (MOS-Contro
lled) It is described that it is called an electrostatic induction thyristor.
Since the insulation control SI thyristor has a high gate current amplification factor, it can operate with a small gate signal. 60 MOS control SI thyristors with integrated gate capacitors only
Prototypes up to 0V-3A class, which can operate only with the gate capacitor C _G , have been published by Nishizawa, "SI Thyristor
s Hold Promise for Improved DCPower Transmission,
"PCI & Motor 'Con 88, Munich, West Germany 1988,
June 6-8, or a paper by Nishizawa, Tamamushi, "Recent D
evelopment and Future Potential of the Power Stati
c Induction (SI) Devices, "Proceedings of theThir
d International Conference on Power Electronics an
d Variable-SpeedDrives, Vol.291, pp.21-24, July 19
88.

Further, an example of the structure of a MOS control SI thyristor in which only the gate capacitor C _G and / or the p-channel MOS transistor for turn-off is integrated is disclosed by Nishizawa and Suzuki in JP-A-3-292770 or JP-A-3-292770. It is disclosed in Japanese Patent No. 292769.

However, when the electrostatic induction thyristor has a large current capacity, it is difficult to sufficiently drive it with a gate signal having a transient differential waveform via the gate capacitor. In order to uniformly turn on and drive the entire large-capacity SI thyristor, it is necessary to form the gate capacitor C _G by forming a gate oxide film on the gate over the entire wafer. The size of the MOS gate capacitor is substantially determined by the film thickness of the gate oxide film, but it is difficult to form it too thin. If the capacitance of the gate capacitor is large, the gate drive signal is added between the gate and the cathode, which is advantageous, but it is difficult to form the gate capacitor C _G larger than the capacitance C _GK between the gate and the cathode. As described above, in the case of a small capacity, it has been already confirmed that only the gate capacitor operates up to 600V-3A class.

Therefore, a MOS for stably turning on and off a large capacity thyristor.
A control thyristor configuration is desirable. Moreover, it is desirable that the production is easy by forming the planar. In addition, compared to the conventional MOS control thyristor,
A structure which is excellent in / dt and has a short turn-on time t _gt is desirable.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a planar structure MOS control thyristor in which a turn-off p-channel MOSFET and a turn-on n-channel MOSFET are integrated, and a cathode region and a cathode region are provided. (EN) A planar MOS control thyristor having a channel structure between two bases (high resistance layers) and capable of controlling a current flowing in the channel by a JFET effect or an electrostatic induction effect by a base or gate potential.

[0010]

An n-channel MOSFET for controlling injection of electrons from the cathode region to the second base (high resistance layer) is integrated, and the cathode and the second base (high resistance layer). 1) is provided with a channel structure controlled by a p-base (gate).

By adopting such a configuration,
The thyristor can be stably turned on by the n ^- channel MOSFET, and since it has a channel structure, di / dt at the time of turn-on can be set high and the turn-on time t _gt can be _shortened .

Therefore, the structure of the present invention is as follows. That is, the present invention comprises a cathode region on a first main surface of a semiconductor substrate, an anode region on a second main surface, and a gate region adjacent to the cathode region in the vicinity of the first main surface where the cathode region is formed. Area, p-channel MOSFE
In a planar MOS-controlled thyristor having T and n channel MOSFETs formed, the same conductivity as the cathode region is provided between the gate region and a region opposite to the cathode region formed in contact with the cathode region. Type layer is interposed, the opposite conductivity type region and the gate region respectively form a main electrode of a p-channel MOSFET having the same conductivity type layer as a channel, and the same conductivity type layer and the high resistance layer are formed. An n-channel MOSFET having both electrodes as main electrodes and the gate region as a channel is formed near the surface between them, and the cathode is provided near the cathode region in the direction perpendicular to the substrate from the cathode region toward the high resistance layer. A channel region that controls the conduction state of electrons injected from the region is formed, and the channel region is the gate region. Thus is substantially depleted sandwiched between,
The potential of the channel is changed by the electrostatic induction effect by the potential of the gate region,
The gate electrodes of the FET and the n-channel MOSFET are formed in common, and the gate electrode of the FET and the n-channel MOSFET are crossed over the same conductivity type region and the gate region from a part of the opposite conductivity type region via the insulating layer on the first main surface. It has a structure as a MOS-controlled thyristor having a planar structure, which is formed to extend to an upper part of a high resistance layer region, and a cathode electrode is formed by short-circuiting the cathode region and the opposite conductivity type region. .

[0013]

In the planar-structured MOS control thyristor according to the present invention shown in FIG. 1, the main thyristor portion is operated by the electrostatic induction thyristor, or the region where the base layer is thin is operated by the electrostatic induction effect and is formed relatively thick. Area is G
The same operation as TO or SCR is performed. The n-channel MOSFET formed near the surface controls the injection amount of electrons from the cathode. When electrons are injected into the second base (high resistance layer), holes are injected from the anode region into the high resistance layer, the p base region is positively charged, and electrons are emitted from the cathode region toward the channel region 12. Injection is started. When the injection of electrons into the second base (high resistance layer) 5 starts via the channel region 12, the n-channel MOSF
The ET may no longer be held in the on state. This is because the number of electrons injected from the cathode via the channel 12 is overwhelmingly large. However, there is no problem even if the n-channel MOSFET remains on. When the main thyristor is in the latch-up state,
The electron current from the cathode is channel region (12) and p
From the anode region 2 through the base layer 6 to the anode electrode 1
While the hole current from the anode region flows to the cathode region 8 via the p base layer 6 and the channel region (12).
To the cathode electrode 9.

At turn-off, p-channel MOSF
ET is turned on, while n-channel MOSFET
Is turned off. The holes accumulated in the p base layer 6 flow into the opposite conductivity type layer (11) through the channel region of the p channel MOSFET and are short-circuited to the cathode electrode 9. As a result, the diffusion potential of the n ⁺ p junction or the n ⁺ p ⁻ junction between the cathode / p base or the channel (12) rises, and the electron injection from the cathode region 8 is stopped. That is, as the potential of the p base layer 6 becomes higher, the potential in the channel region 12 rises and the electron injection from the cathode region 8 is blocked. This puts the main thyristor in a blocking state. In order to hold the main thyristor in the blocking state, the p-channel MOSFET must be held in the ON state, and the channel region 12 must be formed as a normally-off channel. At the same time, it is necessary to keep the n-channel MOSFET off. In order to keep the main thyristor conductive, it is necessary to keep the p-channel MOSFET off and the channel region 12 to be a conductive channel. In this case, it may be considered that the n-channel MOSFET only needs to be turned on when the turn-on is triggered.
It is desirable to keep the on-state because the on-resistance decreases when the electron current is made to flow widely over the entire wafer.

[0015]

First Embodiment FIG. 1 is a schematic cross-sectional structure diagram of a planar structure MOS control thyristor as a first embodiment of the present invention. In FIG. 1, 1 is an anode electrode, 2 is an anode region, 3 is a buffer layer, 5 is a high resistance layer, 6 is a gate (base) region, 7 is the same conductivity type layer, 8 is a cathode region, and 9 is a cathode region.
Is a cathode electrode, 10 is a MOS gate electrode, 11 is an opposite conductivity type layer, and 12 is a channel region. Reference numerals 14 and 15 are insulating layers. In particular, 14 is an n-channel or p-channel MO
It becomes a gate insulating film for SFET. p ⁺ opposite conductivity type layer 1
1 is electrically short-circuited by the n ⁺ cathode region 8 and the cathode electrode 9. A p channel is formed near the MOS interface of the n opposite conductivity type layer 7, and the p base (gate) region 6 is formed.
N channel is formed in the vicinity of the MOS interface. The p ⁺ opposite conductivity type layer 11 and the p base (gate) region 6 are pMOSFs.
The main electrode region of ET is formed, and the n-conductivity type layer 7 and the n ⁻ high resistance layer 5 form the main electrode region of nMOSFET. The channel region 12 need only be substantially depleted, and is formed as an n ⁻ layer or a p ⁻ layer. The electrons flowing in the channel region 12 may be flowing by the JFET effect that makes the narrow channel width controlled by the p base layers 6 on both sides substantially conductive, or may be controlled by the electrostatic induction effect by the potential barrier control. Good.

The structure shown in FIG. 1 has a conventional CMOS, D
It can be formed using a technique such as MOS or nMOS. The channel length of the MOSFET is formed to, for example, about 2 μm or less. The depth of the n ⁺ cathode region is, for example, about 5 μm or less, the thickness of the p ⁺ opposite conductivity type layer 11 is 2 μm or less, and the depth of the n same conductivity type layer 7 is 3 μm or less. The depth of the p base (gate) region is, for example, 10 μm or less. The channel region 12 is set to have a width and an impurity density that are sufficiently depleted by the diffusion potential of the p base layer 6. p-channel MOSFET, n-channel MOSFET
In the vicinity of the MOS interface, the surface of the n-conductivity type layer 7 and the surface of the p base (gate) region 6 are channel-doped in order to achieve a predetermined threshold voltage. The thickness of the insulating film 14 is preferably 1000 Å or less, for example.

The size of the first embodiment of the present invention is not limited to the above example, and it is desirable that the thickness of the cathode region 8, the p base layer 6 and the like be thin in order to realize miniaturization and a short channel. it is obvious.

[0018]

[Embodiment 2] FIG. 2 is a schematic cross-sectional structure diagram of a planar structure MOS control thyristor as a second embodiment of the present invention. In the structure of FIG. 2, the same components are
The same reference numerals as those of the embodiment are given and the description thereof will be omitted. The structural feature of the second embodiment is that the junction region between the n ⁺ cathode region 8 and the p base layer (gate region) is enlarged.
This means that the region in which the hole current flows when the main thyristor is in the on state is set wide. When the main thyristor is in the ON state, the electron current is mainly in the channel region 1
2 and the p base layer 6, and if the nMOSFET is in the ON state, the channel portion of the nMOSFET also flows.
On the other hand, the hole current only flows to the n ⁺ cathode region mainly through the n ⁺ (cathode) / p (base) layer junction via the p base layer. This is a p-channel MOSFET
Is in the off state. Therefore, in the structure of FIG.
The structure shown in FIG. 2 of the second embodiment is a structure in which electrons can widely flow over the entire wafer but hole current also widely flows. In FIG. 2, the width of the n ⁺ cathode region 8 is widened and the junction area with the p base layer 6 is set wide.

Further, in the structure of FIG. 2, an electrostatic induction buffer layer (n ⁺ n ⁻ n ⁺ ...) Is provided as a buffer layer. Regarding the electrostatic induction buffer layer, Japanese Patent Application No. 4 by Muraoka and Tamamushi
-Is disclosed. The region 4 is a buffer short-circuit layer, and is short-circuited with the anode region 2 at a pitch of about 2L _n (L _n is the diffusion length of electrons) or less.

The structure on the anode side is not limited to the structure via the buffer layer described above, and the structure of PN
Needless to say, the structure, the anode short structure, the SI anode short structure, the double gate structure, the MOS control structure, the Schottky short structure, or the like may be used, or the lifetime control may be combined.

FIG. 3 shows an example of a structure in which two planar-structured MOS control thyristors of the first embodiment of the present invention are arranged in parallel. In the planar-structure MOS-controlled thyristor of the present invention, n ⁺ cathode region 8, p ⁺ opposite conductivity type layer 11,
It suffices that a large number of n-conductivity-type layers 7 are formed in the p-base layer 6 and that the channel 12 is formed in the anode direction of the n ⁺ cathode region 8. Off p-channel MOSFET
However, it is easy to integrate. However, an n-channel MOSFET for stable turn-on of the entire main thyristor
As described above, it is necessary to integrate the above.
It is sufficiently possible to form the n-channel MOSFET simply between the same conductivity type layer 7 and the p base layer 6 and the n ⁻ high resistance layer 6. However, when configuring a large number of MOS control thyristors, it is desirable to arrange the n-channel MOSFETs at a predetermined pitch. FIG. 3 shows such an nMOS
It is an example of a multi-channel structure considering the arrangement of FETs. An n ⁺ drain shorting layer 13 is provided at a position where a depletion layer extending from the p base layers 6 on both sides reaches. The electrons injected from the n-conductivity type layer 7 conduct through the channel near the surface of the p base layer 6 and reach the n ⁻ layer 6. This n ^- layer 6
N ⁺ acts as a drain for absorbing electrons injected into the
It is the drain short-circuit layer 13. The n ⁺ drain short-circuit layer 13 is shared in potential with the n buffer layer 3 or the anode electrode 1. The n ⁺ drain short-circuit layer 13 shown in FIG.
May be provided for each unit cell of the MOS control thyristor, but p including several unit cells is taken into consideration in consideration of integration density.
It may be provided for each base layer 6. The point is that a large number of multi-cells can be stably turned on, and the arrangement configuration for that can be determined in consideration of the current capacity.

FIG. 4 shows an example of a structure in which the upper MOS insulating layer 14 of the n ⁺ drain shorting layer 13 is formed thicker in the structure of FIG. 10 'is a MOS gate electrode. Considering the operation of a high breakdown voltage n-channel MOSFET,
The channel length L _N is the width L near the surface of the p base layer 6.
Determined by _N , p base layer 6 to n ⁺ drain shorting layer 1
The n ⁻ high resistance layer 5 toward 3 is substantially depleted. Due to the operation of the p-channel MOSFET, the transconductance G _m is inversely proportional to the gate-drain capacitance. That is, it is desirable that the capacitance between the gate and the drain be smaller than the capacitance between the gate and the channel or the gate and the source. Therefore, the structure of FIG. 4 has a small gate-drain capacitance. This n channel M
By devising to improve the performance of the OSFET, the turn-on speed of the main thyristor can be improved.

[0023]

[Third Embodiment] FIG. 5 is a schematic cross-sectional structure diagram of a planar structure MOS control thyristor as a third embodiment of the present invention. The structural difference between the first embodiment (FIG. 1) and the second embodiment (FIG. 2) is that the n ⁺ cathode region 8 is not in direct contact with the p base (gate) region 6, but the n base layer 7 ″ is The intervening points and the impurity density of the p base layer 6 are described in Example 1,
2, the channel region 12 is clearly defined and the nMOS channel region 6'in the vicinity of the surface of the p base layer 6 has an impurity density set relatively low with respect to the p base layer 6 to form an nMOSFET. The point is that the channel region of is clearly defined. In the state in which a negative voltage pulse is applied to the MOS gate electrode 10, holes flow from the p ⁺ layer 6 into the nMOS channel region 6'and pMOSFE
Since the channel region 7 ′ of T is inverted to form the p-inversion layer, the holes accumulated in the p ⁺ base layer 6 effectively flow into the opposite conductivity type layer 11 and the cathode region 8 is affected by the cathode electrode. Short circuited. That is, p-channel MOSFET
As a result, the gate and the cathode are substantially short-circuited. When a positive voltage pulse is applied to the MOS gate electrode 10, the pMOSFET is turned off,
On the other hand, an n inversion layer is formed in the nMOS channel region 6 ′, and electrons in the n ⁺ cathode region 8 are injected into the n ⁻ high resistance layer 5 through the same conductivity type layer 7 and injected from the anode region 2. The holes are accumulated in the p ⁺ base (gate) layer 6,
An operation of lowering the barrier height for electrons in the depleted channel region 12 or opening the channel width is performed. As a result, n ^{+ from the} cathode region 8
The operation of injecting electrons into the channel region 12 via the base layer 7 ″ is started, and finally, the operation shifts to the latch-up state. In the structure of the third embodiment, in the latch-up state, the electrons are mainly the channel. Region 12 and nMO
While flowing through the SFET channel region 6 ', holes flow from the channel region 12 and the gate region 6 to the n ⁺ cathode region 8 through the n base layer 7 "and the same conductivity type layer 7.

In the structure of the third embodiment, the electron conduction region is narrowed by the amount of the high impurity density of the p base layer 6 formed, but this is due to the electrostatic induction effect of the potential barrier height in the channel region 12. Since the controllability is improved, the injection efficiency from the n ⁺ cathode region 8 is high. Further, since the n base layer 7 ″ is interposed,
⁺ Prevents the breakdown voltage between the cathode region 8 and the cathode region 8 from decreasing. Further, if the impurity density of the n base layer 7 ″ and the layer 7 of the same conductivity type in the vicinity thereof is formed low, the breakdown voltage is further improved, and
^{+ The} structure is such that the amount of electrons injected from the cathode region 8 also increases. By setting the impurity density and dimensions of the channel region 12 in the third embodiment, the p ⁺ base layer 6
Substantially depleted only by the diffusion potentials of and, it is possible to form a potential barrier sufficiently high for electron injection from the n ⁺ cathode region 8. Alternatively, if the channel length of 12 is set long, the J-FET effect can be provided. In the structure of FIG. 5, the p base layer 6 is shown as a relatively large region, but by forming the p base layer 6 as a whole and making the p ⁺ layer 6 small, the buried gate SI thyristor process and the CMOS process can be performed. Alternatively, a finer structure can be formed by combining DMOS (nMOS) processes.

FIG. 6 shows an example of a structure in which two planarly controlled MOS control thyristors of the third embodiment shown in FIG. 5 are arranged in parallel. An n ⁺ drain shorting layer 13 is provided and has the same structure as that shown in FIG.

[0026]

[Fourth Embodiment] FIG. 7 is a schematic cross-sectional structural view of a planar structure MOS control thyristor as a fourth embodiment of the present invention. The reason why the planar structure is shown in FIG. 7 is that the main thyristor portion is configured as an SI thyristor with a buried gate structure, but an n-channel MOSFET and a p-channel MO are used.
This is because all the SFETs are formed along the first main surface. The same components as those in Examples 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted. The structural feature of FIG. 7 is that the gate region 6 of the main thyristor is formed as a normally-off buried gate structure. In order to realize normally-off, the channel region between the p ⁺ buried gates is substantially depleted and a potential barrier is formed, and the barrier height is sufficient to block electron injection from the n ⁺ cathode region 8. ing. 7 ″ is an n base layer,
7'is a pMOS channel region. 6'is an nMOS channel region. Regions 7, 7'and 7 "can be formed simultaneously by epitaxial growth after buried gate diffusion.

The structure shown in the fourth embodiment can be manufactured by combining a normal buried gate and SI thyristor process with nMOS, DMOS, CMOS technology as a planar technology.

The structure shown in the fourth embodiment can also be made in parallel by multichanneling. nMOS
The arrangement of the FETs should be configured in consideration of the integration density as in the other embodiments.

It is needless to say that the structures of the first to fourth embodiments described above may have the n-type and p-type conductivity types opposite to each other. In that case, nMOSFET, pMOS
The role of the FET is also reversed, the pMOSFET is for turning on and the nMOSFET is for turning off.

The main thyristor portion disclosed in the present invention is not limited to the above-mentioned four-layer structure thyristor, SCR structure or GTO structure, but may be a buried gate GTO, a buried gate SI thyristor or a double gate S.
It may be an I thyristor, a double gate GTO, or the like.
Further, a planar structure or vertical structure MOS is provided on the anode side.
It is also clear that control structures may be introduced.

It is also possible to use an n-buffer structure or, in another embodiment, an electrostatic induction (SI) buffer structure.

Alternatively, an anode short circuit structure or an SI short circuit structure may be used.

[0033] The high-resistance layer 5 in the above embodiment the n ^- in the layer, but not limited thereto, p ^- layer may be i layer. Considering the speed at which the depletion layer spreads, it is desirable that the high resistance layer 5 be a p ⁻ layer for an n base (gate) structure in which the conductivity types of p and n are opposite.

[0034]

According to the structure of the planar-structure MOS-controlled thyristor of the present invention, compared with the conventional MOS-controlled thyristor, it has a channel structure that can be controlled by the JFET effect or the electrostatic induction effect.
The on-time can be short-circuited. For example, 4500V-
It is possible to obtain the following turn-on time t _gt 0.5μs in the 400A class.

Furthermore, since such a channel structure is provided, di / dt at the time of turn-on can be increased, and a MOS control thyristor with a high current rise can be obtained.

Even when the main thyristor is an electrostatic induction thyristor, there is an advantage that the nMOSFET and pMOSFET can be realized with extremely high integration density.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structural diagram of a planar structure MOS control thyristor as a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional structure diagram of a planar structure MOS control thyristor as a second embodiment of the present invention.

FIG. 3 is a planer structure MOS according to a first embodiment of the present invention.
It is an example of a structure in which two control thyristors are arranged in parallel.

FIG. 4 is another structural example in which the MOS control thyristors having the planar structure as the first embodiment of the present invention are arranged in parallel.

FIG. 5 is a schematic cross-sectional structure diagram of a planar structure MOS control thyristor as a third embodiment of the present invention.

6 is an MO of the planar structure of Example 3 shown in FIG.
It is a structural example which arranged two S control thyristors in parallel.

FIG. 7 is a schematic sectional structural view of a planar structure MOS control thyristor as a fourth embodiment of the present invention.

FIG. 8 is a basic structural diagram of a conventional MOS control thyristor.

FIG. 9 is a schematic cross-sectional structure diagram of another conventional MOS control thyristor.

10 is an nMO for turn-on in the conventional example of FIG.
This is a configuration example in which an SFET is separately manufactured.

[Explanation of symbols]

1 Anode electrode 2 Anode region 3 Buffer layer 3'Static induction buffer layer (n ⁺ n ^- n ⁺ ...) 4 Buffer short-circuit layer 5 High resistance layer 6 Gate region (base region) 6'nMOS channel region 7 Same conductivity type layer 7 ′ pMOS channel region 7 ″ n base layer 8 cathode region 9 cathode electrode 10, 10 ′ MOS gate electrode 11 opposite conductivity type layer 12 channel region 13 n ⁺ diffusion layer 14, 15 insulating layer 16 n ⁺ region

Claims (1)

[Claims] 1. A semiconductor substrate having a cathode region on a first main surface and an anode region on a second main surface, the gate being adjacent to the cathode region in the vicinity of the first main surface where the cathode region is formed. Planar structure MOS in which region, p-channel MOSFET and n-channel MOSFET are formed
In the control thyristor, a layer of the same conductivity type as the cathode region is interposed between the gate region and a region of opposite conductivity type formed in contact with the cathode region, and the region of opposite conductivity type. And the gate region respectively form a main electrode of a p-channel MOSFET whose channel is the layer of the same conductivity type, and the gate region is formed between the layer of the same conductivity type and the high resistance layer as the main electrode. N-channel MO as a channel
An SFET is formed near the surface, and a channel region is formed near the cathode region in a direction perpendicular to the substrate from the cathode region toward the high resistance layer, the channel region controlling a conduction state of electrons injected from the cathode region, The channel region is sandwiched by the gate regions and is substantially depleted, the potential in the channel is changed by the electrostatic induction effect by the potential of the gate region, and the p-channel MOSFET and the n-channel MOSFET are
Gate electrodes are formed in common, and a part of the opposite conductivity type region is formed on the first main surface via an insulating layer to cross over the same conductivity type region and the gate region and the high resistance layer region of A planar structure MOS control thyristor, wherein the cathode electrode is formed to extend to an upper portion, and the cathode electrode is formed by short-circuiting the cathode region and the opposite conductivity type region.