KR102509083B1 - MCT device having uniform turn-off characteristics and method for manufacturing the same - Google Patents

Abstract

The present invention forms a uniform and short-length off-FET channel using a self-align process of a spacer formation and recession method, thereby improving the current driving capability and device operation of the off-FET. The uniformity of can be improved. Also, according to the present invention, an MCT device that is turned off at a low gate voltage or a gate voltage of 0V can be manufactured.

Description

MCT device having uniform turn-off characteristics and method for manufacturing the same

The present invention relates to a power semiconductor device, and more particularly, to a MOS-controlled thyristor (MCT) device.

A MOS controlled thyristor (MCT) is a device that integrates a Metal-Oxide-Semiconductor (MOS) gate into a thyristor of a PNPN junction structure and controls the turn-on and turn-off of the thyristor with a gate voltage.

Compared to other power semiconductor devices such as MOSFET (Metal-Oxide-Semiconductor field-effect transistor), BJT (bipolar junction transistor), IGBT (insulated-gated bipolar transistor), MCT has high current driving capability and low on-state. - It has excellent electrical characteristics such as loss of state voltage.

In addition, since MCT drives on-off by applying a voltage to a MOS gate with high impedance, power loss is very small and switching loss is very small compared to GTO (gate turn-off thyristor), which drives on-off with existing current. It has the advantage of being small and easy to implement a driving circuit.

In addition, MCT has excellent timing accuracy compared to the spark gap previously used as a switch in pulse power power systems such as high-energy detonators and electromagnetic propulsion devices, as well as simple triggering and pulse-life ), has excellent stability and durability, and has the advantages of small size / light weight and low cost.

On the other hand, since the MCT is maintained in the on-state even if the gate power is shorted by the regenerative action of the PNP BJT and NPN BJT inside the thyristor, the turn-off performance determines the current driving capability of the device. .

The MCT device integrates a MOS Gate into a PNPN thyristor structure, turns on the thyristor by turning on the on-FET, and turns the thyristor off by turning on the off-FET. Since the current driving capability is determined, an off-FET having a short channel length must be formed.

In addition, in order to prevent device damage during turn-off, off-FETs must have uniform characteristics throughout the MCT device, and for this purpose, formation of off-FETs with a uniform channel length is required.

In addition, in the manufacture of the MCT device, in order to have a high breakdown voltage characteristic and high emitter injection characteristics of the thyristor, a high concentration of the upper base (P-base in the case of n-MCT) and A high concentration of the top emitter (N-emitter in the case of n-MCT) is required.

However, such a high concentration of P-base and N-emitter causes the threshold voltage (Vth) of on-FET to have a positive (+) value and the threshold voltage (Vth) of off-FET to be negative (-). The large shift not only deteriorates the turn-off performance of the MCT, but also complicates the gate driving circuit.

An object of the present invention to solve the above problems is an MCT device having an off-FET channel formed with a uniform short length to improve current driving capability, uniformity of device operation and turn-off performance, and a manufacturing method thereof is to provide Another object of the present invention is to provide an MCT device that is turned off at a low gate voltage or a gate voltage of 0V and a manufacturing method thereof.

The foregoing and other objects, advantages and characteristics of the present invention, and methods of achieving them will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings.

A method of manufacturing an MCT device according to an aspect of the present invention for achieving the above object is a base region of a first conductivity type doped with impurities of a first conductivity type in a substrate and a first conductivity type in the base region of the first conductivity type. forming an emitter region of a second conductivity type doped with impurities of a second conductivity type; forming a spacer on a side surface of an oxide film formed on the substrate and exposing an upper portion of the emitter region of the second conductivity type; An impurity of the first conductivity type is ion-implanted into the emitter region of the second conductivity type exposed upward by the spacer to form a drain region of the first conductivity type of an off-FET, thereby forming the second conductivity type forming a channel region of an off-FET defined between a bonding surface of an emitter region of the first conductivity type and a bonding surface of the drain region of the first conductivity type; ion-implanting impurities of the first conductivity type into an upwardly exposed channel region of the off-FET according to the removal of the spacer; after removing the oxide film, forming a gate electrode layer on the substrate, exposing the drain region of the first conductivity type and the emitter region of the second conductivity type upward; forming a doped region of a second conductivity type by ion-implanting impurities of the second conductivity type into the emitter region of the second conductivity type upwardly exposed by the gate electrode layer; and an upper metal layer used as a cathode electrode on the gate electrode layer, the drain region of the first conductivity type, and the doped region of the second conductivity type, and a lower metal layer used as an anode electrode on the lower surface of the substrate. Formation may be included.

In an embodiment, in the forming of the channel region of the off-FET, the photoresist pattern formed on the spacer and the emitter region of the second conductivity type exposed upward by the spacer is used as an ion implantation mask. Thus, an ion implantation process of implanting impurities of the first conductivity type into an emitter region of the second conductivity type upwardly exposed by the spacer and the photoresist pattern may be performed.

In an embodiment, the channel region of the off-FET is formed below the spacer in a lateral direction between a junction surface of the emitter region of the second conductivity type and a junction surface of the drain region of the first conductivity type. can

In an embodiment, the step of ion-implanting the first conductivity type impurity into the channel region of the off-FET may include removing the spacer using an isotropic etching process; and ion-implanting impurities of the first conductivity type into an upper exposed channel region of the off-FET by the isotropic etching process, thereby adjusting a turn-on voltage of the off-FET.

In an embodiment, the impurity of the first conductivity type to be ion-implanted into the channel region of the off-FET is an impurity of the first conductivity type, and the ion implantation amount of the impurity of the first conductivity type is 1×10 ¹¹ to 1 ×10 ¹³ cm ^-2 may be.

In an embodiment, the ion-implanting of the first conductivity type impurity into the channel region of the off-FET may include further removing the spacer and the oxide layer using an etching process; forming another oxide layer on an upper surface of the substrate exposed by removing the spacer and the oxide layer; Forming another photoresist pattern formed on the different oxide film between a base region of the first conductivity type and a base region of another first conductivity type adjacent to the base region of the first conductivity type. ; and ion-implanting impurities of a first conductivity type into a channel region of the off-FET and a channel region of an on-FET adjacent to the channel region of the off-FET by using the other photoresist pattern as an ion implantation mask. A step of performing an ion implantation process may be included.

In an embodiment, the channel region of the on-FET may be a region under the surface of the base region of the first conductivity type.

In an embodiment, the ion-implanting of the first conductivity type impurity into the channel region of the off-FET may include further removing the oxide layer and the spacer using an etching process; forming another oxide layer on the entire surface of the substrate exposed to the upper side according to the removal of the oxide layer and the spacer; and ion-implanting impurities of a first conductivity type into a channel region of the off-FET and a channel region of the on-FET adjacent to the channel region of the off-FET to form a threshold voltage adjusting layer on the entire surface of the substrate. can include

In an embodiment, when the first conductivity type impurity is a p-type impurity, the second conductivity type impurity is an n-type impurity, and when the first conductivity type impurity is an n-type impurity, the second conductivity type impurity is The type impurity may be a p-type impurity.

An MCT device according to another aspect of the present invention includes an emitter layer of a first conductivity type doped with impurities of a first conductivity type and an emitter layer of the second conductivity type disposed on the emitter layer of the first conductivity type doped with impurities of the second conductivity type. a substrate including a second conductivity type base layer; a base region of a first conductivity type disposed in the second conductivity type base layer; an emitter region of a second conductivity type disposed in the base region of the first conductivity type; a doped region of the second conductivity type disposed in the emitter region of the second conductivity type and a drain region of the first conductivity type of an off-FET surrounding the doped region of the second conductivity type; disposed between the junction surface of the drain region of the first conductivity type and the junction surface of the emitter region of the second conductivity type in the emitter region of the second conductivity type, and doped with impurities of the first conductivity type. the channel region of an off-FET; an on-disposed between the junction surface of the emitter region of the second conductivity type and the junction surface of the base region of the first conductivity type so as to be adjacent to the channel region of the off-FET in the base region of the first conductivity type; the channel region of the FET; a gate electrode layer disposed on the entire surface of the substrate and having an opening exposing the doped region of the second conductivity type and the drain region of the first conductivity type upward; a cathode electrode layer disposed on the doped region of the second conductivity type and the drain region of the first conductivity type, which are exposed upward through the gate electrode layer and the opening, with an interlayer insulating film interposed therebetween; and an anode electrode layer disposed on the lower surface of the substrate.

In an embodiment, in order to improve electrical characteristics of the off-FET and the on-FET, all or part of the channel region of the off-FET and the channel region of the on-FET are doped with impurities of the first conductivity type. It can be.

In an embodiment, the channel region of the off-FET is an oxide film formed on the base layer of the second conductivity type, a spacer formed on a side surface of the oxide film, and a photoresist pattern formed on the emitter region of the second conductivity type. It can be formed by a self-aligned process using.

In an embodiment, the doped region of the second conductivity type, the drain region of the first conductivity type, the off-FET channel region, and the on-FET channel region extend in a line shape when viewing the substrate from above. The opening of the gate electrode layer has a line shape to upwardly expose a portion of the doped region of the second conductivity type and the drain region of the first conductivity type extending in the line shape when the substrate is viewed from above. can have

In an embodiment, when viewing the substrate from above, the second conductivity type emitter region has a circular shape, and the first conductivity type off-FET channel region has a circular shape at an end of the second conductivity type emitter region. wherein the second conductivity type doped region is spaced apart from the on-FET channel region with the off-FET channel region interposed therebetween, and the base region of the second conductivity type exposed to the surface of the substrate is the on-FET channel region. It is spaced apart from the off-FET channel region at a predetermined distance with the FET channel region interposed therebetween, and the opening of the gate electrode layer, when viewing the substrate from above, is formed between the doped region of the second conductivity type and the doped region of the first conductivity type. It may have a circular shape exposing a portion of the drain region upward.

In an embodiment, when viewing the substrate from above, the second conductive base layer exposed to the surface of the substrate has a circular shape, and the channel region of the on-FET exposed to the surface of the substrate extends to the surface of the substrate. It has a circular shape surrounding the exposed second conductivity type base layer, the channel region of the off-FET has a circular shape surrounding the on-FET channel region, and the drain region of the first conductivity type has the off-FET channel region. Surrounding the channel region of the FET, the opening of the gate electrode layer,

When viewed from above the substrate, a portion of the doped region of the second conductivity type and the drain region of the first conductivity type may be exposed upward.

In an embodiment, when the substrate is viewed from above, the emitter region of the second conductivity type has an octagonal shape, and the off-FET channel region of the first conductivity type is an end portion of the emitter region of the second conductivity type. has an octagonal band shape, the second conductivity type doped region is spaced apart from the on-FET channel region with the off-FET channel region interposed therebetween, and the second conductivity type base region exposed to the surface of the substrate is It is spaced apart from the off-FET channel region by a predetermined distance with the on-FET channel region interposed therebetween, and the opening of the gate electrode layer, when viewed from above the substrate, connects the doped region of the second conductivity type with the first conductive region. A part of the mold's drain region may be exposed upward.

In an embodiment, the base region of the second conductivity type exposed to the surface of the substrate has a circular shape, and the emitter region of the octagonal shape of the second conductivity type and the off-FET channel region of the octagonal band shape have the shape of the octagonal shape. It may have a concave side at a portion adjacent to the base region of the second conductivity type.

In the manufacturing process of the MCT device of the present invention, a uniform and short-length off-FET channel is formed using a self-aligning process of a spacer formation and recession method, so that the off-FET It is possible to improve the current driving capability and the uniformity of device operation.

In addition, the present invention not only improves the turn-off performance of the MCT by turning on the off-FET at a low gate voltage by selectively performing channel ion implantation into the channel region of the off-FET. , the MCT device can be turned off at a gate voltage of 0V by forming an off-FET channel of a depletion mode.

In addition, in the present invention, off-FETs and on-FETs are disposed in all unit cells of the MCT device, and the channel length of the off-FETs is uniformly formed when viewed from a plane, so that the self-alignment process is uniform. It is possible to fabricate an MCT device having the same performance.

1A is a schematic diagram showing a cross-sectional structure of a unit cell of a general n-type MCT device.
Figure 1b is a diagram showing an equivalent circuit of the MCT element shown in Figure 1a.
2 to 11 are cross-sectional views for explaining a manufacturing process of an MCT device according to an embodiment of the present invention.
12 and 13 are cross-sectional views for explaining another embodiment of a process for ion-implanting p-type impurities into the off-FET channel region of FIGS. 7 and 8 .
14 is a plan view of the MCT device manufactured according to the first embodiment of the present invention viewed from above in a state in which a gate insulating film, an interlayer insulating film, and an upper metal layer are removed.
15 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line D-D' shown in FIG. 14;
16 is a top plan view of a gate electrode layer according to a second embodiment of the present invention.
FIG. 17 is a top plan view of the MCT element in a state in which a gate insulating film disposed below the gate electrode layer shown in FIG. 16, an interlayer insulating film disposed above the gate electrode layer, and an upper metal layer are removed.
FIG. 18 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line AA′ shown in FIG. 17 in a state where the gate electrode layer shown in FIG. 16 is removed.
19 is a top plan view of a gate electrode layer according to a third embodiment of the present invention.
FIG. 20 is a top plan view of the MCT element in a state in which a gate insulating film disposed under the gate electrode layer shown in FIG. 19, an interlayer insulating film disposed thereon, and an upper metal layer used as a cathode are removed.
FIG. 21 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line BB′ shown in FIG. 20 .
22 is a top plan view of a gate electrode layer according to a fourth embodiment of the present invention.
FIG. 23 is a top plan view of the MCT element in a state in which a gate insulating film disposed below the gate electrode layer shown in FIG. 22, an interlayer insulating film disposed above, and an upper metal layer used as a cathode are removed.
24 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line C-C' shown in FIG. 23;

Hereinafter, an MCT device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Widths and thicknesses of layers or regions shown in the accompanying drawings are somewhat exaggerated to aid understanding of the present invention, and the same reference numerals are interpreted as the same elements throughout the detailed description.

First, to aid understanding of the present invention, a general MCT device will be briefly described with reference to FIGS. 1A and 1B, and then an MCT device according to an embodiment of the present invention will be described in detail.

1A is a schematic diagram showing a cross-sectional structure of a unit cell of a general n-type MCT device, and FIG. 1B is an equivalent circuit of the MCT device shown in FIG. 1A.

Referring to FIGS. 1A and 1B , the device structure of the MCT is similar to that of the IGBT, but has a triple diffusion structure further including a p-MOSFET (off-FET) in addition to an n-MOSFET (on-FET).

MCT turn-on process

The turn-on process of MCT is as follows.

When a voltage higher than the threshold voltage (Vth) of the on-FET is applied to the gate while the (+) voltage is applied to the anode, a channel is formed just below the surface of the P-base region and the on-FET turns on. - Come on.

The electron current flowing through the channel enters the N-base of the PNP BJT (P+/N-base/P-base), lowers the potential barrier of the junction (J1) between the P+ layer and the N-base, and lowers the lower image. Holes flow in from the terminal (lower P+) to turn on the PNP transistor.

The hole current of the PNP transistor flows into the NPN BJT (N-emitter/P-base/N-base) to break the potential barrier at the junction between the N-emitter (N-well) and the P-base (J3). lower, and electrons flow in from the upper emitter (N-emitter, ie N-well) to turn on the NPN BJT.

This electron current flows into the base of the PNP BJT again and turns on the PNPN thyristor. The turn-on process of the thyristor described above is called "regenerative action".

MCT turn-off process

The turn-off process of MCT is as follows.

When a negative voltage greater than the threshold voltage of the off-FET is applied to the gate when the MCT is in the on-state, the off-FET is turned on, which forms another path for holes to flow, forming the P-base of the holes are erased.

As a result, the potential barrier of the bonding surface J3 is raised, electron injection from the N-emitter (N-well) is stopped, and the NPN BJT is turned off to stop the regenerative operation of the thyristor. Electrons remaining in the N-base are annihilated by recombination, so the MCT is turned off.

In the MCT device described above, turn-off performance determines current driving capability of the device, and for this purpose, an off-FET having a short channel length must be formed.

In addition, in order to prevent device damage during turn-off, off-FETs must have uniform characteristics throughout the MCT device, and for this purpose, formation of off-FETs with a uniform channel length is required.

The present invention designs an off-FET with a short channel length that determines the current driving capability of an MCT device to have the same environment in all areas of the MCT device, and uses a self-alignment process of a spacer formation and recession method. By forming a channel region of the off-FET, current driving capability and uniformity of device operation are improved.

In addition, since the present invention can selectively proceed with channel ion implantation into the channel region of the off-FET, the turn-off performance of the MCT can be improved by turning on the off-FET at a low gate voltage, and at the same time, the 0V gate It can also be turned off at voltage.

Example 1 of a method for manufacturing an MCT device

In the following description, an n-MCT of an n-type lower base (N-base) will be described as an example, but if the types of all impurities (impurity or dopant) are reversed, it becomes a p-MCT device. That is, when the first conductivity type impurity is a p-type impurity, the second conductivity type impurity is an n-type impurity, and when the first conductivity type impurity is an n-type impurity, the second conductivity type impurity is is a p-type impurity.

2 to 11 are cross-sectional views for explaining a manufacturing process of an MCT device according to an embodiment of the present invention.

First, referring to FIG. 2 , a substrate 100 is prepared.

The substrate 100 includes a p-type emitter layer 101 (p emitter layer, lower emitter) doped with p-type impurities at a high concentration (p++), an n-type buffer layer 102 formed on the p-type emitter layer 101, n buffer layer) and an n-type base layer (103, n-base layer, lower base) formed on the n-type buffer layer 102. In this case, the n-type base layer 103 may be a layer doped with n-type impurities at a low concentration (n--).

The wafer on which the p-type emitter layer 101, the n-type buffer layer 102, and the n-type base layer 103 are sequentially grown is used as a substrate 100 for fabricating an MCT device.

As another example, an n-type buffer layer and a p-type emitter layer may be separately formed on the rear surface of a wafer doped with n-type impurities at a low concentration (n--) as a substrate.

The p-type impurity doped in the p-type emitter layer 101 may be, for example, a Group 3 element such as boron (B, Boron) or aluminum (Al), and the doping concentration of the p-type impurity (doping concentration) may be, for example, approximately 1×10 ¹⁸ cm ⁻³ or greater.

The n-type impurity doped into the n-type buffer layer 102 may be, for example, a group 5 element such as phosphorus (P) or arsenic (As), and the doping concentration of the n-type impurity is, for example, approximately 1×10 ¹⁶ to about 1×10 ¹⁸ cm ⁻³ . The thickness of the n-type buffer layer 102 may be, for example, about 1 μm to about 10 μm.

The doping concentration and thickness of the n-type impurity doped into the n-type base layer 103 may be determined according to the blocking voltage or breakdown voltage of a semiconductor device to be manufactured.

In the case of a silicon power semiconductor device, the n-type impurity doped into the n-type base layer 103 may be, for example, a group 5 element such as phosphorus (P) or arsenic (As), and the n-type impurity is doped. The concentration may be, for example, 1×10 ¹⁶ cm ⁻³ or less. The thickness of the n-type base layer 103 may be, for example, approximately ~10 μm or more.

When the substrate 100 is prepared, a process of forming (or growing) a first oxide film 204 on the surface of the substrate 100 (the surface of the n-type base layer 103) is performed.

The first oxide layer 204 may be formed by, for example, an oxidation process. Here, the first oxide layer 204 may also be referred to as a 'sacrificial oxide layer'. The thickness of the first oxide film 204 may be, for example, about 0.5 μm or more.

Subsequently, in order to expose a portion of the surface of the substrate 100 upward, a first oxide film 204 formed on the n-type base layer 103 using a photolithography process and an etching process. ) A process of removing a part of is performed.

A p-type base region (p-base, upper base) to be formed in the n-type base layer 103 is defined, and this p-type base region 104 is shown in FIG. 3 .

Subsequently, a process of forming (or growing) a second oxide film 205 on the surface of the n-type base layer 103 exposed upward by the removal of the first oxide film 204 may be performed.

The second oxide film 205 is formed on the surface of the substrate 100 (or the surface of the n-type base layer 103) from an ion implantation process or a vacuum plasma doping process performed in a subsequent process. serves to protect The thickness of the second oxide layer 205 may be, for example, approximately 10 to 100 nm.

Then, by using the ion implantation process (or vacuum plasma doping process), the p-type base region (FIG. 3 A process of implanting the p-type impurity 206 to form 104 of ) is performed.

The p-type impurity implanted into the n-type base layer 103 may be, for example, a group 3 element such as boron (B, Boron) or aluminum (Al), and the ion implantation amount of the p-type impurity ( ion dose) may be, for example, approximately 1×10 ¹³ to 1×10 ¹⁴ cm ^-2 .

Next, referring to FIG. 3 , a diffusion process of diffusing the p-type impurity ion-implanted into the n-type base layer 103 into the n-type base layer 103 (diffusion process) process) is going on.

The diffusion process may be, for example, a high temperature annealing process. A doping depth or junction depth of the p-type impurity may be, for example, about 5 to 10 μm.

Next, to form an n-type emitter region 105 (n-emitter, upper emitter) of FIG. 4 to be described later, n-type impurities 208 (eg, P, As) are formed under the surface of the p-type base region 104. etc.), an ion implantation process is performed. At this time, the first oxide film 204 serves as an ion implantation mask in the ion implantation process of the n-type impurity to form the n-type emitter region 105 .

The n-type impurity 208 for forming the n-type emitter region ( 105 in FIG. 4 ) may be, for example, P (phosphorus) or As, and the ion implantation amount of the n-type impurity 208 ( ion dose) may be, for example, 1×10 ¹³ to 1×10 ¹⁴ cm ^-2 .

Subsequently, referring to FIG. 4 , a diffusion process of diffusing the ion-implanted n-type impurity 208 under the surface of the p-type base region 104 into the inside of the p-type base region 104 is performed. It goes on. An n-type emitter region 105 (n-emitter) is formed in the p-type base region 104 by this diffusion process.

The diffusion process may be, for example, a high-temperature heat treatment process. A doping depth or junction depth of the n-type impurity 208 diffused into the p-type base region 104 by this diffusion process may be, for example, 1 to 5 μm.

In the diffusion process of the p-type impurity (206 in FIG. 2) for forming the p-type base region 104, the p-type impurity (206 in FIG. 2) is diffused deeply in the lateral direction to form the p-type base region 104 ) and the n-type base layer 103 expands deeply in the lateral direction.

In contrast, in the diffusion process of the n-type impurity (208 in FIG. 3) for forming the n-type emitter region 105 in FIG. 4, the n-type emitter region is formed due to the p-type impurity (206 in FIG. 2) The junction surface of (105, n-emitter) and the p-type base region 104 does not extend deeply in the lateral direction.

Of course, if the ion implantation amount of the n-type impurity ( 208 in FIG. 3 ) is increased, the junction surface of the n-type emitter region 105 may deeply expand in the lateral direction. However, in this case, since the surface density of the n-type emitter region 105 forming the channel of the off-FET increases, the threshold voltage of the off-FET has a very large negative value, which is It degrades the current drive capability of the FET.

Meanwhile, a channel region 112 of an on-FET is formed in a region below the surface of the p-type base region 104 . Here, the channel region 112 of the on-FET is a junction between the n-type base region 103 and the p-type base region 104 in the region below the surface of the p-type base region 104 and the p-type base region 104. and the junction surface of the n-type emitter region 105.

Meanwhile, although not shown in the figure, the n-type emitter region 105 is formed by forming the first oxide film 204 and the second oxide film 205 after the diffusion process of the p-type base region 104 described in FIG. After removing all of them, growing a separate oxide film, patterning the n-type emitter region 105, and performing the above-described ion implantation and diffusion process of the n-type impurity (208 in FIG. 3) to form. there is.

Subsequently, referring to FIG. 5 , in order to secure the channel region 110 of the off-FET having a short and uniform length to be described in FIG. 6, a deposition process and an etch-back process are performed to form a first oxide film. The process of forming the spacer 211 on the side of the is in progress.

In the deposition process, a spacer material layer is deposited on the entire surface of the first oxide layer 204 . In the etch-back process, spacers 211 are formed along side surfaces of the first oxide layer 204 by etching the spacer material layer. Here, the etch-back process may be, for example, a plasma etching process.

Subsequently, a third oxide film 212 may be additionally grown to protect the surface of the substrate from an ion implantation process to be performed in a subsequent process. The thickness of the third oxide layer 212 may be, for example, approximately 10 to 100 nm.

The spacer 211 may be, for example, an oxide film or a nitride film. The spacer 211 may have a thickness of about 200 nm or more, for example.

As described above, in the case of the MCT device, since the turn-off performance determines the current driving capability of the device, the channel length of the channel region 110 of the off-FET is formed short in order to improve the current driving capability of the off-FET. and all MCT devices integrated on one wafer must have a uniform channel length.

Next, referring to FIG. 6 , in order to form a p-type drain region 106 (p+) for serving as a drain of an off-FET, an n-type emitter region 105 is spaced apart from the spacer 211 at a predetermined interval. ) A photolithography process of forming a photoresist pattern 214 on the top may be performed.

Thereafter, p-type impurities (B, Al, etc.) are ion-implanted into the n-type emitter region 105 using the spacer 211 and the photoresist pattern 214 as an ion implantation mask. A process of forming the p-type drain region 106 of the off-FET is performed. The ion dose of the p-type impurity may be, for example, approximately 1×10 ¹⁵ cm ⁻² or greater.

Through the above process, between the end (junction surface) of the n-type emitter region 105 and the end (junction surface) of the p-type drain region 106 of the off-FET or under the spacer 211 The off-FET channel region 110 is formed in the lateral direction.

As such, the off-FET channel region 110 having a short channel length and a uniform length may be formed through the self-align process using spacer formation and the p+ ion implantation process.

Subsequently, referring to FIG. 7 , after forming the p-type drain region 106 of the off-FET, a process of removing the photoresist pattern 214 used as a mask for ion implantation is performed.

Subsequently, an etching process of removing a portion of the spacer 211 and the first oxide layer 204 is performed so that the off-FET channel region 110 or a portion of the off-FET channel region 110 is exposed upward. Here, the etching process of removing a part of the first oxide layer 204 and the spacer 211 may be, for example, an isotropic etching process.

The isotropic etching process may be, for example, wet etching. In this case, when the spacer 211 is an oxide, it may be etched at a faster rate than the first oxide layer 204 in the wet etching process.

When the spacer 211 is an oxide, the spacer 211 is, for example, an oxide film grown by chemical vapor deposition (CVD), and the first oxide film 204 is formed by a thermal oxidation process. It may be a grown oxide film.

Subsequently, referring to FIG. 8 , an ion implantation process for implanting p-type impurities (B and Al) into the channel region 110 of the off-FET is performed. At this time, the ion implantation dose (dose) of the ion-implanted p-type impurities into the off-FET channel region 110 is, for example, 1×10 ¹¹ to 1×10 ¹³ cm ^- can be ²

The ion implantation of the off-FET channel region 110 may improve off-FET characteristics by adjusting the turn-on voltage of the off-FET. In addition, the channel region 110 of the off-FET forms a pMOS channel in a depletion mode so that the off-FET is turned on at a gate voltage of 0V, thereby turning off the MCT device.

Subsequently, referring to FIG. 9 , after removing the first oxide film 204 and the oxide films formed to protect the surface of the substrate 100 in the ion implantation process using an etching process, a gate insulating film 108 is formed on the entire surface of the substrate 100. A process of sequentially growing the gate electrode layer 109 and the gate electrode layer 109 is performed.

Subsequently, an n-type (n+) doped region 107 (n+), which will be described below, and a gate insulating film 108 on a portion of the p-type drain region 106 of the off-FET surrounding the n-type doped region 107 are formed. A process of etching the gate electrode layer 109 is performed to have the opening OP exposed upward. To form the opening OP, a photolithography process may be further used.

Then, in order to improve the ohmic contact characteristics and electron injection characteristics of the n-type emitter region 105, an n-type doped region surrounded by the p-type drain region 106 of the off-FET ( 107) is performed.

The n-type doped region 107 is formed between the p-type drain region 106 of the off-FET by using, for example, a photoresist pattern (not shown) as a mask for ion implantation, and n-type impurities (P, As) ) by implanting ions of Here, the ion implantation amount of the n-type impurity may be approximately 1×10 ¹⁵ cm ⁻² or greater.

Subsequently, referring to FIG. 10 , a process of depositing an interlayer insulating film 113 on the gate electrode layer 109 and the gate insulating film 108 exposed upward through the opening OP is performed.

Thereafter, by using a photolithography process and an etching process, the gate insulating film ( 108) and the interlayer insulating film 113 are removed.

Next, referring to FIG. 11 , an upper portion to be used as a cathode electrode on the interlayer insulating film 113 and a portion of the p-type drain region 106 of the off-FET exposed to the upper portion and the n+ doped region 107 A process of forming (or depositing and etching) the metal layer 114 is performed.

Then, a process of forming (depositing) a lower metal layer 115 to be used as an anode electrode on the lower surface of the p-type emitter layer 101 is performed.

By forming the upper and lower metal layers 114 and 115, manufacturing of the MCT device is completed.

The MCT fabrication process described above improves the current driving capability of the off-FET and the uniformity of device operation by forming a uniform and short-length off-FET channel using the self-alignment process of the spacer formation and recession method. uniformity) can be improved.

In addition, channel ion implantation can be selectively performed on the off-FET channel region, thereby improving the turn-off performance of the MCT by turning on the off-FET at a low gate voltage. The voltage can turn off the MCT element.

Example 2 of a method for manufacturing an MCT device

Meanwhile, in the manufacturing process of the MCT device of FIGS. 2 to 11 , the ion implantation process of the off-FET channel region 110 may be performed in the following process instead of the method described in FIGS. 7 and 8 .

12 and 13 are cross-sectional views for explaining another embodiment of a process for ion-implanting p-type impurities into the off-FET channel region of FIGS. 7 and 8 .

Referring first to FIG. 12 , after forming the p-type drain region 106 according to the process of FIG. 6, the photoresist pattern 214, the spacer 211, the first oxide film 204 and A process of removing the third oxide layer ( 212 in FIG. 6 ) may proceed.

Subsequently, an oxidation process in which a fifth oxide film 237 is grown on the upper surface of the substrate 100 exposed by removing the first oxide film 204 and the third oxide film (212 in FIG. 6) is performed. can At this time, the thickness of the fifth oxide film 237 may be, for example, approximately 10 to 100 nm.

Next, referring to FIG. 13 , a photolithography process of forming a photoresist pattern 238 on the fifth oxide film 237 is performed. A photoresist pattern 238 may be formed between the p-type base region 104 and another p-type base region 104' adjacent to the p-type base region 104.

The photoresist pattern 238 is used as a mask for ion implantation, and the channel region 110 of the off-FET and the channel region 112 of the on-FET adjacent to the channel region 110 of the off-FET are formed. An ion implantation process of implanting p-type impurities (B, Al) into a partial region (or the entire region) is performed.

According to this ion implantation process, a threshold voltage adjustment layer (239) is formed.

On the other hand, although not shown in the drawings, the threshold voltage adjusting layer 239 may be formed on the entire surface of the substrate 100 without forming the photoresist pattern 238 .

An ion implantation dose of the threshold voltage control layer 239 may be, for example, 1Х10 ¹¹ to 1Х10 ¹³ cm ^-2 . The threshold voltage adjusting layer 239 may be formed by an ion implantation process simultaneously performed in the off-FET channel region 110 and the on-FET channel region 112 .

By implanting ions into the off-FET channel region 110, the turn-on voltage of the off-FET is adjusted to improve the electrical characteristics of the off-FET, and at the same time, by implanting ions into the on-FET channel region 112, the on-FET The threshold voltage can be increased to a stable value.

In addition, the off-FET channel 110 may turn off the MCT device by forming a pMOS channel in a depletion mode so that the off-FET is turned on at a gate voltage of 0V.

Subsequently, after removing the photoresist pattern 238 and the fifth oxide film 237, manufacturing of the MCT device may be completed through the processes of FIGS. 9 to 11.

The formation of the threshold voltage adjusting layer 239 described in FIGS. 7 and 8 and FIGS. 12 and 13 may be applied to all of the first to fourth embodiments to be described below.

Hereinafter, structural characteristics according to the gate electrode layer 109 in the n-type n-MCT device manufactured according to the manufacturing process of FIGS. 2 to 13 will be described.

First embodiment

14 is a top plan view of the MCT device manufactured according to the first embodiment of the present invention, viewed from above in a state in which the gate insulating film, the interlayer insulating film, and the upper metal layer are removed, and FIG. 15 is a cut line D-D' shown in FIG. It is a three-dimensional cross-sectional view of the MCT device cut along.

Referring to FIGS. 14 and 15 , an n-type buffer layer 102 may be disposed on the high-concentration p-type emitter layer 101 . An n-type base layer 103 serving as a lower base of the PNPN thyristor is disposed on the n-type buffer layer 102.

An upper base diffused into the n-type base layer 103 according to an ion implantation process of p-type impurities, that is, a p-type base region 104 is disposed on the n-type base layer 103 .

An n-type emitter region 105 formed by diffusion into the p-type base region 104 by ion implantation of n-type impurities is disposed inside the p-type base region 104 . At this time, below the upper surface of the p-type base region 104 becomes an on-FET channel region 112 serving as an on-FET channel.

An n-type doped region 107 and a p-type drain region 106 are disposed inside the n-emitter region 105 . At this time, the p-type drain region 106 serves as a drain of the off-FET.

The n-type doped region 107 is in contact with the n-type emitter region 105 to improve ohmic contact characteristics of the n-type emitter region 105 and to improve emitter injection efficiency of the upper NPN BJT. improve

A region immediately below the upper surface of the n-type emitter region 105 becomes a channel region 110 of the off-FET. At the same time, the channel region 110 of the off-FET serves as a passage through which the source current of the on-FET flows.

The ion implantation of the channel region 110 of the off-FET can improve off-FET characteristics by adjusting the turn-on voltage of the off-FET. In addition, the channel region 110 of the off-FET forms a pMOS channel in a depletion mode so that the off-FET is turned on at a gate voltage of 0V, thereby turning off the MCT device.

The gate insulating film 108, the gate electrode layer 109, the interlayer insulating film 113, the upper metal layer 114, and the lower metal layer 115 formed thereafter are formed according to the manufacturing process described with reference to FIGS. 9 to 11.

As shown in FIG. 14, the gate electrode layer 109 is formed of the n-type doped region 107 included in one MCT device and the p-type drain region 106 surrounding the n-type doped region 107. It has a plurality of openings OP exposing some of them upward. In this case, the gate electrode layer 109 may be arranged in a line shape. Each of the openings OP may also be arranged in a line shape.

One MCT element is arranged in a line shape on one wafer, and the MCT elements arranged on the wafer have the same structure.

Meanwhile, as shown in FIGS. 14 and 15, the n-type doped region 107 exposed upward by the line-shaped opening OP formed in the gate electrode layer 109 and the n-type doped region 107 are surrounded by Like the line-shaped opening OP, the p-type drain region 106 may extend in a line shape when viewed from above.

In addition, the n-type emitter region 105 also extends in the shape of a line when viewed from above.

Therefore, the off-FET channel region 110 formed between the contact surface of the n-type emitter region 105 and the p-type base region 104 and the p-type drain region 106, the on-FET source The passage through which the current flows) also has a line shape when viewed from above.

In addition, the surface of the n-type base layer 103 serving as the lower base may also be seen in a line shape when viewed from above.

The line-shaped off-FET channel region 110 and the on-FET channel region 112 are formed at all locations of the MCT device according to an ion implantation process using the spacer 211 shown in FIGS. 5 and 6 as an ion implantation mask. has the same width at , whereby it is possible to form off-FETs and on-FETs with uniform characteristics.

As described above, in the MCT device having the gate electrode layer 109 arranged in a line shape, the off-FET channel region 110 and the on-FET channel region 112 are the gate electrode layer 109 of the MCT device unit cell. All are located at the ends, and the turn-on and turn-off characteristics of the MCT element can be maintained uniformly in all cells.

In addition, channel ion implantation may be selectively performed on the channel region 110 of the off-FET, so that the off-FET is turned on at a low gate voltage, thereby improving the turn-off performance of the MCT.

In addition, since the off-FET channel region 110 is formed through ion implantation of p-type impurities to operate in a depletion mode, the MCT device can be turned off at a gate voltage of 0V.

Second embodiment

16 is a plan view of a gate electrode layer according to a second embodiment of the present invention viewed from above, and FIG. 17 is a gate insulating film disposed below the gate electrode layer shown in FIG. 16, an interlayer insulating film disposed above the gate electrode layer, and an upper portion thereof. 18 is a plan view of the MCT element as viewed from above with the metal layer removed, and FIG. 18 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line AA′ shown in FIG. 17 with the gate electrode layer shown in FIG. 16 removed. However, in FIG. 17, the gate electrode layer 109 is omitted.

Referring to FIGS. 16 to 18 , an n-type buffer layer 102 is disposed on the p-type emitter layer 101 . An n-type base layer 103 serving as a lower base of the PNPN thyristor is disposed on the n-type buffer layer 102.

A p-type base region 104 is disposed inside the n-type base layer 103, and an n-type emitter region 105 is disposed inside the p-type base region 104. At this time, an on-FET channel region 112 serving as an on-FET channel is disposed below the upper surface of the p-type base region 104 .

An n+ doped region 107 and a p-type drain region 106 are disposed inside the n-type emitter region 105 . At this time, the p-type drain region 106 serves as a drain of the off-FET.

The n-type doped region 107 contacts the n-type emitter region 105 to improve ohmic contact characteristics of the n-type emitter region 105 and improve emitter injection efficiency of the upper NPN BJT.

An area immediately below the upper surface of the n-type emitter region 105 becomes an off-FET channel region 110, and the channel region 110 of the off-FET serves as a passage through which the source current of the on-FET flows. do.

The ion implantation of the off-FET channel region 110 may improve off-FET characteristics by adjusting the turn-on voltage of the off-FET, and the off-FET channel region 110 is in a depletion mode. The MCT device can be turned off by forming a pMOS channel so that the off-FET is turned on at a gate voltage of 0V.

Thereafter, the gate insulating film 108, the gate electrode material 109, the interlayer insulating film 113, the upper metal layer 114, and the lower metal layer 115 are formed according to the manufacturing process of FIGS. 9 to 11 described above.

As shown in FIG. 16, the gate electrode layer 109 according to the second embodiment of the present invention surrounds the n-type doped region 107 included in the MCT element and the n-type doped region 107, and is a p-type. It has a plurality of openings OP (OP1, OP2, OP3, and OP4) exposing a portion of the drain region 106 upward.

The gate electrode layer 109 according to the second embodiment of the present invention is arranged in a grid or matrix form. Each opening OP may have, for example, a circular shape.

As shown in FIG. 16, a unit cell region representing one MCT element on the gate electrode layer 109 is a rectangular region R1 including one opening OP1 or four adjacent openings ( It may be defined as a rectangular region R2 including some regions of OP1 , OP2 , OP3 , and OP3 .

Each of the partial areas included in the quadrangular area R2 may be one of the four areas when the circular opening is divided into four areas.

One MCT element constituting a unit cell is arranged in a grid or matrix form on one wafer, and the MCT elements arranged on the wafer have the same structure.

Meanwhile, as shown in FIGS. 17 and 18 , the n+ doped region 107 exposed upward by the circular opening OP1 formed in the gate electrode layer 109 and the p+ region surrounding the n+ doped region 107 ( 106) may be formed in a circular shape when viewed from above.

In addition, the n-type emitter region 105 may also be formed in a circular shape when viewed from above.

Therefore, the off-FET channel region 110 formed between the junction of the n-emitter region 105 and the p-type base region 104 and the p-type drain region 106 is a passage through which the source current of the on-FET flows. ) also has a circular band shape when viewed from above.

In addition, the n-type base layer 103 serving as a lower base may have a quadrangular shape with concave sides when viewed from above.

The n-type base layer 103 and the off-FET channel region 110 are spaced apart by the upper surface 112 (on-FET channel region) where the p-type base region 104 is exposed to the surface, and the on-FET channel region ( 112) has a circular band shape with a uniform width.

The off-FET channel region 110 having a circular band shape is formed at all positions of the MCT device according to the manufacturing process (process of forming the channel region by using the spacer 211 as an ion implantation mask) according to the present invention. has the same width at , and because of this, it is possible to form an off-FET with uniform characteristics.

As described above, in the MCT device having the gate electrode layer 109 having circular openings arranged in a grid form, the circular band-shaped on-FET channel region 112, and the off-FET channel region 110, The off-FET channel region 110 and the on-FET channel region 112 are located at both ends of the gate electrode material 109 of the MCT device unit cell, and the turn-on and turn-off characteristics of the MCT device are uniform in all cells. can have

In addition, since channel ion implantation can be selectively performed in the off-FET channel region, the turn-off performance of the MCT can be improved by turning on the off-FET at a low gate voltage, as well as improving the turn-off performance of the MCT in a depletion mode. The MCT device can be turned off at a gate voltage of 0V by forming the off-FET channel region 110 through ion implantation of p-type impurities to operate.

The MCT device having a gate structure formed to have a circular opening and a circular on-FET and off-FET shape has a larger PNPN thyristor area per unit cell and an on-FET compared to an MCT device having a line-shaped gate structure And by having an off-FET region, it is possible to improve the characteristics of the MCT device.

Third embodiment

19 is a top plan view of a gate electrode layer according to a third embodiment of the present invention, as viewed from above, and FIG. 20 is a gate insulating film disposed under the gate electrode layer shown in FIG. 19, an interlayer insulating film disposed thereon, and an upper portion used as a cathode. A plan view of the MCT element viewed from above in a state in which the metal layer is removed, and FIG. 21 is a three-dimensional cross-sectional view of the MCT element cut along the cutting line BB′ shown in FIG. 20 . However, in FIG. 21, the gate electrode layer is omitted.

Referring to FIG. 19 , the gate electrode layer 109 according to the third embodiment has octagonal openings OP5 , OP6 , OP7 , and OP8 arranged in a grid or matrix form. Each of the octagonal openings OP5 , OP6 , OP7 , and OP8 may have four concave sides and four straight sides.

The MCT element constituting the unit cell has a square region R3 including one opening OP5 or a square region including parts of the four openings OP5, OP6, OP7, and OP8 on the gate electrode layer 109 ( R4) can be defined.

20 and 21, the n-type base layer seen on the surface of the substrate 100 in a state in which the gate insulating film 108, the gate electrode layer 109, the interlayer insulating film 113, and the upper metal layer 114 are removed. (103) may be circular.

Also, with the gate insulating film 108, the gate electrode layer 109, the interlayer insulating film 113, and the upper metal layer 114 removed, the p-type base region 104 seen on the surface of the substrate 100 has a circular n It may be the remaining part surrounding the mold base layer 103.

As shown in FIGS. 20 and 21 , the channel region 112 of the on-FET is exposed in a circular band shape on the surface of the substrate 100 and is p-type in contact with the circular n-type base layer 103. It is disposed on top of the base region 104 .

Although the n-type emitter region 105 is not shown in FIG. 20, the n-type base layer 103 that looks circular on the surface of the substrate 100 and the on-type base layer 103 that looks like a circular band on the surface of the substrate 100 -It is formed in the remaining regions except for the channel region 112 of the FET.

The circular band-shaped channel region 112 of the on-FET and the p-type drain region 106 are spaced apart from each other with the circular band-shaped off-FET channel region 110 interposed therebetween when viewed from above. .

On the top of the n-type emitter region 105, the off-FET channel region 110, which is seen as a circular band on the surface of the substrate, is exposed in an octagonal band shape by the octagonal opening OP of the gate electrode layer 109. A p-type drain region 106 and an n-type doped region 107 surrounded by the octagonal band-shaped p-type drain region 106 are disposed.

The octagonal opening OP of the gate electrode layer 109 may include four concave sides and four straight sides, and thus, the p-type drain region 106 exposed upward through the opening OP. It may also consist of an inner edge and an outer edge composed of four concave sides and four straight edges.

As such, in the MCT device having the gate electrode layer having the octagonal opening OP formed of concave sides and straight sides, the off-FET channel region 110 having a circular band shape is formed, and the off-FET channel region ( 110) simultaneously serves as a passage through which the source current of the on-FET flows.

In the MCT device according to the third embodiment, the channel region 110 of the off-FET and the channel region 112 of the on-FET have a circular band shape and are formed to have the same structure at all locations, so that they have uniform characteristics. of off-FET and on-FET can be implemented.

In addition, since channel ion implantation can be selectively performed in the off-FET channel region, the off-FET is turned on at a low gate voltage, thereby improving the turn-off performance of the MCT. In addition, the MCT device can be turned off at a gate voltage of 0V by forming the p-channel 110 operating in a depletion mode.

The MCT device having the gate structure having the octagonal opening and the off-FET and on-FET channel regions 110 and 112 having a circular band shape is wider than the MCT device having the line-shaped gate structure. PNPN thyristor wider per unit cell The characteristics of the MCT device can be improved by having an area and an on-FET and an off-FET region.

Fourth embodiment

22 is a top plan view of a gate electrode layer according to a fourth embodiment of the present invention viewed from above, and FIG. 23 is a gate insulating film disposed below the gate electrode layer shown in FIG. 22, an interlayer insulating film disposed above, and an upper metal used as a cathode. It is a plan view of the MCT element viewed from above in a state where the layer is removed, and FIG. 24 is a three-dimensional cross-sectional view of the MCT element taken along the cutting line C-C' shown in FIG. 23 . However, in FIG. 24, the gate electrode layer 109 is omitted.

22 to 24, the gate electrode layer 109 according to the fourth embodiment is arranged in a grid or matrix form as shown in FIG. 22, and has octagonal openings OP9, OP10, OP11, and OP12. ) has The octagonal openings OP5 , OP6 , OP7 , and OP8 may have four concave sides and four straight sides.

The MCT element constituting the unit cell has a square region R5 including one opening OP9 or a square region including parts of four openings OP: OP9, OP10, OP11, and OP12 on the gate electrode layer 109. It may be defined as region R6.

In the n-type emitter region 105, an n-type doped region 107, a p-type drain region 106 surrounding the n-type doped region 107, and an off-FET channel region 110 are disposed.

The octagonal opening OP of the gate electrode layer 109 according to the fourth embodiment covers the n-type doped region 107 and a portion of the p-type drain region 106 surrounding the n-type doped region 107. exposed at the top.

The n-type doped region 107 exposed upward through the octagonal-shaped opening OP of the gate electrode layer 109 has an octagonal shape having four concave sides and four straight sides when viewed from above. can have

The p-type drain region 106, a portion of which is exposed by the octagonal-shaped opening OP of the gate electrode layer 109, surrounds the octagonal-shaped n-type doped region 107 when viewed from above. It may have a band shape.

Accordingly, the p-type drain region 106 having the octagonal band shape has eight inner edges and eight outer edges when viewed from above. The eight inner sides are composed of four concave sides and four straight sides, and the eight outer sides may also be composed of four concave sides and four straight sides.

The off-FET channel region 110 surrounding the p-type drain region 106 having the octagonal band shape also has the octagonal band shape having a constant width when viewed from above.

Accordingly, the off-FET channel region 110 also has 8 inner edges and 8 outer edges. The eight inner sides are composed of four concave sides and four straight sides, and the eight outer sides may also be composed of four concave sides and four straight sides.

The n-type base layer 103 shown on the surface of the substrate 100 in a state in which the gate insulating film 108, the gate electrode layer 109, the interlayer insulating film 113, and the upper metal layer 114 are removed is shown in FIGS. 23 and 24 As shown in, it may have a circular shape.

As shown in FIG. 24, the circular n-type base layer 103 shown on the surface of the substrate 100 is p shown on the surface of the substrate 100 in a state in which 108, 109, 113, and 114 are removed. It is spaced apart from the channel region 110 of the octagonal strip-shaped off-FET at regular intervals with the base region 104 interposed therebetween.

In the MCT device having the gate electrode layer 109 having an octagonal opening, an octagonal band-shaped off-FET channel region 110 is formed, and the inner and outer sides of the octagonal band-shaped off-FET channel region 110 are formed. may have four concave sides and four straight sides, respectively.

According to the manufacturing process of the MCT device described above, since the channel region 110 of the off-FET is formed to have a short and uniform channel length, an off-FET with uniform characteristics can be implemented.

In addition, since channel ion implantation can be selectively performed in the off-FET channel region, turn-on performance of the MCT can be improved by turning on the off-FET at a low gate voltage.

In addition, the MCT device can be turned off at a gate voltage of 0V by forming the p-channel 110 operating in a depletion mode.

The MCT device having the gate electrode layer 109 having the octagonal opening OP and the off-FET channel region 110 having the octagonal band shape is compared to the MCT device having the gate electrode layer having the line shape, per unit cell. The characteristics of the MCT device can be improved by having a wider PNPN thyristor area and on-FET and off-FET areas.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made by those skilled in the art without departing from the essential characteristics of the present invention.

Therefore, the embodiments expressed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas that are equivalent or within the scope of equivalents should be construed as being included in the scope of the present invention.

Claims (16)

Forming a base region of a first conductivity type doped with impurities of a first conductivity type in a substrate and an emitter region of a second conductivity type doped with impurities of a second conductivity type in the base region of the first conductivity type ;
forming a spacer on a side surface of an oxide film formed on the substrate and exposing an upper portion of the emitter region of the second conductivity type;
Impurities of the first conductivity type are ion-implanted into all or part of the emitter region of the second conductivity type exposed upward by the spacer to form a drain region of the first conductivity type of an off-FET, forming a channel region of an off-FET defined between a junction surface of an emitter region of a second conductivity type and a junction surface of a drain region of the first conductivity type;
ion-implanting impurities of the first conductivity type into an upwardly exposed channel region of the off-FET according to the removal of the spacer;
after removing the oxide film, forming a gate electrode layer on the substrate, exposing the drain region of the first conductivity type and the emitter region of the second conductivity type upward;
forming a doped region of a second conductivity type by ion-implanting impurities of the second conductivity type into the emitter region of the second conductivity type upwardly exposed by the gate electrode layer; and
An upper metal layer used as a cathode electrode and a lower metal layer used as an anode electrode on the lower surface of the substrate are formed on the gate electrode layer, the drain region of the first conductivity type, and the doped region of the second conductivity type. step to do
Method for manufacturing an MCT device comprising a. In paragraph 1,
Forming the channel region of the off-FET,
The spacer and the photoresist pattern formed on the emitter region of the second conductivity type upwardly exposed by the spacer are used as an ion implantation mask, and the second upwardly exposed by the spacer and the photoresist pattern The method of manufacturing an MCT device is a step of performing an ion implantation process of implanting impurities of the first conductivity type into a conductivity type emitter region. In paragraph 1,
The channel region of the off-FET,
The method of manufacturing an MCT element formed below the spacer in a lateral direction between a bonding surface of the emitter region of the second conductivity type and a bonding surface of the drain region of the first conductivity type. In paragraph 1,
The step of ion-implanting impurities of the first conductivity type into the channel region of the off-FET,
removing the spacer using an isotropic etching process; and
Adjusting the turn-on voltage of the off-FET by ion-implanting impurities of the first conductivity type into the channel region of the off-FET exposed through the isotropic etching process.
Method for manufacturing an MCT device comprising a. In paragraph 4,
The impurity of the first conductivity type ion-implanted into the channel region of the off-FET is an impurity of the first conductivity type;
The ion implantation amount of the impurity of the first conductivity type is 1 × 10 ¹¹ to 1 × 10 ¹³ cm ^-2 Method of manufacturing an MCT device. In paragraph 1,
The step of ion-implanting impurities of the first conductivity type into the channel region of the off-FET,
further removing the spacer and the oxide layer using an etching process;
forming another oxide layer on an upper surface of the substrate exposed by removing the spacer and the oxide layer;
Forming another photoresist pattern formed on the different oxide film between a base region of the first conductivity type and a base region of another first conductivity type adjacent to the base region of the first conductivity type. ;
Ion-implanting impurities of the first conductivity type into the off-FET channel region and the on-FET channel region adjacent to the off-FET channel region using the other photoresist pattern as an ion implantation mask. Steps to proceed with the injection process
Method for manufacturing an MCT device comprising a. In paragraph 6,
The method of manufacturing an MCT device in which the channel region of the on-FET is an area under the surface of the base region of the first conductivity type. In paragraph 1,
The step of ion-implanting impurities of the first conductivity type into the channel region of the off-FET,
further removing the oxide film and the spacer using an etching process;
forming another oxide layer on the entire surface of the substrate exposed to the upper side according to the removal of the oxide layer and the spacer; and
Forming a threshold voltage control layer on the entire surface of the substrate by ion-implanting impurities of a first conductivity type into a channel region of the off-FET and a channel region of the on-FET adjacent to the channel region of the off-FET.
Method for manufacturing an MCT device comprising a. a substrate including an emitter layer of a first conductivity type doped with impurities of a first conductivity type and a base layer of a second conductivity type doped with impurities of a second conductivity type disposed on the emitter layer of the first conductivity type;
a base region of a first conductivity type disposed in the second conductivity type base layer;
an emitter region of a second conductivity type disposed in the base region of the first conductivity type;
a doped region of the second conductivity type disposed in the emitter region of the second conductivity type and a drain region of the first conductivity type of an off-FET surrounding the doped region of the second conductivity type;
disposed between the junction surface of the drain region of the first conductivity type and the junction surface of the emitter region of the second conductivity type in the emitter region of the second conductivity type, and doped with impurities of the first conductivity type. the channel region of an off-FET;
an on-disposed between the junction surface of the emitter region of the second conductivity type and the junction surface of the base region of the first conductivity type so as to be adjacent to the channel region of the off-FET in the base region of the first conductivity type; the channel region of the FET;
a gate electrode layer disposed on the entire surface of the substrate and having an opening exposing the doped region of the second conductivity type and the drain region of the first conductivity type upward;
a cathode electrode layer disposed on the doped region of the second conductivity type and the drain region of the first conductivity type, which are exposed upward through the gate electrode layer and the opening, with an interlayer insulating film interposed therebetween; and
An anode electrode layer disposed on the lower surface of the substrate,
In order to improve electrical characteristics of the off-FET and the on-FET, all or part of the channel region of the off-FET and the channel region of the on-FET are doped with impurities of the first conductivity type. delete In paragraph 9,
The channel region of the off-FET,
An oxide film formed on the base layer of the second conductivity type, the MCT element formed by a self-alignment process using a spacer formed on a side surface of the oxide film. In paragraph 9,
The doped region of the second conductivity type, the drain region of the first conductivity type, the off-FET channel region, and the on-FET channel region extend in a line shape when viewing the substrate from above,
The opening of the gate electrode layer,
When viewing the substrate from above, the MCT device having a line shape to expose a portion of the doped region of the second conductivity type and the drain region of the first conductivity type extending in the line shape upward. In paragraph 9,
When the substrate is viewed from above, the second conductivity type emitter region is circular, and the channel region of the first conductivity type off-FET has a circular shape at an end of the second conductivity type emitter region, The doped region of the second conductivity type is spaced apart from the channel region of the on-FET with the channel region of the off-FET interposed therebetween, and the base region of the second conductivity type exposed to the surface of the substrate is the on-FET. spaced apart from the channel region of the off-FET by a predetermined distance with the channel region of
The opening of the gate electrode layer,
When the substrate is viewed from above, the MCT device has a circular shape exposing a portion of the doped region of the second conductivity type and the drain region of the first conductivity type upward. In paragraph 9,
When viewing the substrate from above, the second conductive type base layer exposed to the surface of the substrate has a circular shape, and the channel region of the on-FET exposed to the surface of the substrate has a circular shape. The channel region of the off-FET has a circular shape surrounding the base layer of the second conductivity type, the channel region of the off-FET has a circular shape surrounding the channel region of the on-FET, and the drain region of the first conductivity type is the channel region of the off-FET. enclose the area,
The opening of the gate electrode layer,
When viewed from above the substrate, the MCT device to expose a portion of the doped region of the second conductivity type and the drain region of the first conductivity type upward. In paragraph 9,
When the substrate is viewed from above, the emitter region of the second conductivity type has an octagonal shape, and the channel region of the off-FET of the first conductivity type has an octagonal band at the end of the emitter region of the second conductivity type. The doped region of the second conductivity type is spaced apart from the channel region of the on-FET with the channel region of the off-FET interposed therebetween, and the base region of the second conductivity type exposed to the surface of the substrate is Spaced apart from the channel region of the off-FET by a predetermined distance with the channel region of the on-FET interposed therebetween;
The opening of the gate electrode layer,
When viewed from above the substrate, the MCT element exposing a portion of the doped region of the second conductivity type and the drain region of the first conductivity type upward. In paragraph 15,
The base region of the second conductivity type exposed to the surface of the substrate has a circular shape, and the octagonal shape of the emitter region of the second conductivity type and the octagonal band shape of the channel region of the off-FET have the second conductivity type. An MCT element having a concave side in a portion adjacent to the base region of the mold.

Images