JP3196575B2 - Composite semiconductor device and power conversion device using the same - Google Patents
Composite semiconductor device and power conversion device using the sameInfo
- Publication number
- JP3196575B2 JP3196575B2 JP13491095A JP13491095A JP3196575B2 JP 3196575 B2 JP3196575 B2 JP 3196575B2 JP 13491095 A JP13491095 A JP 13491095A JP 13491095 A JP13491095 A JP 13491095A JP 3196575 B2 JP3196575 B2 JP 3196575B2
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- JP
- Japan
- Prior art keywords
- semiconductor region
- main surface
- region
- semiconductor
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Thyristors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はＭＩＳゲートでオン、オ
フできるオン時の抵抗損失が小さく大電流化に適した複
合半導体装置において、特に低損失でかつ安全動作領域
の広い複合半導体装置及びそれを使った電力変換装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device which can be turned on and off by a MIS gate and has a small on-resistance loss and is suitable for a large current. The present invention relates to a power converter using the same.
【０００２】[0002]
【従来の技術】インバータ装置を始めとする電力変換器
の高性能化の要求から、高速，低損失，大容量の半導体
スイッチング素子の開発が望まれている。近年これに応
える半導体スイッチング素子として、ＭＩＳゲートでサ
イリスタを制御する素子(MIS制御サイリスタ）が注目さ
れている。ＭＩＳ制御サイリスタは、ＭＩＳゲートでバ
イポーラトランジスタを制御する素子であるＩＧＢＴ(I
nsulated Gate BipolarTransistor）に比べ低いオン電
圧が実現できるため、オン時の抵抗損失が小さく高耐圧
化に適している。サイリスタと直列にMISFETを接続し、
このMISFETのオン・オフによりサイリスタの電流経路を
導通・遮断してスイッチングするＭＩＳ制御サイリスタ
は、直列接続されたMISFETの限流作用により、素子を集
積化し並列動作させた場合にも、一つの素子への電流集
中が起こりにくく大電流化に適している。また特にオン
状態にサイリスタのｐベース層がフローティング電位と
なる構造の素子は、サイリスタがオンしやすくさらに抵
抗損失の低減が期待できる。このような素子は、例え
ば、特開平4−196359号公報において報告されている。
図２にその断面構造を示す。この半導体装置はｎ−基板
（ｎ−１層）１の裏面にｐ＋層２が形成されている。こ
のｐ＋層２に低抵抗で接触してコレクタ電極（Ｃ）３が
設けられている。ｎ−基板表面にはゲート電極５と絶縁
膜６からなる絶縁ゲートＧ１，ゲート電極７と絶縁膜８
からなる絶縁ゲートＧ２が形成されている。絶縁ゲート
Ｇ１下に達するようにｎ＋１層１１，ｎ＋２層１２が絶
縁ゲートＧ１をはさんで主表面から形成されている。ま
た絶縁ゲートＧ２をはさんでｎ＋２層１２と反対側にｎ
＋３層１３が、Ｇ２下に達するように主表面から形成さ
れている。ｎ＋１層１１，ｎ＋２層１２を取り囲むよう
にｐ１層１４が設けられている。ｎ＋３層１３を取り囲
むように、ｐ２層１５が設けられている。ｎ＋１層１１
に低抵抗で接触して電極４が設けられている。ｎ＋２層
２とｐ１層１４に低抵抗で接触してエミッタ電極（Ｅ）
９が形成されている。ｎ＋３層１３に低抵抗で接触して
電極１０が設けられている。絶縁ゲートＧ１とＧ２の電
極は低抵抗の配線電極により接続されている。また電極
４と電極１０も別の低抵抗の配線電極により接続されて
いる。2. Description of the Related Art Development of a high-speed, low-loss, large-capacity semiconductor switching device has been demanded in view of a demand for higher performance of a power converter such as an inverter device. In recent years, an element that controls a thyristor with a MIS gate (MIS control thyristor) has attracted attention as a semiconductor switching element responding to this. The MIS control thyristor is an element that controls a bipolar transistor with an MIS gate.
A low on-state voltage can be realized compared to an nsulated gate bipolar transistor), so the resistance loss at the time of on-state is small and suitable for high breakdown voltage. Connect MISFET in series with thyristor,
The MIS control thyristor, which switches by turning on and off the MISFET to conduct / cut off the current path of the thyristor, is a single element even when the elements are integrated and operated in parallel by the current limiting action of the MISFET connected in series. This is suitable for increasing the current with less current concentration on the surface. In particular, an element having a structure in which the p-base layer of the thyristor has a floating potential in the on state can easily turn on the thyristor and can be expected to reduce the resistance loss. Such an element has been reported, for example, in JP-A-4-196359.
FIG. 2 shows the cross-sectional structure. In this semiconductor device, ap + layer 2 is formed on the back surface of an n− substrate (n−1 layer) 1. A collector electrode (C) 3 is provided in contact with the p + layer 2 with low resistance. An insulating gate G1 comprising a gate electrode 5 and an insulating film 6, a gate electrode 7 and an insulating film 8
Is formed. The n + 1 layer 11 and the n + 2 layer 12 are formed from the main surface with the insulating gate G1 interposed therebetween so as to reach below the insulating gate G1. Further, n is located on the side opposite to the n + 2 layer 12 with the insulating gate G2 interposed therebetween.
The +3 layer 13 is formed from the main surface so as to reach below G2. A p1 layer 14 is provided so as to surround the n + 1 layer 11 and the n + 2 layer 12. A p2 layer 15 is provided so as to surround the n + 3 layer 13. n + 1 layer 11
The electrode 4 is provided in contact with the electrode 4 with low resistance. The emitter electrode (E) is brought into contact with the n + 2 layer 2 and the p1 layer 14 with low resistance.
9 are formed. The electrode 10 is provided in contact with the n + 3 layer 13 with low resistance. The electrodes of the insulated gates G1 and G2 are connected by a low-resistance wiring electrode. The electrode 4 and the electrode 10 are also connected by another low-resistance wiring electrode.
【０００３】図３に本複合半導体装置の等価回路を示
す。本装置は、ｐ＋層２，ｎ−１層１，ｐ２層１５から
成るｐｎｐトランジスタ（Ｑ１）とｎ−１層１，ｐ２層
１５，ｎ＋３層１３から成るｎｐｎトランジスタ（Ｑ
２）により構成されるサイリスタ（Ｔｈ１）を含んでい
る。このサイリスタＴｈ１は電極１０，配線電極，電極
４，絶縁ゲートＧ１とｎ＋１層１１とｐ１層１４とｎ＋
２層１２からなるｎチャネルMISFET（Ｍ２）を経由して
エミッタ電極（Ｅ）９に接続される。またｎ＋３層１
３，ｐ２層１５，ｎ−１層１から成るｎチャネルMISFET
（Ｍ１）のソース，ドレインがＱ２のエミッタ，コレク
タにそれぞれ接続される。さらにｐ１層１４，ｎ−１層
１，ｐ２層１５からなるｐチャネルMISFET(Ｍ３)が、ｐ
１層１４とｐ２層１５の間に設けられている。FIG. 3 shows an equivalent circuit of the present composite semiconductor device. This device comprises a pnp transistor (Q1) composed of p + layer 2, n-1 layer 1 and p2 layer 15, and an npn transistor (Q1) composed of n-1 layer 1, p2 layer 15 and n + 3 layer 13.
2) The thyristor (Th1) configured by (2) is included. The thyristor Th1 includes an electrode 10, a wiring electrode, an electrode 4, an insulated gate G1, an n + 1 layer 11, a p1 layer 14, and n +
It is connected to the emitter electrode (E) 9 via an n-channel MISFET (M2) composed of two layers 12. Also, n + 3 layer 1
N-channel MISFET composed of 3, p2 layer 15, and n-1 layer 1
The source and drain of (M1) are connected to the emitter and collector of Q2, respectively. Further, a p-channel MISFET (M3) composed of the p1 layer 14, the n-1 layer 1, and the p2 layer 15
It is provided between the first layer 14 and the p2 layer 15.
【０００４】以下図２，図３を用いて本装置の動作原理
を示す。まず本装置をターンオンするには、エミッタ電
極Ｅに対しコレクタ電極Ｃ及びゲート電極Ｇに正の電圧
を加える。これにより絶縁ゲートＧ１及びＧ２下のｐ１
層１４とｐ２層１５表面にそれぞれｎ反転層が形成され
る。（Ｍ１，Ｍ２オン）このＭ１，Ｍ２を介してエミッ
タ電極Ｅとｎ−１層１が接続され、電子がｎ−１層１に
注入される。この電子注入によりｎ−１層１のポテンシ
ャルが下がり、ｐ＋層２より正孔がｎ−１層１に注入さ
れる（Ｑ１オン）。注入された正孔はｎ−１層１を拡散
しＱ２のベース層であるｐ２層１５へ注入される。この
正孔注入によりｐ２層１５のポテンシャルが上がり、ｎ
＋３層１３よりｐ２層１５へ電子が注入される。（Ｑ２
オン）この結果サイリスタＴｈ１がオンし、半導体装置
がオン状態になる。また、Ｔｈ１に流れる電流は直列接
続されたＭ２の限流 作用を受ける。一方、ターンオフ
するには、ゲート電極Ｇを、エミッタ電極Ｅに対し同電
位または負の電位にバイアスする。これによりＭ１，Ｍ
２がオフし、ｎ−１層１への電子注入が遮断されるの
で、Ｑ１及びＱ２がオフし半導体装置はオフ状態にな
る。The operation principle of the present apparatus will be described below with reference to FIGS. First, to turn on the device, a positive voltage is applied to the collector electrode C and the gate electrode G with respect to the emitter electrode E. Thereby, p1 below the insulated gates G1 and G2
An n inversion layer is formed on each of the surfaces of the layer 14 and the p2 layer 15. (M1, M2 ON) The emitter electrode E and the n-1 layer 1 are connected via the M1 and M2, and electrons are injected into the n-1 layer 1. This electron injection lowers the potential of the n-1 layer 1, and holes are injected into the n-1 layer 1 from the p + layer 2 (Q1 ON). The injected holes diffuse into the n-1 layer 1 and are injected into the p2 layer 15, which is the base layer of Q2. By this hole injection, the potential of the p2 layer 15 increases, and n
Electrons are injected from the +3 layer 13 into the p2 layer 15. (Q2
On) As a result, the thyristor Th1 is turned on, and the semiconductor device is turned on. Further, the current flowing through Th1 is subjected to the current limiting action of M2 connected in series. On the other hand, to turn off, the gate electrode G is biased to the same potential or a negative potential with respect to the emitter electrode E. This allows M1, M
2 is turned off, and electron injection into the n-1 layer 1 is cut off, so that Q1 and Q2 are turned off and the semiconductor device is turned off.
【０００５】この半導体装置は、ｐ＋層２からの正孔の
注入に加えて、サイリスタ動作によりｎ＋３層１３から
ｎ−１層１へ電子が注入されるため、ＩＧＢＴに比べｎ
−１層の導電率変調が強く生じ、低オン電圧が実現でき
る。またＩＧＢＴと同様に絶縁ゲートへの電圧の印加・
除去によりオン・オフ可能なため、従来のＩＧＢＴと同
様にゲート回路が極めて簡略化される特徴を維持でき
る。In this semiconductor device, in addition to injection of holes from the p + layer 2, electrons are injected from the n + 3 layer 13 to the n-1 layer 1 by thyristor operation.
The conductivity modulation of the -1 layer is strongly generated, and a low on-state voltage can be realized. Also, as in the case of the IGBT, application of a voltage to the insulated gate
Since the gate circuit can be turned on / off by removal, the feature that the gate circuit is extremely simplified can be maintained similarly to the conventional IGBT.
【０００６】さらに本装置では、サイリスタのｐベース
層が直接電極に接しておらず、サイリスタのｐベース層
と電極の間に少なくとも１つのｎ型層を有する構成によ
り、サイリスタのｐベース層の電位は固定されずフロー
ティング電位となる。このとき、サイリスタのｐベース
層と電極間の抵抗が高いので、サイリスタのｐベース層
の電位が上昇しやすい。このため装置のオン時にサイリ
スタのｐベース層とｎエミッタの接合が順方向バイアス
されやすいので、サイリスタがターンオンしやすく低抵
抗損失であるという特徴を持つ。Further, in this device, the p-base layer of the thyristor is not in direct contact with the electrode, and at least one n-type layer is provided between the p-base layer of the thyristor and the electrode. Is not fixed and becomes a floating potential. At this time, since the resistance between the p-base layer of the thyristor and the electrode is high, the potential of the p-base layer of the thyristor tends to increase. Therefore, when the device is turned on, the junction between the p base layer and the n emitter of the thyristor is easily biased in the forward direction, so that the thyristor is easily turned on and has low resistance loss.
【０００７】[0007]
【発明が解決しようとする課題】上記従来型のサイリス
タのｐベース層がフローティング電位となるＭＩＳ制御
サイリスタを試作・評価した結果、この従来装置は安全
動作領域がＩＧＢＴに比べ極めて狭いことを本発明者等
は発見した。As a result of trial production and evaluation of a MIS control thyristor in which the p base layer of the above-mentioned conventional thyristor has a floating potential, it was found that the safe operation area of this conventional device was extremely narrower than that of an IGBT. Found them.
【０００８】本発明は、フローティング電位のｐベース
を持つサイリスタの特徴であるオンしやすいこと、低抵
抗損失であることを維持しながら、同時に広い安全動作
領域を持つＭＩＳ制御型サイリスタを提供することを目
的とする。An object of the present invention is to provide a MIS controlled thyristor having a wide safe operation area while maintaining the characteristics of a thyristor having a p-base of a floating potential, that it is easy to turn on and low resistance loss. With the goal.
【０００９】[0009]
【課題を解決するための手段】本発明者等は、上記従来
型のＭＩＳ制御サイリスタの解析を行い、安全動作領域
の狭い原因が、サイリスタと直接に接続されたMISFETに
過大な電圧が印加されるためであることを見いだした。
以下この現象を図３の等価回路を用いて説明する。The present inventors have analyzed the above-mentioned conventional MIS control thyristor, and found that an excessive voltage was applied to the MISFET directly connected to the thyristor because of the narrow safe operation area. I found it to be.
Hereinafter, this phenomenon will be described with reference to the equivalent circuit of FIG.
【００１０】サイリスタと直接に接続されたMISFET（Ｍ
２）に印加される電圧ＶＭ２は、コレクタ−エミッタ間
電圧ＶＣＥから、Ｔｈ１に印加される電圧ＶＴｈ１を除
いた電圧、ＶＭ２＝ＶＣＥ−ＶＴｈ１となる。オン状態
でＶＣＥを増やすとＭ２の限流作用によりコレクタ電流
ＩＣが飽和しほぼ一定の値となるので、ＶＴｈ１もほぼ
一定となる。このときＶＣＥを増やすとＶＭ２が増加す
る。さらにＶＣＥを増やすと、ＶＭ２がＭ２のソース−
ドレイン間耐圧ＶＢＭ２を越え、Ｍ２にアバランシェ電
流が流れ、ＩＣが増加する。このためＶＣＥの大きな領
域ではＭ２の限流作用がなくなり、半導体装置に過大な
電流が流れ、半導体装置が破壊してしまう。このため従
来装置では安全動作領域が狭くなる。以上の知見から、
上記の問題は以下の各手段によって解決できる。An MISFET (M) directly connected to a thyristor
The voltage VM2 applied to 2) is a voltage obtained by subtracting the voltage VTh1 applied to Th1 from the collector-emitter voltage VCE, that is, VM2 = VCE-VTh1. When VCE is increased in the ON state, the collector current IC is saturated by the current limiting action of M2 and becomes a substantially constant value, so that VTh1 also becomes substantially constant. At this time, if VCE is increased, VM2 is increased. If VCE is further increased, VM2 becomes the source of M2-
The avalanche current flows through M2 beyond the drain-to-drain breakdown voltage VBM2, and the IC increases. For this reason, in a region where VCE is large, the current limiting effect of M2 is lost, and an excessive current flows through the semiconductor device, thereby destroying the semiconductor device. For this reason, the safe operation area is reduced in the conventional device. From the above findings,
The above problem can be solved by the following means.
【００１１】まずＭ３のソース−ドレイン間耐圧ＶＢＭ
３をＶＢＭ２より低くすることにより解決できる。具体
的には、部分的にＶＢＭ３の低い領域を設ける。例えば
Ｍ３のチャネル長を少なくとも一部分小さくする。また
エミッタ電極と短絡されたｐ型層を設け、この層とサイ
リスタのｐベース層間の距離を、少なくとも一部分小さ
くしてもよい。また、これらの複合半導体装置を複数個
接続し、さらにVBM3の低い部分をＭ３のチャネル長方向
及びそれに垂直な方向で交互に設けてもよい。また、Ｍ
２のドレイン層とチャネル層の間に低キャリア濃度の領
域を設けてもよい。First, the source-drain breakdown voltage VBM of M3
3 can be set lower than VBM2. Specifically, a region having a low VBM3 is partially provided. For example, the channel length of M3 is reduced at least partially. Further, a p-type layer short-circuited with the emitter electrode may be provided, and the distance between this layer and the p-base layer of the thyristor may be reduced at least partially. Alternatively, a plurality of these composite semiconductor devices may be connected, and further, a low portion of VBM3 may be provided alternately in the channel length direction of M3 and in a direction perpendicular thereto. Also, M
A low carrier concentration region may be provided between the drain layer and the channel layer.
【００１２】上記問題を解決する別の手段としては、サ
イリスタのｐベース層とエミッタ電極間に、ＶＢＭ２よ
り低いツェナー電圧のツェナーダイオードをサイリスタ
のｐベース層にカソード電極を向けて設ける。As another means for solving the above problem, a Zener diode having a Zener voltage lower than VBM2 is provided between the p base layer of the thyristor and the emitter electrode with the cathode electrode facing the p base layer of the thyristor.
【００１３】さらに別の手段としては、サイリスタのｐ
ベース層とｐ１層１４の間の少なくとも一部に、サイリ
スタのｐベース層とｐ１層１４にそれぞれ接しかつ主表
面に露出するように、低キャリア濃度のｐ型層を設け
る。[0013] Still another means is that the thyristor p
At least a portion between the base layer and the p1 layer 14 is provided with a p-type layer having a low carrier concentration so as to be in contact with the p base layer and the p1 layer 14 of the thyristor and to be exposed on the main surface.
【００１４】[0014]
【作用】Ｍ３のソース−ドレイン間耐圧ＶＢＭ３をＶＢ
Ｍ２より低くしたことにより、ＩＧＢＴ並の安全動作領
域が得られる。図３の等価回路から明らかなようにVM2
は、Ｍ３に印加される電圧ＶＭ３からＱ２のベース−エ
ミッタ間電圧ＶＢＥＱ２を除いたものＶＭ２＝ＶＭ３−
ＶＢＥＱ２である。ＶＢＥＱ２はほぼ一定なので、ＶＣ
Ｅの増加によりＶＭ２が増加すると、ＶＭ３が増加す
る。ＶＭ３がVBM3まで増加すると、Ｍ３にリーク電流が
流れ、ＶＭ３は上昇しなくなるので、ＶＭ２の最大値Ｖ
Ｍ２maxはＶＢＭ３からＶＢＥＱ２を除いたものＶＭ２m
ax＝ＶＢＭ３−ＶＢＥＱ２になる。このためＶＢＭ３を
ＶＢＭ２より低くすれば、ＶＭ２はＶＢＭ２より低くな
る。このためＭ２の限流作用が失われずＩＧＢＴ並の安
全動作領域が得られる。The source-drain withstand voltage VBM3 of M3 is VB3.
By setting it lower than M2, a safe operation area comparable to IGBT can be obtained. As is clear from the equivalent circuit of FIG.
Is the voltage obtained by subtracting the base-emitter voltage VBEQ2 of Q2 from the voltage VM3 applied to M3. VM2 = VM3-
VBEQ2. Since VBEQ2 is almost constant, VC
When VM2 increases due to an increase in E, VM3 increases. When VM3 increases to VBM3, a leak current flows to M3, and VM3 does not rise.
M2max is VM2m obtained by removing VBEQ2 from VBM3.
ax = VBM3-VBEQ2. Therefore, if VBM3 is set lower than VBM2, VM2 becomes lower than VBM2. As a result, the current limiting function of M2 is not lost, and a safe operation area comparable to that of the IGBT is obtained.
【００１５】またＭ３のチャネル長Ｌを少なくとも一部
分小さくする、エミッタ電極と短絡されたｐ型層を設
け、この層とサイリスタのｐベース層間の距離を少なく
とも一部分Ｍ３のチャネル長より小さくするなどの方法
により、部分的にＶＢＭ３の低い領域を設けＶＢＭ３を
ＶＢＭ２より低くすることで、ＩＧＢＴ並の安全動作領
域が得られると同時に、Ｍ３のチャネル長Ｌが大きな部
分を残すことができる。Ｌを一様に小さくしてＶＢＭ３
を低くすると、ｎ−１層１への電子注入が減少してサイ
リスタがオンしにくくなり抵抗損失が増えるが、この場
合Ｌが大きな部分からの電子注入があるため、フローテ
ィング電位のサイリスタのｐベースの特徴であるオンし
やすいこと、低抵抗損失であることを維持しながら、同
時に広い安全動作領域を維持できる。A method of reducing the channel length L of M3 at least partially, providing a p-type layer short-circuited with the emitter electrode, and at least partially reducing the distance between this layer and the p-base layer of the thyristor to be smaller than the channel length of M3. Thus, by providing a region where VBM3 is low partially and making VBM3 lower than VBM2, a safe operation region similar to IGBT can be obtained, and a portion where the channel length L of M3 is large can be left. VBM3
Lowering the electron injection into the n-1 layer 1, the thyristor is hard to turn on, and the resistance loss increases. In this case, since the electron injection from a portion where L is large, the p base of the thyristor having the floating potential is used. A wide safe operation area can be maintained at the same time while maintaining the characteristics of easy turning on and low resistance loss.
【００１６】さらに、これらの複合半導体装置を複数個
接続し、さらにＶＢＭ３がＶＢＭ２より低い部分をＭ３
のチャネル長方向及びそれに垂直な方向で交互に設けた
ことで、Ｌが大きな部分が面内で均一に設けられるの
で、ｎ−１層１への電子注入が均一に行われ、装置が面
内で均一に動作する。このため電流集中による装置の破
壊を防止でき、従来装置より大きな電流を制御可能であ
る。Further, a plurality of these composite semiconductor devices are connected, and a portion where VBM3 is lower than VBM2 is
Are alternately provided in the channel length direction and the direction perpendicular thereto, so that a portion having a large L is uniformly provided in the plane, so that the electron injection into the n-1 layer 1 is performed uniformly, and the device becomes in-plane. Works uniformly. For this reason, destruction of the device due to current concentration can be prevented, and a larger current than in the conventional device can be controlled.
【００１７】また、MISFETのドレイン層とチャネル層の
間に低キャリア濃度の領域を設けることで、ＶＢＭ２が
向上しＶＢＭ３より大きくなるので、広い安全動作領域
が得られる。このときＬを小さくする必要がないので、
ｎ−１層１への電子注入は損なわれない。このためフロ
ーティング電位のｐベースの特徴であるオンしやすいこ
と、低抵抗損失であることを維持しながら、同時に広い
安全動作領域を維持できる。Further, by providing a region having a low carrier concentration between the drain layer and the channel layer of the MISFET, VBM2 is improved and becomes larger than VBM3, so that a wide safe operation region can be obtained. At this time, there is no need to reduce L,
The electron injection into the n-1 layer 1 is not impaired. For this reason, it is possible to maintain a wide safe operation area while maintaining the p-base characteristic of the floating potential, that is, easy on and low resistance loss.
【００１８】また、サイリスタのｐベース層とエミッタ
電極間に、ＶＢＭ２より低いツェナー電圧のツェナーダ
イオードをサイリスタのｐベース層にカソード電極を向
けて設けることにより、実効的なＶＢＭ３がツェナー電
圧になるので、Ｍ２にVBM2以上の電圧が印加されない。
このときＶＢＭ３がツェナー電圧になるまでは、サイリ
スタのｐベース層の電位は固定されずフローティング電
位となる。このためフローティング電位のｐベースを持
つサイリスタの特徴であるオンしやすいこと、低抵抗損
失であることを維持しながら、同時に広い安全動作領域
を維持できる。また、サイリスタのｐベース層とｐ１層
１４の間の少なくとも一部に、サイリスタのｐベース層
とｐ１層１４にそれぞれ接しかつ主表面に露出するよう
に、低キャリア濃度のｐ型層を設けることで、サイリス
タのｐベース層とエミッタ電極間が、ｐ型層で接続され
るため、サイリスタのｐベース層の電位が低くなる。こ
のためＶＭ２が低くなり、ＶＢＭ２以上の電圧が印加さ
れにくくなり、安全動作領域が広くなる。このとき、サ
イリスタのｐベース層はこの低キャリア濃度のｐ型層を
通じて、エミッタ電極と短絡されるが、このｐ型層は抵
抗が高いので、ｐベース層とエミッタ電極間の抵抗は高
いままである。このためフローティング電位のｐベース
を持つサイリスタの特徴であるオンしやすいこと、低抵
抗損失であることを損なわず、同時に広い安全動作領域
を維持できる。Further, by providing a Zener diode having a Zener voltage lower than VBM2 between the p base layer of the thyristor and the emitter electrode with the cathode electrode directed to the p base layer of the thyristor, the effective VBM 3 becomes the Zener voltage. , M2 are not applied with a voltage higher than VBM2.
At this time, until VBM3 becomes the Zener voltage, the potential of the p base layer of the thyristor is not fixed but becomes a floating potential. For this reason, it is possible to maintain a wide safe operation area while maintaining the thyristor having the p base of the floating potential, which is easy to turn on and has low resistance loss. In addition, a p-type layer having a low carrier concentration is provided at least in part between the p base layer and the p1 layer of the thyristor so as to be in contact with the p base layer and the p1 layer of the thyristor and to be exposed on the main surface. Since the p-type layer connects the p-base layer of the thyristor and the emitter electrode, the potential of the p-base layer of the thyristor decreases. For this reason, VM2 becomes low, it becomes difficult to apply a voltage higher than VBM2, and the safe operation area is widened. At this time, the p base layer of the thyristor is short-circuited to the emitter electrode through the low carrier concentration p type layer, but since the p type layer has a high resistance, the resistance between the p base layer and the emitter electrode remains high. is there. For this reason, it is possible to maintain a wide safe operation area without impairing the characteristics of the thyristor having the p base of the floating potential, that is, the thyristor is easily turned on and has low resistance loss.
【００１９】この結果、本発明の複合半導体装置は抵抗
損失（オン電圧）が小さく、同時に広い安全動作領域を
持つ。As a result, the composite semiconductor device of the present invention has a small resistance loss (ON voltage) and has a wide safe operation area.
【００２０】[0020]
【実施例】以下、本発明の実施例を図１により説明す
る。図１にその断面構造及び表面の構造を示すこの半導
体装置は、ｎ−基板（ｎ−１層）１の裏面にｐ＋層２が
形成されている。このｐ＋層２に低抵抗で接触してコレ
クタ電極（Ｃ）３が設けられている。ｎ−基板表面には
ゲート電極５と絶縁膜６からなる絶縁ゲートＧ１，ゲー
ト電極７と絶縁膜８からなる絶縁ゲートＧ２が形成され
ている。絶縁ゲートＧ１下に達するようにｎ＋１層１
１，ｎ＋２層１２が絶縁ゲートＧ１をはさんで主表面か
ら形成されている。また絶縁ゲートＧ２をはさんでｎ＋
２層１２と反対側にｎ＋３層１３が、Ｇ２下に達するよ
うに主表面から形成されている。ｎ＋１層１１，ｎ＋２
層１２を取り囲むようにｐ１層１４が、ｎ＋３層１３を
取り囲むようにｐ２層１５がそれぞれ設けられている。
ここでｐ１層１４とｐ２層１５はその間隔が異なる領域
が最低限２つ以上存在するように設けられている。ｎ＋
１層１１に低抵抗で接触して電極４が設けられている。
ｎ＋２層２とｐ１層１４に低抵抗で接触してエミッタ電
極（Ｅ）９が形成されている。ｎ＋３層１３に低抵抗で
接触して電極１０が設けられている。絶縁ゲートＧ１と
Ｇ２の電極は低抵抗の配線電極により接続されている。
また電極４と電極１０も別の低抵抗の配線電極により接
続されている。An embodiment of the present invention will be described below with reference to FIG. In this semiconductor device whose cross-sectional structure and front surface structure are shown in FIG. 1, a p + layer 2 is formed on the back surface of an n− substrate (n−1 layer) 1. A collector electrode (C) 3 is provided in contact with the p + layer 2 with low resistance. An insulated gate G1 composed of a gate electrode 5 and an insulating film 6 and an insulated gate G2 composed of a gate electrode 7 and an insulating film 8 are formed on the surface of the n- substrate. N + 1 layer 1 so as to reach below insulating gate G1
The 1, n + 2 layer 12 is formed from the main surface across the insulating gate G1. In addition, n +
On the opposite side of the two layers 12, an n + 3 layer 13 is formed from the main surface so as to reach below G2. n + 1 layer 11, n + 2
A p1 layer 14 is provided so as to surround the layer 12, and a p2 layer 15 is provided so as to surround the n + 3 layer 13.
Here, the p1 layer 14 and the p2 layer 15 are provided such that at least two or more regions having different intervals exist. n +
The electrode 4 is provided in contact with the first layer 11 with low resistance.
An emitter electrode (E) 9 is formed in contact with the n + 2 layer 2 and the p1 layer 14 with low resistance. The electrode 10 is provided in contact with the n + 3 layer 13 with low resistance. The electrodes of the insulated gates G1 and G2 are connected by a low-resistance wiring electrode.
The electrode 4 and the electrode 10 are also connected by another low-resistance wiring electrode.
【００２１】この半導体装置の等価回路及び動作原理
は、図２の従来例と同じである。これに加えこの半導体
装置は、ｐ１層１４とｐ２層１５の間隔が広い（Ｌ）領
域と狭い（ＬＳ）領域が存在する。このｐ１層１４とｐ
２層１５の間隔の広い領域と、狭い領域は、例えば図１
に示したように絶縁ゲートＧ２の幅を変え、この絶縁ゲ
ートＧ２をマスクとするゲートセルフアライン手法でｐ
１層１４及びｐ２層１５を形成することで設けることが
可能である。The equivalent circuit and operation principle of this semiconductor device are the same as those of the conventional example shown in FIG. In addition to this, this semiconductor device has a wide (L) region and a narrow (LS) region where the distance between the p1 layer 14 and the p2 layer 15 is large. This p1 layer 14 and p
The wide area and the narrow area of the two layers 15 are, for example, as shown in FIG.
The width of the insulated gate G2 is changed as shown in FIG.
It can be provided by forming the first layer 14 and the p2 layer 15.
【００２２】Ｍ３のソース−ドレイン耐圧ＶＢＭ３は、
ｐ１層１４とｐ２層１５の間の狭いＬＳの部分のｎ−１
層１が空乏化しパンチスルーする電圧で決まる。このた
めＬＳを小さくし、ＶＢＭ３がＶＢＭ２以下とすること
で、Ｍ２に過剰な電圧が印加されず広い安全動作領域が
得られる。またｐ１層１４とｐ２層１５の間隔の広いＬ
の領域が設けられているため、ｎ−１層１への電子注入
は損なわれない。この結果、フローティング電位のｐベ
ースを持つサイリスタの特徴であるオンしやすいこと、
低抵抗損失であることを維持しながら、同時に広い安全
動作領域を維持できる。なお、好ましくはＬは６０μｍ
以下、ＬＳは３０μｍ以下とするのがよい。The source-drain breakdown voltage VBM3 of M3 is
n-1 of the narrow LS portion between the p1 layer 14 and the p2 layer 15
It is determined by the voltage at which layer 1 is depleted and punches through. Therefore, by reducing LS and setting VBM3 to VBM2 or less, an excessive voltage is not applied to M2, and a wide safe operation area can be obtained. Also, the distance L between the p1 layer 14 and the p2 layer 15 is large.
Is provided, the electron injection into the n-1 layer 1 is not impaired. As a result, it is easy to turn on which is a feature of the thyristor having the p base of the floating potential.
While maintaining low resistance loss, a wide safe operating area can be maintained at the same time. Preferably, L is 60 μm
Hereinafter, LS is preferably set to 30 μm or less.
【００２３】また、この実施例ではｐ１層１４とｐ２層
１５の間の狭い部分を、ｐ１層１４とｐ２層１５を共に
近付けることで形成しているが、図４に示す別の実施例
のようにｐ１層１４のみの幅を変えた場合、サイリスタ
Ｔｈ１の形状が均一になるので、電流集中が生じにく
い。このため図１の実施例に比べさらに大電流の制御が
可能となる。Further, in this embodiment, a narrow portion between the p1 layer 14 and the p2 layer 15 is formed by bringing the p1 layer 14 and the p2 layer 15 close to each other. When the width of only the p1 layer 14 is changed as described above, the shape of the thyristor Th1 becomes uniform, so that current concentration hardly occurs. Therefore, it is possible to control a larger current than in the embodiment of FIG.
【００２４】以下、本発明の別の実施例を図５により説
明する。図５にその断面構造と表面構造を示すこの半導
体装置は、ｎ−基板（ｎ−１層）１の裏面にｐ＋層２が
形成されている。このｐ＋層２に低抵抗で接触してコレ
クタ電極（Ｃ）３が設けられている。ｎ−基板表面には
ゲート電極５と絶縁膜６からなる絶縁ゲートＧ１，ゲー
ト電極７と絶縁膜８からなる絶縁ゲートＧ２が形成され
ている。絶縁ゲートＧ１下に達するようにｎ＋１層１
１，ｎ＋２層１２が絶縁ゲートＧ１をはさんで主表面か
ら形成されている。また絶縁ゲートＧ２をはさんでｎ＋
２層１２と反対側にｎ＋３層１３が、Ｇ２下に達するよ
うに主表面から形成されている。ｎ＋１層１１，ｎ＋２
層１２を取り囲むようにｐ１層１４が、ｎ＋３層１３を
取り囲むようにｐ２層１５がそれぞれ設けられている。
ｐ１層１４とｐ２層１５の間の少なくとも一部分に主表
面からｐ３層１６が設けられている。さらにｐ１層１４
とｐ２層１５の間の主表面の少なくとも一部分がｎ−１
層１でおおわれている。ｎ＋１層１１に低抵抗で接触し
て電極４が設けられている。ｎ＋２層２とｐ１層１４に
低抵抗で接触してエミッタ電極（Ｅ）９が形成されてい
る。ｎ＋３層１３に低抵抗で接触して電極１０が設けら
れている。絶縁ゲートＧ１とＧ２の電極は低抵抗の配線
電極により接続されている。また電極４と電極１０も別
の低抵抗の配線電極により接続されている。Hereinafter, another embodiment of the present invention will be described with reference to FIG. In this semiconductor device whose sectional structure and surface structure are shown in FIG. 5, a p + layer 2 is formed on the back surface of an n− substrate (n−1 layer) 1. A collector electrode (C) 3 is provided in contact with the p + layer 2 with low resistance. An insulated gate G1 composed of a gate electrode 5 and an insulating film 6 and an insulated gate G2 composed of a gate electrode 7 and an insulating film 8 are formed on the surface of the n- substrate. N + 1 layer 1 so as to reach below insulating gate G1
The 1, n + 2 layer 12 is formed from the main surface across the insulating gate G1. In addition, n +
On the opposite side of the two layers 12, an n + 3 layer 13 is formed from the main surface so as to reach below G2. n + 1 layer 11, n + 2
A p1 layer 14 is provided so as to surround the layer 12, and a p2 layer 15 is provided so as to surround the n + 3 layer 13.
At least a portion between the p1 layer 14 and the p2 layer 15 is provided with a p3 layer 16 from the main surface. Furthermore, the p1 layer 14
And at least a part of the main surface between the p2 layer 15 and n-1
It is covered with layer 1. The electrode 4 is provided in contact with the n + 1 layer 11 with low resistance. An emitter electrode (E) 9 is formed in contact with the n + 2 layer 2 and the p1 layer 14 with low resistance. The electrode 10 is provided in contact with the n + 3 layer 13 with low resistance. The electrodes of the insulated gates G1 and G2 are connected by a low-resistance wiring electrode. The electrode 4 and the electrode 10 are also connected by another low-resistance wiring electrode.
【００２５】この半導体装置の等価回路が図３の等価回
路と異なる点はＭ３と並列に、ｐ１層１４，ｎ−１層
１，ｐ３層１６からなるｐチャネルMISFET（Ｍ４）とｐ
３層１６，ｎ−１層１，ｐ２層１５からなるｐチャネル
MISFET（Ｍ５）が直列接続されていることである。ま
た、動作原理は、図２の従来例と同じである。この半導
体装置のＶＢＭ３は、ｐ１層１４とｐ３層１６の間の長
さＬＳ１のｎ−１層１が空乏化する電圧にｐ３層１６と
ｐ２層１５の間の長さＬＳ２のｎ−１層１が空乏化する
電圧を加えたものになる。このためＬＳ１及びＬＳ２の
幅を十分小さくすることで、ＶＢＭ３をＶＢＭ２以下に
できる。これにより図１の実施例と同様に、Ｍ２に過剰
な電圧が印加されず広い安全動作領域が得られる。ま
た、ｐ１層１４とｐ２層１５の間隔の広い領域が設けら
れているため、ｎ−１層１への電子注入は損なわれな
い。この結果、フローティング電位のｐベースを持つサ
イリスタの特徴であるオンしやすいこと、低抵抗損失で
あることを維持しながら、同時に広い安全動作領域を維
持できる。さらに本実施例では、電流が飽和していない
オン状態ではｐ＋３層１６がフローティング電位とな
る。このため、図１の実施例に比べｐ１層１４からのホ
ールの引き抜きが少ないので、ｎ−１層１の正孔濃度が
高まるため、さらに抵抗損失を低減できる。The difference between the equivalent circuit of this semiconductor device and the equivalent circuit of FIG. 3 is that a p-channel MISFET (M4) composed of a p1 layer 14, an n-1 layer 1, and a p3 layer 16 is connected in parallel with M3.
P channel composed of three layers 16, n-1 layer 1, and p2 layer 15
The MISFET (M5) is connected in series. The operation principle is the same as that of the conventional example shown in FIG. The VBM3 of this semiconductor device is applied to a voltage at which the n-1 layer 1 having a length LS1 between the p1 layer 14 and the p3 layer 16 is depleted to an n-1 layer having a length LS2 between the p3 layer 16 and the p2 layer 15. 1 is the sum of the depletion voltage. For this reason, by making the width of LS1 and LS2 sufficiently small, VBM3 can be made equal to or less than VBM2. Thus, as in the embodiment of FIG. 1, an excessive voltage is not applied to M2, and a wide safe operation area can be obtained. Further, since a region with a large interval between the p1 layer 14 and the p2 layer 15 is provided, electron injection into the n-1 layer 1 is not impaired. As a result, it is possible to maintain a wide safe operation area while maintaining the thyristor having the p base of the floating potential, which is easy to turn on and has low resistance loss. Further, in this embodiment, the p + 3 layer 16 has a floating potential in the ON state where the current is not saturated. For this reason, the number of holes extracted from the p1 layer 14 is smaller than that in the embodiment of FIG. 1, and the hole concentration of the n-1 layer 1 is increased, so that the resistance loss can be further reduced.
【００２６】本発明の、他の実施例を図６に示す。この
半導体装置は図５の半導体装置のｐ３層１６に代わり、
ｎ−１層１より低キャリア濃度のｎ−２層２１が設けら
れている点である。ｎ−２層２１を設けることにより、
ｐ１層１４とｐ２層１５の間のｎ層の空乏化する電圧が
減少するため、ＶＢＭ３をＶＢＭ２以下にできる。この
ため図５の装置と同様の効果がある。もちろんｎ−２層
２１はｐ１層１４とｐ２層１５にまたがって形成しても
良く、その場合さらに空乏化する電圧を低減できる。FIG. 6 shows another embodiment of the present invention. This semiconductor device replaces the p3 layer 16 of the semiconductor device of FIG.
The point is that an n-2 layer 21 having a lower carrier concentration than the n-1 layer 1 is provided. By providing the n-2 layer 21,
Since the voltage at which the n-layer between the p1 layer 14 and the p2 layer 15 is depleted is reduced, VBM3 can be reduced to VBM2 or less. Therefore, the same effect as that of the apparatus shown in FIG. 5 is obtained. Of course, the n-2 layer 21 may be formed over the p1 layer 14 and the p2 layer 15, and in that case, the voltage for depletion can be further reduced.
【００２７】本発明の、他の実施例を図７に示す。図７
に断面構造と表面構造を示すこの半導体装置は、図５の
実施例のフローティング電位のｐ３層１６に低抵抗接触
して電極２３を設け、エミッタ電極と低抵抗の配線で接
続した構成である。本装置では、ＶＢＭ３はｐ３層１６
とｐ２層１５の間の長さＬＳ２のｎ−１層１が空乏化す
る電圧であるから、ＬＳ２を小さくしてＶＢＭ３をＶＢ
Ｍ２以下にできる。これにより図１の実施例と同様に、
Ｍ２に過剰な電圧が印加されず広い安全動作領域が得ら
れる。また、ｐ１層１４とｐ２層１５の間隔の広い領域
が設けられているため、ｎ−１層１への電子注入は損な
われない。この結果、フローティング電位のｐベースを
持つサイリスタの特徴であるオンしやすいこと、低抵抗
損失であることを維持しながら、同時に広い安全動作領
域を維持できる。FIG. 7 shows another embodiment of the present invention. FIG.
This semiconductor device has a cross-sectional structure and a surface structure, and has a structure in which an electrode 23 is provided in low resistance contact with the p3 layer 16 of the floating potential of the embodiment of FIG. In this device, VBM3 is the p3 layer 16
Since the n-1 layer 1 having the length LS2 between the gate and the p2 layer 15 is depleted, LS2 is reduced to reduce VBM3 to VB3.
M2 or less. Thereby, similarly to the embodiment of FIG.
No excessive voltage is applied to M2, and a wide safe operation area can be obtained. Further, since a region with a large interval between the p1 layer 14 and the p2 layer 15 is provided, electron injection into the n-1 layer 1 is not impaired. As a result, it is possible to maintain a wide safe operation area while maintaining the thyristor having the p base of the floating potential, which is easy to turn on and has low resistance loss.
【００２８】図８に、本発明の他の実施例を示す。本装
置が図２の従来例と異なる点は、MISFETのドレイン層で
あるｎ＋１層１１とｐ１層１４との間にｎ＋１層１１よ
りキャリア濃度の低いｎ−２層２１を設けたことであ
る。これによりＶＢＭ２を向上させＶＢＭ３より大きく
できる。またＭ３のチャネル長Ｌは変化しないので、ｎ
−１層１への電子注入を損なうことない。このため、フ
ローティング電位のｐベースを持つサイリスタの特徴で
あるオンしやすいこと、低抵抗損失であることを維持し
ながら、同時に広い安全動作領域を維持できる。FIG. 8 shows another embodiment of the present invention. This device is different from the conventional example of FIG. 2 in that an n−2 layer 21 having a lower carrier concentration than the n + 1 layer 11 is provided between the n + 1 layer 11 and the p1 layer 14 which are the drain layers of the MISFET. Thereby, VBM2 can be improved and made larger than VBM3. Since the channel length L of M3 does not change, n
-1 Does not impair electron injection into layer 1. For this reason, it is possible to maintain a wide safe operation area while maintaining the characteristics of the thyristor having the p base of the floating potential, that is, easy on and low resistance loss.
【００２９】図９に、本発明の他の実施例を示す。本装
置が図８の実施例と異なるのは、MISFETのゲート下のみ
にｎ−２層２１を設けたことである。この場合もＶＢＭ
２が向上しＶＢＭ３より大きくできる。このため図８の
実施例と同様の効果が得られる。FIG. 9 shows another embodiment of the present invention. This device differs from the embodiment of FIG. 8 in that the n-2 layer 21 is provided only under the gate of the MISFET. Also in this case, VBM
2 can be improved to be larger than VBM3. Therefore, the same effect as that of the embodiment of FIG. 8 can be obtained.
【００３０】図１０に、本発明の他の実施例を示す。本
装置が図８の実施例と異なるのは、ｎ−２層２１の代わ
りに、ｐ１層１４よりキャリア濃度の低いｐ−層２２を
設けたことである。この場合もＶＢＭ２が向上しＶＢＭ
３より大きくできるため、図８の実施例と同様の効果が
得られる。FIG. 10 shows another embodiment of the present invention. The present device differs from the embodiment of FIG. 8 in that a p− layer 22 having a lower carrier concentration than the p1 layer 14 is provided instead of the n−2 layer 21. Also in this case, VBM2 is improved and VBM is improved.
3, the same effect as in the embodiment of FIG. 8 can be obtained.
【００３１】図１１に、本発明の他の実施例を示す。本
装置が図２の従来例と異なる点は、サイリスタのｐベー
ス層とエミッタ電極間に、ＶＢＭ２より低いツェナー電
圧のツェナーダイオードＤ２０がサイリスタのｐベース
層にカソード電極を向けて設けられていることである。
このため本装置では、ＶＢＭ３がツェナー電圧となるの
でＭ２にＶＢＭ２以上の電圧が印加されない。またＭ３
のチャネル長Ｌは変化しないので、ｎ−１層１への電子
注入を損なうことない。このため、フローティング電位
のｐベースを持つサイリスタの特徴であるオンしやすい
こと、低抵抗損失であることを維持しながら、同時に広
い安全動作領域を維持できる。このツェナーダイオード
は、例えば一例をあげると、絶縁ゲートＧ２に一般的に
使われている多結晶シリコンを使って、同時に集積化し
て形成することも可能である。FIG. 11 shows another embodiment of the present invention. This device is different from the conventional example of FIG. 2 in that a Zener diode D20 having a Zener voltage lower than VBM2 is provided between the p base layer of the thyristor and the emitter electrode with the cathode electrode facing the p base layer of the thyristor. It is.
For this reason, in this device, since VBM3 becomes a Zener voltage, a voltage higher than VBM2 is not applied to M2. Also M3
Does not change, the electron injection into the n-1 layer 1 is not impaired. For this reason, it is possible to maintain a wide safe operation area while maintaining the characteristics of the thyristor having the p base of the floating potential, that is, easy on and low resistance loss. For example, this zener diode can be simultaneously integrated and formed using, for example, polycrystalline silicon generally used for the insulated gate G2.
【００３２】本発明の他の実施例を、図１２に示す。本
半導体装置が、図２の従来装置と異なる点は、サイリス
タのｐベース層とｐ１層１４の間の少なくとも一部に、
サイリスタのｐベース層とｐ１層１４にそれぞれ接しか
つ主表面に露出するように、低キャリア濃度のｐ−層２
４を設けたことである。このｐ−層２４のシートキャリ
ア濃度は、全ての動作状態においてｐ−層２４が完全に
空乏化しない最低限の濃度で、典型的な値としては１×
１０13cm-2以下が好ましい。本装置ではサイリスタのｐ
ベース層とエミッタ電極間がｐ−層２４で接続されるた
め、サイリスタのｐベース層の電位が低くなる。これは
実効的にＶＢＭ３が低くなったことに相当する。このた
めＶＭ２が低くなり、ＶＢＭ２以上の電圧が印加されに
くく、安全動作領域が広くなる。このとき、サイリスタ
のｐベース層はこの低キャリア濃度のｐ型層を通じて、
エミッタ電極と短絡されるが、このｐ型層は抵抗が高い
ので、ｐベース層とエミッタ電極間の抵抗は高いままで
ある。すなわちｐベース層は実質フローティング状態と
なる。このためフローティング電位のｐベースを持つサ
イリスタの特徴であるオンしやすいこと、低抵抗損失で
あることを損なわず、同時に広い安全動作領域を維持で
きる。FIG. 12 shows another embodiment of the present invention. This semiconductor device is different from the conventional device of FIG. 2 in that at least a portion between the p base layer and the p1 layer 14 of the thyristor
The p- layer 2 having a low carrier concentration is in contact with the p base layer and the p1 layer 14 of the thyristor and exposed on the main surface.
4 is provided. The sheet carrier concentration of the p − layer 24 is a minimum concentration at which the p − layer 24 is not completely depleted in all operating states, and is typically 1 ×
It is preferably 10 13 cm -2 or less. In this device, the thyristor p
Since the base layer and the emitter electrode are connected by the p − layer 24, the potential of the p base layer of the thyristor becomes low. This is equivalent to the fact that VBM3 is effectively reduced. For this reason, VM2 becomes low, it is difficult to apply a voltage higher than VBM2, and the safe operation area is widened. At this time, the p base layer of the thyristor passes through the low carrier concentration p-type layer.
Although short-circuited with the emitter electrode, the resistance between the p-base layer and the emitter electrode remains high because the p-type layer has a high resistance. That is, the p base layer is substantially in a floating state. For this reason, it is possible to maintain a wide safe operation area without impairing the characteristics of the thyristor having the p base of the floating potential, that is, the thyristor is easily turned on and has low resistance loss.
【００３３】図１３に図１の実施例を複数個集積する場
合の装置の実施例を示す。図は本装置の断面構造及び表
面構造を示す。本実施例ではｐ１層１４とｐ２層１５の
間隔が広い（Ｌ）領域と狭い（ＬＳ）領域が、装置の表
面の面内でｐ１層１４からｐ２層１５へ向かう方向及び
それに垂直な方向で交互に設けられている。これによ
り、ｎ−１層１への電子注入が均一に行われるため素子
が面内で均一に動作するので、電流集中による半導体素
子の破壊を防止でき、従来素子より大きな電流を半導体
装置を破壊せずに制御可能である。実際の装置では上記
の各実施例が図に示したような形で１００から１０００
００個程度集積される。また本半導体装置のゲート電
極，エミッタ電極はそれぞれ独立してはおらず、図には
示していない他の領域で互いに接続されている。FIG. 13 shows an embodiment of the apparatus when a plurality of the embodiments of FIG. 1 are integrated. The figure shows the cross-sectional structure and the surface structure of this device. In the present embodiment, the wide (L) region and the narrow (LS) region between the p1 layer 14 and the p2 layer 15 are formed in the direction from the p1 layer 14 to the p2 layer 15 and in the direction perpendicular thereto in the plane of the device surface. They are provided alternately. As a result, electron injection into the n-1 layer 1 is performed uniformly, so that the element operates uniformly in the plane. Therefore, destruction of the semiconductor element due to current concentration can be prevented, and a larger current than the conventional element can be destroyed in the semiconductor device. Controllable without. In an actual apparatus, each of the above embodiments is 100 to 1000 in the form shown in the figure.
About 00 are integrated. Further, the gate electrode and the emitter electrode of the present semiconductor device are not independent of each other, but are connected to each other in other regions not shown in the figure.
【００３４】以上、ｐ１層１４とｐ２層１５の耐圧よ
り、ｎ＋２層１２とｎ＋１層１１の耐圧を大きくする各
種の構造について述べてきたが、さらにｎ＋１層１１と
絶縁ゲートＧ１の電極５の印加電圧にも注意しなければ
ならない。つまり、ターンオフ時にゲート電圧はエミッ
タ電位に対し負の電位の方向に変化するのに対し、ｎ＋
１層１１は、コレクタ電位の上昇により、正の電位の方
向に変動するため、ゲート絶縁膜６に過電圧が加わり絶
縁破壊しやすくなる。従って、ｐ１層１４とｐ２層１５
の耐圧より、ｎ＋２層１２とｎ＋１層１１の耐圧を大き
くすると同時に、ｎ＋層１１とゲート電極５の間に印加
される電圧がその絶縁耐圧を越えないように、ｐ１層１
４とｐ２層１５の耐圧を低くしてｎ＋１層１１の電位を
下げなければならない。好ましくは、ｐ１層１４とｐ２
層１５の耐圧を、ｎ＋層１１とゲート電極５の絶縁耐圧
の１／２以下にすることが絶縁膜６の信頼性上好まし
い。Although various structures for increasing the breakdown voltage of the n + 2 layer 12 and the n + 1 layer 11 above the breakdown voltage of the p1 layer 14 and the p2 layer 15 have been described above, the application of the n + 1 layer 11 and the electrode 5 of the insulating gate G1 is further described. You must also pay attention to the voltage. That is, at the time of turn-off, the gate voltage changes in the direction of a negative potential with respect to the emitter potential, while n +
The first layer 11 changes in the direction of the positive potential due to an increase in the collector potential, so that an overvoltage is applied to the gate insulating film 6 and dielectric breakdown easily occurs. Therefore, the p1 layer 14 and the p2 layer 15
The withstand voltage of the n + 2 layer 12 and the n + 1 layer 11 is made larger than the withstand voltage of the p1 layer 1 so that the voltage applied between the n + layer 11 and the gate electrode 5 does not exceed the withstand voltage.
4 and the p2 layer 15 must have a lower withstand voltage to lower the potential of the n + 1 layer 11. Preferably, p1 layer 14 and p2
It is preferable from the viewpoint of reliability of the insulating film 6 that the withstand voltage of the layer 15 be equal to or less than の of the withstand voltage of the n + layer 11 and the gate electrode 5.
【００３５】なお、上記各実施例は、いずれも縦型の複
合半導体装置であるが、本発明は横型の素子にも適用で
きる。また、複数の実施例の構造を併用することも可能
である。さらに、各半導体層の導電型すなわちｐとｎを
逆極性にしてもよい。Although each of the above embodiments is a vertical composite semiconductor device, the present invention can be applied to a horizontal element. It is also possible to use the structures of a plurality of embodiments together. Further, the conductivity type of each semiconductor layer, that is, p and n may have opposite polarities.
【００３６】図１４は本発明の半導体装置を用いて、電
力変換装置の１つである電動機駆動用インバータ装置を
構成した一例を示したものである。本発明の６個の半導
体装置で電圧型インバータ回路を構成し、三相誘導電動
機３０を制御する例で、その基本回路は本発明の半導体
装置３１，フライホイールダイオード３２，スナバダイ
オード３３，スナバ抵抗３４，スナバコンデンサ３５か
ら構成されている。従来素子に比べ、損失が低い本発明
の半導体装置３１により、インバータ装置の低損失化や
大容量化が達成でき、さらに安全動作領域が広いため、
スナバ回路の縮小及び削除が可能になる。従って電力変
換装置の一層の低損失化，小型化が実現できる。FIG. 14 shows an example in which a semiconductor device of the present invention is used to constitute an inverter device for driving a motor, which is one of power conversion devices. In the example in which a voltage type inverter circuit is constituted by six semiconductor devices of the present invention and a three-phase induction motor 30 is controlled, the basic circuit is a semiconductor device 31, a flywheel diode 32, a snubber diode 33, a snubber resistor of the present invention. 34, and a snubber capacitor 35. The semiconductor device 31 of the present invention, which has a lower loss than the conventional device, can achieve a low loss and a large capacity of the inverter device and further has a wide safe operation area.
The snubber circuit can be reduced and deleted. Therefore, it is possible to further reduce the loss and the size of the power converter.
【００３７】[0037]
【発明の効果】本発明によれば、抵抗損失（オン電圧）
が小さく、安全動作領域の広い複合半導体装置が得られ
るとともに、低損失で小型の電力変換装置を実現でき
る。According to the present invention, the resistance loss (ON voltage)
In addition to obtaining a composite semiconductor device having a small size and a wide safe operation area, a small power converter with low loss can be realized.
【図１】本発明の一実施例。FIG. 1 shows an embodiment of the present invention.
【図２】従来例。FIG. 2 is a conventional example.
【図３】図２の等価回路。FIG. 3 is an equivalent circuit of FIG. 2;
【図４】本発明の他の実施例。FIG. 4 shows another embodiment of the present invention.
【図５】本発明の他の実施例。FIG. 5 shows another embodiment of the present invention.
【図６】本発明の他の実施例。FIG. 6 shows another embodiment of the present invention.
【図７】本発明の他の実施例。FIG. 7 shows another embodiment of the present invention.
【図８】本発明の他の実施例。FIG. 8 shows another embodiment of the present invention.
【図９】本発明の他の実施例。FIG. 9 shows another embodiment of the present invention.
【図１０】本発明の他の実施例。FIG. 10 shows another embodiment of the present invention.
【図１１】本発明の他の実施例。FIG. 11 shows another embodiment of the present invention.
【図１２】本発明の他の実施例。FIG. 12 shows another embodiment of the present invention.
【図１３】本発明の、素子を複数個集積化する場合の実
施例で、図１の実施例を複数個集積化した例。FIG. 13 is an embodiment of the present invention in which a plurality of elements are integrated, in which a plurality of the embodiments of FIG. 1 are integrated.
【図１４】本発明の半導体装置を用いて、電動機駆動用
インバータ装置を構成した一例。FIG. 14 is an example in which a semiconductor device of the present invention is used to form an inverter device for driving a motor.
１，２１…ｎ−１層、２…ｐ＋層、３…コレクタ電極、
４…ｎ＋１層１１の電極、５，７，１８…ゲート電極、
６，８，１９…絶縁膜、９…エミッタ電極、１０…ｎ＋
３層１３の電極、１１，１２，１３…ｎ＋層、１４，１
５，１６…ｐ層、２０…ツェナーダイオード、２２，２
４…ｐ−層、２３…ｐ３層１６の電極。1,21 ... n-1 layer, 2 ... p + layer, 3 ... collector electrode,
4... N + 1 layer 11 electrodes, 5, 7, 18... Gate electrodes,
6, 8, 19 ... insulating film, 9 ... emitter electrode, 10 ... n +
Three-layer 13 electrodes, 11, 12, 13... N + layers, 14, 1
5, 16 ... p layer, 20 ... Zener diode, 22, 2
4 ... p-layer, 23 ... electrodes of p3 layer 16.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 森 睦宏 茨城県日立市大みか町七丁目１番１号 株式会社 日立製作所 日立研究所内 (56)参考文献 特開 平４−196359（ＪＰ，Ａ) 特開 平６−310708（ＪＰ，Ａ) 特開 平６−112496（ＪＰ，Ａ) 特開 平８−255894（ＪＰ，Ａ) 特開 平９−205193（ＪＰ，Ａ) 特開 平８−250705（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/749 H01L 29/74 H01L 29/78 H01L 29/78 652 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Mutsumi Mori 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-4-196359 (JP, A) JP-A-6-310708 (JP, A) JP-A-6-112496 (JP, A) JP-A-8-255894 (JP, A) JP-A-9-205193 (JP, A) JP-A 8-250705 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/749 H01L 29/74 H01L 29/78 H01L 29/78 652
Claims (14)
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域，第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第３の半導体領域と前記第４の半導体領域
の距離が、少なくとも一部分が他の部分に比べ近接して
いることを特徴とする複合半導体装置。A second conductive type second semiconductor region provided on a first conductive type first semiconductor region having a first main surface so as to be exposed at a second main surface; A third semiconductor region of the first conductivity type and a fourth semiconductor region of the first conductivity type provided in the second semiconductor region so as to be exposed on the main surface of the second semiconductor region; A second conductive type fifth semiconductor region and a second conductive type sixth semiconductor region provided so as to be exposed on the second main surface; and the second main surface in the fourth semiconductor region. A seventh semiconductor region of the second conductivity type provided so as to be exposed to the semiconductor device, and a fifth semiconductor region on the second main surface.
A first insulated gate formed over the second semiconductor region, the sixth semiconductor region, and the second semiconductor region, the fourth semiconductor region, and the seventh semiconductor region on the second main surface. A second insulated gate formed; a first electrode on the first main surface in low-resistance contact with the first semiconductor region; a third semiconductor region on the second main surface; 6, a second electrode having a short-circuited semiconductor region, and a gate electrode having a first insulated gate and a second insulated gate short-circuited, wherein the fifth semiconductor region and the seventh semiconductor region are low. The third semiconductor region and the fourth semiconductor region are connected by resistance.
Distance is at least partly closer than other parts
Composite semiconductor device characterized by there.
の少なくとも一部分を前記第４の半導体領域に近付けた
ことを特徴とする複合半導体装置。2. The composite semiconductor device according to claim 1 , wherein at least a part of said third semiconductor region is close to said fourth semiconductor region.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域、第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表 面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第３の半導体領域と前記第４の半導体領域
の間の少なくとも一部分に、第１導電型の第８の半導体
領域を前記第２の主表面に露出するように設けたことを
特徴とする複合半導体装置。3. A first conductive type first having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
And a region exposed to the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to extend out;
A sixth semiconductor region of a second conductivity type and the fourth semiconductor region;
A second conductor provided in the region so as to be exposed at the second main surface.
A seventh semiconductor region of an electric type, and a fifth semiconductor region on the second main surface.
Formed over the semiconductor region and the sixth semiconductor region.
First insulated gate and the second second half on the main table surface was
The conductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate formed by the first main table;
A first electrode having a low resistance contact with the first semiconductor region on the surface;
A pole, a third semiconductor region on the second major surface and a sixth
A second electrode having a short-circuited semiconductor region, and a first insulated gate
And a gate electrode in which the second insulated gate is short-circuited.
The fifth semiconductor region and the seventh semiconductor region have a low resistance.
Connect the at least a portion between the third semiconductor region and the fourth semiconductor region, characterized in that a eighth semiconductor region of the first conductivity type so as to be exposed at the second main surface Composite semiconductor device.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域、第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第３の半導体領域と前記第４の半導体領域
の間の少なくとも一部分に、前記第２の半導体領域より
もキャリア濃度の低い第２導電型の第９の半導体領域を
第２の主表面に露出するように設けたことを特徴とする
複合半導体装置。4. A first conductive type first having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
And a region exposed to the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to extend out;
A sixth semiconductor region of a second conductivity type and the fourth semiconductor region;
A second conductor provided in the region so as to be exposed at the second main surface.
A seventh semiconductor region of an electric type, and a fifth semiconductor region on the second main surface.
Formed over the semiconductor region and the sixth semiconductor region.
A first insulated gate and a second half on the second major surface.
The conductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate formed by the first main table;
A first electrode having a low resistance contact with the first semiconductor region on the surface;
A pole, a third semiconductor region on the second major surface and a sixth
A second electrode having a short-circuited semiconductor region, and a first insulated gate
And a gate electrode in which the second insulated gate is short-circuited.
The fifth semiconductor region and the seventh semiconductor region have a low resistance.
A second conductive type ninth semiconductor region having a lower carrier concentration than the second semiconductor region in at least a portion between the third semiconductor region and the fourth semiconductor region. A composite semiconductor device provided to be exposed on a surface.
と、前記第３の半導体領域及び前記第６の半導体領域を
接続したことを特徴とする複合半導体装置。5. The composite semiconductor device according to claim 3 , wherein said eighth semiconductor region is connected to said third semiconductor region and said sixth semiconductor region.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域、第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第３の半導体領域中に、前記第５の半導体
領域を囲んで、前記第５の半導体領域よりキャリア濃度
の低い第２の導電型の第１０の半導体領域を、前記第２
の主表面に露出するように設けたことを特徴とする複合
半導体装置。6. A first conductive type first having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
And a region exposed to the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to extend out;
A sixth semiconductor region of a second conductivity type and the fourth semiconductor region;
A second conductor provided in the region so as to be exposed at the second main surface.
A seventh semiconductor region of an electric type, and a fifth semiconductor region on the second main surface.
Formed over the semiconductor region and the sixth semiconductor region.
A first insulated gate and a second half on the second major surface.
The conductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate formed by the first main table;
A first electrode having a low resistance contact with the first semiconductor region on the surface;
A pole, a third semiconductor region on the second major surface and a sixth
A second electrode having a short-circuited semiconductor region, and a first insulated gate
And a gate electrode in which the second insulated gate is short-circuited.
The fifth semiconductor region and the seventh semiconductor region have a low resistance.
And connecting the tenth semiconductor region of the second conductivity type having a lower carrier concentration than the fifth semiconductor region to the third semiconductor region, surrounding the fifth semiconductor region.
A composite semiconductor device provided so as to be exposed on a main surface of the composite semiconductor device.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域、第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半 導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第３の半導体領域中に、前記第５の半導体
領域よりキャリア濃度の低い第２の導電型の第１１の半
導体領域を、前記第２の主表面に露出するように、前記
第１の絶縁ゲートの下の一部に前記第５の半導体領域に
接して設けたことを特徴とする複合半導体装置。7. A first conductive type first electrode having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
And a region exposed to the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to extend out;
A sixth semiconductor region of a second conductivity type and the fourth semiconductor region;
A second conductor provided in the region so as to be exposed at the second main surface.
A seventh semiconductor region of an electric type, and a fifth semiconductor region on the second main surface.
Formed over the semiconductor region and the sixth semiconductor region.
A first insulated gate and a second half on the second major surface.
The conductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate formed by the first main table;
A first electrode having a low resistance contact with the first semiconductor region on the surface;
A pole, a third semiconductor region on the second major surface and a sixth
A second electrode are short-circuited semiconductors region, a first insulated gate
And a gate electrode in which the second insulated gate is short-circuited.
The fifth semiconductor region and the seventh semiconductor region have a low resistance.
And connecting the eleventh semiconductor region of the second conductivity type having a lower carrier concentration than that of the fifth semiconductor region to the second main surface in the third semiconductor region. A composite semiconductor device provided below a portion of one of the insulated gates in contact with the fifth semiconductor region.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域及び前記第３の半導体領域に隣接し前記第３の半導体
領域よりキャリア濃度が低い第１導電型の第１２の半導
体領域と、第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第６の半導体領域と、
前記第１２の半導体領域内に前記第２の主表面に露出す
るように設けた第２導電型の第５の半導体領域と、前記
第４の半導体領域内に前記第２の主表面に露出するよう
に設けた第２導電型の第７の半導体領域と、前記第２の
主表面上で第５の半導体領域、第６の半導体領域にまた
がって形成された第１の絶縁ゲートと、前記第２の主表
面上で第２の半導体領域，第４の半導体領域，第７の半
導体領域にまたがって形成された第２の絶縁ゲートと、
前記第１の主表面上で前記第１の半導体領域に低抵抗接
触した第１の電極と、前記第２の主表面上で第３の半導
体領域と第６の半導体領域を短絡した第２の電極と、第
１の絶縁ゲートと第２の絶縁ゲートを短絡したゲート電
極とを有し、前記第５の半導体領域と、前記第７の半導
体領域とを低抵抗接続したことを特徴とする複合半導体
装置。 8. A first conductive type first having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
Region and the third semiconductor adjacent to the third semiconductor region
A twelfth semiconductor of the first conductivity type having a lower carrier concentration than the region
Body region and the second main surface in a third semiconductor region.
A sixth semiconductor region of the second conductivity type provided so as to extend out;
Exposed to the second main surface in the twelfth semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to
In the fourth semiconductor region, exposed to the second main surface.
A seventh semiconductor region of the second conductivity type provided in
On the main surface, the fifth semiconductor region and the sixth semiconductor region
A first insulated gate formed by the second main table;
The second semiconductor region, the fourth semiconductor region, the seventh half
A second insulated gate formed over the conductor region;
A low resistance contact with the first semiconductor region on the first main surface;
A touched first electrode and a third semiconductor on the second major surface.
A second electrode short-circuiting the body region and the sixth semiconductor region;
A gate electrode short-circuiting the first insulated gate and the second insulated gate
A pole, the fifth semiconductor region, and the seventh semiconductor region.
Compound semiconductor characterized by low resistance connection to body region
apparatus.
半導体領域上に第２の主表面に露出するように設けた第
２導電型の第２の半導体領域と、前記第２の主表面に露
出するように前記第２の半導体領域内に設けた第１導電
型の第３の半導体領域及び第１導電型の第４の半導体領
域と、前記第３の半導体領域内に前記第２の主表面に露
出するように設けた第２導電型の第５の半導体領域及び
第２導電型の第６の半 導体領域と、前記第４の半導体領
域内に前記第２の主表面に露出するように設けた第２導
電型の第７の半導体領域と、前記第２の主表面上で第５
の半導体領域、第６の半導体領域にまたがって形成され
た第１の絶縁ゲートと、前記第２の主表面上で第２の半
導体領域，第４の半導体領域，第７の半導体領域にまた
がって形成された第２の絶縁ゲートと、前記第１の主表
面上で前記第１の半導体領域に低抵抗接触した第１の電
極と、前記第２の主表面上で第３の半導体領域と第６の
半導体領域を短絡した第２の電極と、第１の絶縁ゲート
と第２の絶縁ゲートを短絡したゲート電極とを有し、前
記第５の半導体領域と、前記第７の半導体領域を低抵抗
接続し、前記第５の半導体領域と前記第６の半導体領域
の間の耐圧より低いツェナー電圧のツェナーダイオード
を、前記ツェナーダイオードのカソード電極を前記第４
の半導体領域に低抵抗接触し、前記ツェナーダイオード
のアノード電極を前記第２の電極に低抵抗接続して設け
たことを特徴とする複合半導体装置。9. A first conductive type first having a first main surface.
A second portion provided on the semiconductor region so as to be exposed at the second main surface;
A second semiconductor region of a two-conductivity type is exposed on the second main surface.
A first conductive layer provided in the second semiconductor region so that
-Type third semiconductor region and first conductivity-type fourth semiconductor region
And a region exposed to the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to extend out;
And a semi-conductor region of the sixth of the second conductivity type, said fourth semiconductor territory
A second conductor provided in the region so as to be exposed at the second main surface.
A seventh semiconductor region of an electric type, and a fifth semiconductor region on the second main surface.
Formed over the semiconductor region and the sixth semiconductor region.
A first insulated gate and a second half on the second major surface.
The conductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate formed by the first main table;
A first electrode having a low resistance contact with the first semiconductor region on the surface;
A pole, a third semiconductor region on the second major surface and a sixth
A second electrode having a short-circuited semiconductor region, and a first insulated gate
And a gate electrode in which the second insulated gate is short-circuited.
The fifth semiconductor region and the seventh semiconductor region have a low resistance.
And a Zener diode having a Zener voltage lower than a withstand voltage between the fifth semiconductor region and the sixth semiconductor region, and a cathode electrode of the Zener diode being connected to the fourth semiconductor region.
A low resistance contact with the semiconductor region, and an anode electrode of the Zener diode is provided with a low resistance connection to the second electrode.
複合半導体装置を複数接続し、前記第５の半導体領域と
前記第６の半導体領域の間の耐圧より耐圧が低い前記第
４の半導体領域と前記第３の半導体領域の部分を、前記
第２の主表面の面内で前記第４の半導体領域から前記第
３の半導体領域に向かう方向及びそれに垂直な方向で交
互に設けたことを特徴とする複合半導体装置。10. The semiconductor device according to claim 1 , wherein a plurality of the composite semiconductor devices are connected to each other, and the fourth semiconductor device has a withstand voltage lower than a withstand voltage between the fifth semiconductor region and the sixth semiconductor region. And the third semiconductor region are provided alternately in a direction from the fourth semiconductor region toward the third semiconductor region and in a direction perpendicular thereto in the plane of the second main surface. A composite semiconductor device characterized by the above-mentioned.
の半導体領域上に第２の主表面に露出するように設けた
第２導電型の第２の半導体領域と、前記第２の主表面に
露出するように前記第２の半導体領域内に設けた第１導
電型の第３の半導体領域及び第１導電型の第４の半導体
領域と、前記第３の半導体領域内に前記第２の主表面に
露出するように設けた第２導電型の第５の半導体領域及
び第２導電型の第６の半導体領域と、前記第４の半導体
領域内に前記第２の主表面に露出するように設けた第２
導電型の第７の半導体領域と、前記第２の主表面上で第
５の半導体領域、第６の半導体領域にまたがって形成さ
れた第１の絶縁ゲートと、前記第２の主表面上で第２の
半導体領域，第４の半導体領域，第７の半導体領域にま
たがって形成された第２の絶縁ゲートと、前記第１の主
表面上で前記第１の半導体領域に低 抵抗接触した第１の
電極と、前記第２の主表面上で第３の半導体領域と第６
の半導体領域を短絡した第２の電極と、第１の絶縁ゲー
トと第２の絶縁ゲートを短絡したゲート電極とを有し、
前記第５の半導体領域と、前記第７の半導体領域を低抵
抗接続し、前記第３の半導体領域と前記第４の半導体領
域の間の少なくとも一部分に、前記第３の半導体領域と
前記第４の半導体領域にともに接した第１導電型の第１
３の半導体領域を設けたことを特徴とする複合半導体装
置。11. A first conductive type first having a first main surface.
Provided so as to be exposed on the second main surface on the semiconductor region of FIG.
A second semiconductor region of a second conductivity type and the second main surface;
A first conductor provided in the second semiconductor region so as to be exposed;
Third semiconductor region of first conductivity type and fourth semiconductor of first conductivity type
Region and the second main surface in the third semiconductor region.
A fifth semiconductor region of the second conductivity type provided so as to be exposed;
And a sixth semiconductor region of the second conductivity type and the fourth semiconductor
A second region provided in the region so as to be exposed to the second main surface;
A seventh semiconductor region of conductivity type and a second semiconductor region on the second main surface;
5 and a sixth semiconductor region.
A first insulated gate, and a second insulated gate on the second main surface.
The semiconductor region, the fourth semiconductor region, and the seventh semiconductor region.
A second insulated gate thus formed;
A first low- resistance contact with the first semiconductor region on the surface;
An electrode; a third semiconductor region on the second main surface;
A second electrode having a short-circuited semiconductor region, and a first insulating gate.
And a gate electrode short-circuiting the second insulated gate,
The fifth semiconductor region and the seventh semiconductor region are connected at a low resistance.
A first conductive type first conductive type that is in anti-connection and at least partially in contact between the third semiconductor region and the fourth semiconductor region and is in contact with both the third semiconductor region and the fourth semiconductor region;
3. A composite semiconductor device comprising three semiconductor regions.
体領域のシートキャリア濃度が１×１０13cm-2以下であ
ることを特徴とする複合半導体装置。12. The composite semiconductor device according to claim 11 , wherein the thirteenth semiconductor region has a sheet carrier concentration of 1 × 10 13 cm −2 or less.
て、前記第５の半導体領域と前記第１の絶縁ゲートの間
の絶縁耐圧が、前記第３の半導体領域と前記第４の半導
体領域の耐圧より高いことを特徴とする複合半導体装
置。13. The semiconductor device according to claim 1 , wherein a withstand voltage between the fifth semiconductor region and the first insulated gate is equal to that of the third semiconductor region. A composite semiconductor device having a higher breakdown voltage than the fourth semiconductor region.
領域と前記第４の半導体領域の耐圧が、前記絶縁耐圧の
１／２以下であることを特徴とする複合半導体装置。14. The composite semiconductor device according to claim 13 , wherein a withstand voltage of said third semiconductor region and said fourth semiconductor region is not more than half of said withstand voltage.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491095A JP3196575B2 (en) | 1995-06-01 | 1995-06-01 | Composite semiconductor device and power conversion device using the same |
| US08/612,457 US5767555A (en) | 1995-03-09 | 1996-03-07 | Compound semiconductor device controlled by MIS gate, driving method therefor and electric power conversion device using the compound semiconductor device and the driving method |
| EP96103559A EP0731508A3 (en) | 1995-03-09 | 1996-03-07 | MOS controlled thyristor and driving method thereof |
| CN96103944A CN1050226C (en) | 1995-03-09 | 1996-03-08 | MIS gate composite semiconductor device and its driving method and power change-over device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491095A JP3196575B2 (en) | 1995-06-01 | 1995-06-01 | Composite semiconductor device and power conversion device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330570A JPH08330570A (en) | 1996-12-13 |
| JP3196575B2 true JP3196575B2 (en) | 2001-08-06 |
Family
ID=15139393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13491095A Expired - Fee Related JP3196575B2 (en) | 1995-03-09 | 1995-06-01 | Composite semiconductor device and power conversion device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3196575B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4767265B2 (en) * | 2008-01-15 | 2011-09-07 | 三菱電機株式会社 | High voltage semiconductor device |
| JP6275282B2 (en) * | 2015-01-13 | 2018-02-07 | 三菱電機株式会社 | Semiconductor device, manufacturing method thereof, and semiconductor module |
-
1995
- 1995-06-01 JP JP13491095A patent/JP3196575B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08330570A (en) | 1996-12-13 |
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