JPH10294461A - Insulation gate type semiconductor element - Google Patents

Insulation gate type semiconductor element

Info

Publication number
JPH10294461A
JPH10294461A JP11870997A JP11870997A JPH10294461A JP H10294461 A JPH10294461 A JP H10294461A JP 11870997 A JP11870997 A JP 11870997A JP 11870997 A JP11870997 A JP 11870997A JP H10294461 A JPH10294461 A JP H10294461A
Authority
JP
Japan
Prior art keywords
base layer
region
type base
type
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11870997A
Other languages
Japanese (ja)
Inventor
Masayasu Ishiko
Toshio Murata
Tsutomu Uesugi
勉 上杉
年生 村田
雅康 石子
Original Assignee
Toyota Central Res & Dev Lab Inc
株式会社豊田中央研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Central Res & Dev Lab Inc, 株式会社豊田中央研究所 filed Critical Toyota Central Res & Dev Lab Inc
Priority to JP11870997A priority Critical patent/JPH10294461A/en
Publication of JPH10294461A publication Critical patent/JPH10294461A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

[PROBLEMS] To reduce on-voltage in an insulated gate semiconductor device. An IGBT utilizing a conductivity modulation effect has the following configuration. In the n -type base layer 12 and the p-type base layer 13, in a region other than the channel formation region,
The flow path of the holes of the minority carriers injected from the p + -type collector layer 10 is narrowed, and the high resistance n -type base layer 12 is formed.
A buried oxide film 19 of an electrically insulating region for accumulating minority carriers in a region near the n + -type emitter layer 14 was formed. Thereby, holes injected from collector layer 10 are accumulated in n -type base layer 12. As a result,
As a result of the improvement of the minority carrier concentration in the base layer near the emitter layer 14, the conductivity modulation is increased,
The ON voltage decreases.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device having a reduced on-state voltage.

[0002]

2. Description of the Related Art Conventionally, bipolar MOS FETs such as a MOS thyristor, a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), and a conductivity modulation FET (COM FET) have been known as conductivity-modulated transistor elements. ing. These elements are characterized in that they can control a large current at a high withstand voltage. In such power semiconductor devices, reduction of power loss is a very important issue. Since a thyristor such as a GTO is used after being latched up, the ON voltage can be reduced, but the maximum breaking current density is small. On the other hand, since the IGBT is used without latch-up, the maximum breaking current density can be increased compared to a thyristor such as a GTO, but the ON voltage is high and the power loss is large. Then, the trench gate type IGBT (T-IGB
In T), a structure for reducing the ON voltage has been proposed (for example, Japanese Patent Application Laid-Open No. 6-90002). But,
The ON voltage of this element is still higher than the ON voltage of a thyristor such as a GTO, and the higher the breakdown voltage element, the greater the tendency.

[0003]

In the IGBT, it is necessary to improve the degree of conductivity modulation in order to reduce the ON voltage. That is, in order to increase the conductivity modulation, it is necessary to increase the accumulation of minority carriers in the high resistance base region. However, in the conventional IGBT, although the minority carrier has a high concentration near the injection region, the concentration decreases as the minority carrier approaches the emitter region. For this reason, conductivity modulation is not sufficiently performed in the vicinity of the emitter in the high-resistance base region, and the resistance in the high-resistance base region is insufficiently reduced, resulting in a problem that the on-voltage increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an insulated gate type semiconductor device having a high maximum breaking current density and a high withstand voltage to reduce the on-voltage. It is to make it.

[0005]

According to the present invention, there is provided an insulated gate semiconductor device utilizing a conductivity modulation effect.
In a region other than the channel forming region of the base region in the device, the flow path of minority carriers injected from the collector was narrowed, and an electrical insulating region for accumulating minority carriers in a region near the emitter in the high-resistance base region was formed. It is characterized by the following. In the above configuration, a buried electrode may be provided in the electrically insulating region. As described above, the insulated gate semiconductor device utilizing the conductivity modulation effect having these configurations includes a MOS thyristor, a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), and a conductivity modulation FET (COM F).
ET) or the like can be used. In particular, it is effective for semiconductor elements, IGBTs, and COM FETs used without latch-up.

[0006]

Since the electrically insulating region is formed in the base region, minority carriers injected from the collector are accumulated in the high-resistance base region. As a result, in the high resistance base region near the emitter, the minority carrier concentration is improved, so that the conductivity modulation is increased and the on-voltage is reduced. Further, by providing a buried electrode inside the electrically insulating region and applying a voltage having the same sign as the gate electrode, a potential barrier is formed for minority carriers injected around the electrically insulating region, Furthermore, the minority carrier concentration in the vicinity can be improved.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. The present invention is not limited to the following examples. First Embodiment FIG. 1 shows a T-IGB according to a specific embodiment of the present invention.
It is sectional drawing which showed the structure of T. p + type collector layer 10
An n + -type layer 11 is formed thereon, and an n -type base layer 12 for forming a high-resistance base region is formed on the n + -type layer 11. A p-type base layer 13 is formed on n -type base layer 12, and n + -type
An emitter layer 14 is formed. A collector electrode 15 is formed on the lower surface of the p + -type collector layer 10, and an emitter electrode 1 is formed on the p-type base layer 13 and the n + -type emitter layer 14.
6 are formed. A base region is formed by p-type base layer 13 and n -type base layer 12. Further, a gate electrode 17 and a gate oxide film 18 formed therearound are formed in the base region in the vertical direction. Also, p
A buried oxide film 19 forming an electrically insulating region is formed at the boundary between the base layer 13 and the n base layer 12. This buried oxide film 19 can be realized by, for example, an SOI structure using a solid phase epitaxial growth technique.

This device is designed to withstand a voltage of 600 V, and the thickness concentration of each layer is as follows. thickness of the n - -type base layer 12 is 50 [mu] m, the concentration is 1.3 × 10 14 / cm 3, p -type base layer 1
3, and the impurity surface concentration of the n + -type emitter layer 14 is 5 × 10 17 / cm 3 and 5 × 10 19 / cm 3 , respectively, and the thickness is 2.
5 μm and 0.5 μm. The length and width of the gate electrode 17 in the depth direction are 3 μm and 1 μm, respectively. The thickness of the gate oxide film 18 is 0.1 μm, and the thickness of the buried oxide film 19 is 0.1 μm.
0.3 μm.

Next, the operation of the above-structured device will be described. A voltage is applied between the gate electrode 17 and the emitter electrode 16 while a voltage higher than that of the emitter electrode 16 is applied to the collector electrode 15. When the gate voltage exceeds the threshold voltage and is sufficiently applied, an n-channel is formed in a region of the p-type base layer 13 along the gate oxide film 18, and n +
Electrons are injected from n-type emitter layer 14 into n -type base layer 12. As a result, holes of minority carriers are injected from the p + -type collector layer 10 into the n -type base layer 12, and conductivity modulation occurs. The injected holes diffuse into the n -type base layer 12 and flow to the p-type base layer 13.

[0010] A oxide film 19 buried in the diffusion path of the hole is formed, the buried oxide film 19 becomes an obstacle, n - hole flow path from the form the base layer 12 to the p-type base layer 13 is narrowed. As a result, the diffusion resistance of holes in the n -type base layer 12 near the p-type base layer 13 greatly increases, so that the holes are sufficiently accumulated in the n -type base layer 12. FIG. 6 shows the distribution of the hole concentration in the depth direction when the gate voltage is 15 V in the ON state. As is clear from FIG. 6, when the buried oxide film 19 is provided, the n -type base layer 12 near the p-type base layer 13 is compared with the conventional structure without the buried oxide film 19.
It can be seen that in FIG. As a result, conductivity modulation is sufficiently performed, and the on-voltage of the element is lower than that of the conventional structure. For example, on-state voltage at a collector current density of 200 A / cm 2 is about the conventional structure 1.4
On the other hand, in this embodiment, the on-state voltage was reduced to about 1.2 V, which was about 15%.

In the device having the above structure, the length of the buried oxide film 19 for obtaining a sufficient on-voltage lowering effect is determined by the distance La (the width of the flow path of the hole) between its end and the gate oxide film 18. Is preferably formed such that La / Lp <0.25. Here, Lp is 1 / of the cell size.

Second Embodiment FIG. 2 shows a sectional structure of an element according to a second embodiment of the present invention. The difference from the device of the first embodiment is that the buried oxide film 1
90 is separated and three or more holes are formed in the passage. Also in this case, the total flow width W of the holes (= W1 + W2 + W3 + W4 + W5) is W / 2L.
It is desirable to satisfy p <0.25. Even with such a configuration, as shown in FIG. 6, the accumulation density of holes in the vicinity of the p-type base layer 13 of the n -type base layer 12 was improved, and the on-voltage of the element was reduced.

Third Embodiment FIG. 3 shows a sectional structure of a device according to a third embodiment of the present invention. The difference from the first and second embodiments is that the buried oxide film 1
Reference numeral 91 is provided in the n -type base layer 12 instead of the boundary between the p-type base layer 13 and the n -type base layer 12. Also in this structure, a decrease in the ON voltage was observed as in the first and second embodiments. The buried oxide film 1 in FIG.
91 may be provided in the p-type base layer 13. Also in this case, the hole concentration in n -type base layer 12 can be improved.

Fourth Embodiment FIG. 4 shows a sectional structure of a device according to a fourth embodiment of the present invention. This embodiment is an example in which the present invention is applied to a planar IGBT. Also in this example, the same effect as in the first embodiment can be obtained by forming the buried oxide film 192 at the interface between the p-type base layer 13 and the n -type base layer 12. In this embodiment, layers and portions having the same functions as those in the first embodiment are denoted by the same reference numerals. That is, the emitter electrode 16, n
A MOS FET for turning on and off the device is constituted by the + emitter layer 14, the p-type base layer 13, the n --type base layer 12, and the gate electrode 17, and the p + -type collector layer 10, the n --type base layer 12, a p-type base layer 13, and an emitter electrode 16 constitute a transistor for flowing a large current. At this time, the transistor constituted by the n + -type emitter layer 14, the p-type base layer 13, and the n --type base layer 12 is not turned on.

Fifth Embodiment FIG. 5 shows a sectional structure of a device according to a fifth embodiment of the present invention. In this embodiment, the buried electrode 20 is formed in the buried oxide film 193. By setting the buried electrode 20 to the same potential as the gate electrode 17, a potential barrier for holes is formed around the buried oxide film 193. As a result, the width of the flow path flowing to the p-type base layer 13 becomes narrower than when no voltage is applied to the buried electrode 20, and the hole concentration of the portion of the n -type base layer 12 that is joined to the p-type base layer 13 is reduced. Is further improved. Therefore, the conductivity modulation is performed more sufficiently, and the on-voltage of the element is further reduced.

In the above example, an n-type channel element has been described, but a p-type channel element has a similar effect. Although the case of the IGBT has been described in the above example, the present invention is not limited thereto, and the present invention is applicable to an insulated gate semiconductor device using conductivity modulation by injection of minority carriers, and has the same effect.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first specific example of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment.

FIG. 5 is a sectional view of a semiconductor device according to a fifth embodiment.

FIG. 6 is a measurement diagram showing a distribution of a hole concentration in a depth direction.

[Explanation of symbols]

10 ... p + form collector layer 11 ... n + -type layer 12 ... n - -type base layer 13 ... p-type base layer 14 ... n + -type emitter layer 15 ... a collector electrode 16 ... emitter electrode 17 ... gate electrode 18 ... gate oxide film 19, 190, 191, 192, 193 embedded oxide film 20 embedded electrode

Claims (1)

    [Claims]
  1. In an insulated gate semiconductor device utilizing a conductivity modulation effect, a flow path of a minority carrier injected from a collector is narrowed in a region other than a channel forming region of a base region in the device, and a high resistance is obtained. An insulated gate semiconductor device, wherein an electrically insulating region for accumulating the minority carriers is formed in a region near the emitter in the base region.
JP11870997A 1997-04-21 1997-04-21 Insulation gate type semiconductor element Pending JPH10294461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11870997A JPH10294461A (en) 1997-04-21 1997-04-21 Insulation gate type semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11870997A JPH10294461A (en) 1997-04-21 1997-04-21 Insulation gate type semiconductor element

Publications (1)

Publication Number Publication Date
JPH10294461A true JPH10294461A (en) 1998-11-04

Family

ID=14743184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11870997A Pending JPH10294461A (en) 1997-04-21 1997-04-21 Insulation gate type semiconductor element

Country Status (1)

Country Link
JP (1) JPH10294461A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349284A (en) * 1999-06-04 2000-12-15 Toyota Central Res & Dev Lab Inc Insulated gate semiconductor element
WO2005062385A1 (en) * 2003-12-24 2005-07-07 Toyota Jidosha Kabushiki Kaisha Trench gate field effect devices
JP2006019555A (en) * 2004-07-02 2006-01-19 Toyota Central Res & Dev Lab Inc Semiconductor device
WO2006093309A1 (en) * 2005-03-03 2006-09-08 Fuji Electric Holdings Co., Ltd. Semiconductor device and the method of manufacturing the same
JP2007042826A (en) * 2005-08-03 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
KR100834478B1 (en) 2006-05-19 2008-06-05 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
WO2009081667A1 (en) * 2007-12-21 2009-07-02 Toyota Jidosha Kabushiki Kaisha Semiconductor device
CN102054859A (en) * 2009-10-29 2011-05-11 英飞凌科技奥地利有限公司 Bipolar semiconductor device and manufacturing method
JP2011199101A (en) * 2010-03-23 2011-10-06 Toyota Central R&D Labs Inc Insulated gate bipolar transistor
JP2012124518A (en) * 2012-02-15 2012-06-28 Mitsubishi Electric Corp Power semiconductor device
US8362519B2 (en) 2009-06-11 2013-01-29 Toyota Jidosha Kabushiki Kaisha Semiconductor device
CN102969350A (en) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 Trench gate IGBT (Insulated Gate Bipolar Transistor) chip
US8614483B2 (en) 2010-12-08 2013-12-24 Denso Corporation Insulated gate semiconductor device
CN105355655A (en) * 2015-11-16 2016-02-24 电子科技大学 Trench insulated gate bipolar transistor
CN107507861A (en) * 2017-06-19 2017-12-22 西安电子科技大学 Enhanced SiC PNM IGBT devices and preparation method thereof are injected in Novel Schottky contact

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4696327B2 (en) * 1999-06-04 2011-06-08 株式会社豊田中央研究所 Insulated gate type semiconductor device
JP2000349284A (en) * 1999-06-04 2000-12-15 Toyota Central Res & Dev Lab Inc Insulated gate semiconductor element
WO2005062385A1 (en) * 2003-12-24 2005-07-07 Toyota Jidosha Kabushiki Kaisha Trench gate field effect devices
US7737491B2 (en) 2003-12-24 2010-06-15 Toyota Jidosha Kabushiki Kaisha Trench gate field effect devices
KR100802527B1 (en) * 2003-12-24 2008-02-13 도요다 지도샤 가부시끼가이샤 Trench gate field effect devices
JP2006019555A (en) * 2004-07-02 2006-01-19 Toyota Central Res & Dev Lab Inc Semiconductor device
US8053859B2 (en) 2005-03-03 2011-11-08 Fuji Electric Co., Ltd. Semiconductor device and the method of manufacturing the same
JP2008532257A (en) * 2005-03-03 2008-08-14 富士電機デバイステクノロジー株式会社 Semiconductor device and manufacturing method thereof
WO2006093309A1 (en) * 2005-03-03 2006-09-08 Fuji Electric Holdings Co., Ltd. Semiconductor device and the method of manufacturing the same
JP2007042826A (en) * 2005-08-03 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
KR100834478B1 (en) 2006-05-19 2008-06-05 미쓰비시덴키 가부시키가이샤 Semiconductor device and manufacturing method thereof
WO2009081667A1 (en) * 2007-12-21 2009-07-02 Toyota Jidosha Kabushiki Kaisha Semiconductor device
EP2224489A1 (en) * 2007-12-21 2010-09-01 Toyota Jidosha Kabushiki Kaisha Semiconductor device
EP2224489A4 (en) * 2007-12-21 2011-01-05 Toyota Motor Co Ltd Semiconductor device
US8362519B2 (en) 2009-06-11 2013-01-29 Toyota Jidosha Kabushiki Kaisha Semiconductor device
CN102054859A (en) * 2009-10-29 2011-05-11 英飞凌科技奥地利有限公司 Bipolar semiconductor device and manufacturing method
JP2011199101A (en) * 2010-03-23 2011-10-06 Toyota Central R&D Labs Inc Insulated gate bipolar transistor
US8614483B2 (en) 2010-12-08 2013-12-24 Denso Corporation Insulated gate semiconductor device
JP2012124518A (en) * 2012-02-15 2012-06-28 Mitsubishi Electric Corp Power semiconductor device
CN102969350A (en) * 2012-12-07 2013-03-13 株洲南车时代电气股份有限公司 Trench gate IGBT (Insulated Gate Bipolar Transistor) chip
CN105355655A (en) * 2015-11-16 2016-02-24 电子科技大学 Trench insulated gate bipolar transistor
CN107507861A (en) * 2017-06-19 2017-12-22 西安电子科技大学 Enhanced SiC PNM IGBT devices and preparation method thereof are injected in Novel Schottky contact

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