JPH01256172A - Manufacture of conductivity modulating mosfet - Google Patents

Abstract

PURPOSE:To improve positional accuracy, by forming a semiconductor base layer of a first conductivity type on the surface of a semiconductor layer of a second conductivity type, introducing respective dopants for producing a highly doped semiconductor layer of the first conductivity type and a source layer of the second conductivity type into the base layer, and producing these layers simultaneously. CONSTITUTION:A window is opened in a polysilicon layer 8a which is to be a gate. A dopant 20 is introduced by using this polysilicon layer as a mask so that a P-type base layer 4 is formed. Then, a dopant 21 for producing a P<++> layer 5 is introduced. The window in the polysilicon layer 8a is enlarged and a dopant 23 for producing an N<+> source layer 6 is introduced by using the layer 8a as a mask again, The P<++> layer 5 and the N<+> source layer 6 are produced simultaneously by heat treatment. Accordingly, the P<++> layer 5 is formed in a self aligned manner to the edge of a polysilicon gate 8 without deviation as caused by erroneous registering of mask when it is used. Thus, positional accuracy in formation of a device can be improved remarkably.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a vertical conductivity modulation type MOSFET [hereinafter referred to as IGBT (Insulated Gats)].
BipolarTrans istor).

[Conventional technology]

FIG. 3 is a cross-sectional view showing the basic element structure of an IGBT, and an N-channel element will be explained here. Third
In the figure, the main components of the IGBT device are indicated by the symbols: P'' substrate 1. High resistance N-layer 2. P'' well 3 P base layer 4. P'' high impurity concentration [5° N'' source layer 6 gate oxidation Membrane 7. Polysilicon gate8. PSG insulation layer9. Source electrode 10. Gate electrode 11. Consisting of a drain electrode 12, the symbol S represents the source, G represents the gate + D represents the drain terminal, respectively.

As shown in FIG. 3, the IGBT basically has a PNPN four-layer structure, and its operation will be explained next with reference to FIG. 4 showing an equivalent circuit. This circuit has a PNP transistor 13 and an NPN transistor 14 connected as shown in FIG. 4, and has a resistor (RP) 15. Transistor 14 is an N-layer 2. shown in FIG. P layer 4. This corresponds to an NPN parasitic transistor consisting of an N9 layer 6. Normally, the main current can be controlled by the gate 16, but the resistor (RP
) 15 is large, a potential difference greater than a certain current occurs between the base and emitter of the transistor 140, a current flows between the collector and emitter, and the transistor 14 is activated. As a result, even if the gate 16 is turned off, the main current continues to flow, eventually destroying the device itself.

This phenomenon is called a latch amplifier, and in order to operate an IGBT normally, an element must be manufactured to prevent this latch-up phenomenon from occurring.

Therefore, it is known that latch-up can be prevented by forming a P'' layer 5 as shown in FIG. 3.The reason for providing the P'' layer 5 is as shown in FIG.
This is to reduce the potential difference generated across the resistor R715 and lower the voltage between the emitter and base of the parasitic transistor 14, so that the parasitic transistor 14 is not activated.

The formation of the P'' layer 5 will be further explained in relation to latch amplifier prevention, with FIG. 5 showing a partially enlarged view of FIG. 3.

FIG. 5 is a partially enlarged view showing a part of the P'' layer 5 and its vicinity, and parts common to those in FIG. 3 are denoted by the same reference numerals.

In FIG. 5, 17 and its vicinity are channel forming portions, and the direction in which electrons flow is indicated by solid arrows 18. The flow of holes is indicated by dotted arrows 19. The correct bill is dotted arrow 1
When the current flows along the route 9, the above-mentioned potential difference is generated due to the resistance R,. Therefore, in order to keep this potential difference low, it is preferable to form the highly doped P'' layer 5 as close to the channel portion 17 as possible.
In FIG. 5, ■, ■, ■, and ■ are shown for the purpose of comparing the terminal positions directly under the polysilicon gate 8 of P''[5, respectively, and the advantages and disadvantages of these positional relationships will be described below.

For example, if the P''99 layer 5 is dispersed up to ■ in Figure 5, the channel itself will be destroyed, making MOS operation impossible.If P''115 is diffused only up to the position of is PJ! Since it passes through the high resistance region of I4 for a long time, the voltage drop becomes large and latch-up is likely to occur.Also, since the P well 3 is normally formed, the diffusion of the P" layer 5 to the position of In this case, the effect is weak.The most effective method is to scatter the P''00 layer 5 to the position (2), which is ideal, but it is difficult to control to set it at this position. It is formed to prevent launch-up because it is unstable in the manufacturing process as it is prone to misalignment due to some reason and can easily spread to the position shown in ■. It is appropriate to form the P"JI5 under the polysilicon gate 8 by diffusion to the position (■). To achieve this, normally when manufacturing an IGBT, this P"lit5 is formed. Currently, a mask such as a resist is used in the process.

[Problem to be solved by the invention]

As mentioned above, the important point in manufacturing for preventing launch amplifier is to form the high 1 degree P'' layer 5 as close to the position shown in FIG. 5 as possible.

Therefore, the mask alignment for its positioning must be performed with extremely high precision. Normally, the N source layer 6 is formed by ion implantation of impurities using the polysilicon gate 8 as a mask, so it becomes a self-alignment line with respect to the gate, and the accuracy is low. Very good. However, when forming the P'' layer 5 using a different mask, it is of course necessary to ensure the misalignment, so even if the position of
The mask must be designed in a position that approaches the direction of Since the P'' layer 5 is formed by diffusion using a conventional mask, there are many disadvantages.

The present invention has been made to solve the above-mentioned problems, and its purpose is to remove high concentration P''15 using a conventional mask.
The object of the present invention is to provide a method for efficiently manufacturing an IGBT in which rough lumps are less likely to occur by diffusing the P'' layer 5 once with high precision using self-line without using a mask. .

[Means to solve the problem]

In the conductivity modulated MOSFET according to the present invention, a first conductivity type high impurity concentration semiconductor layer is formed according to the following procedure.

I) A window is opened in the polycrystalline semiconductor layer of a stacked body in which a second conductivity type semiconductor layer, a gate oxide film, and a polycrystalline semiconductor layer are formed in this order on a first conductivity type semiconductor substrate, and impurities are introduced through this window. After that, a first conductive type semiconductor base layer is formed on the surface of the second conductive type semiconductor layer by heat treatment.

ii) Introducing an impurity to form a first conductivity type high impurity concentration semiconductor layer into the base layer from the polycrystalline semiconductor layer window.

iii) Isotropically etching the polycrystalline semiconductor layer having the window to slightly widen the window and form a polycrystalline semiconductor gate.

iv) Using the polycrystalline semiconductor gate having the expanded window portion as a mask, impurities are introduced into the surface of the base layer to form a second conductivity type source layer.

(v) A first conductivity type high impurity concentration semiconductor layer and a second conductivity type source layer are simultaneously diffused and formed by heat treatment to form an insulating layer on the polycrystalline semiconductor gate.

[Effect]

As mentioned above, in order to suppress the latch-up phenomenon in IGBTs, a high concentration of P''15 is provided in the P base layer, but in order to fully demonstrate its effect, it is necessary to increase the precision of the formation position of the P'' layer. A conventional resist mask is used in the present invention.

Instead, a window is opened in the polysilicon layer that will become the gate, and impurities are introduced using this as a mask to first form a P base layer, then an impurity is introduced to form a P'' layer, and then a window is opened in the polysilicon layer. After widening the width of the polysilicon layer and introducing impurities to form the N1 source layer using this polysilicon layer as a mask, a P'' layer and an N° source layer are simultaneously formed by heat treatment.

Therefore, the formation of the P'' layer by the method of the present invention forms a self-alignment line with respect to the edge of the polysilicon gate, and there is no shift due to mask alignment as in the conventional method when using a mask such as a resist, so the formation position is accurate. The value will be high.

〔Example〕

The present invention will be explained below based on examples.

FIGS. 1 and 2 are process diagrams showing the process of the present invention in order, and the same reference numerals are used for parts common to those in FIG. In FIG. 1, the initial steps of the ICBTI fabrication process are omitted for convenience, and the process begins after forming a gate oxide film and a polysilicon layer thereon. First, in FIG. 1(a), a high resistance N- layer 2, a gate oxide film 7, and a polysilicon layer 8a which will become a gate are deposited on a P'' substrate 1 in the order of the numbers shown in FIG. 1(1)). A part of the polysilicon layer 8a is removed by a normal photoetching process in which a resist is applied to open a window.In this state, boron ions are implanted using the polysilicon layer 8B as a mask as shown in FIG. 1(C). , the ion implantation is indicated by an arrow, and the implanted boron is represented by 20. This ion implantation is IGB
This is to form a channel for the MO3 part in T, and the boron 20 ion implanted by the subsequent drive
is diffused to form a P haze layer 4 as shown in FIG. 1 tdl. If a thin oxide film is formed on the surface of the polysilicon layer 8a during this process, the entire surface is etched for a short time to leave the gate oxide film 7 and remove only the thin oxide film on the surface of the polysilicon layer 88. After this, using the polysilicon layer 8a as a mask, a step of implanting boron ions to form a high impurity concentration P'' layer is shown in FIG.
As in (C), the ion implantation is indicated by an arrow, and the implanted boron is indicated by 21. Next, the polysilicon layer 8a is etched. For this etching, it is preferable to use an etchant that has a good selectivity between the oxide film and the polysilicon and is capable of isotropic etching. Here, dry etching using SFa was performed. . The result is shown in Figure 2 (fl
As shown in the figure, the thickness of the polysilicon layer 8a is reduced and the sides are etched, so that the window width of the polysilicon layer 8a is slightly expanded. Then, as shown in FIG. Arsenic ions are implanted using a mask as shown by the arrow, and 23 represents the implanted arsenic. The implantation of arsenic 23 is to form the N source Ji6, which will be described later. Phosphorus or the like can also be used, but since the diffusion coefficient of phosphorus is almost the same as that of boron, ion implantation of phosphorus is performed after boron is diffused. Furthermore, in order to prevent latch-up, it is preferable to make the N source layer 6 shallow, and in the present invention, it is better to use arsenic, which has a short range during ion implantation.6 Next, the resist 22 is removed. A PSG insulating film 9 is formed, and boron 21 is ion-implanted by performing high-temperature heat treatment during the PSG glue flow process.
At this time, arsenic 23 is activated and diffused. The obtained diffusion layers become the highly impurity 1 degree P'' layer 5 and the N source layer 6 as shown in FIG.
In order to form the source layer 6, arsenic 23 is ion-implanted using the resist 22 as a mask. After ion-implanting arsenic into the entire surface of the polysilicon gate 8 from an open area, k
It is also possible to use a method of making contact with the P'' layer 5 by forming an I electrode and heat-treating it to create an alloy layer that penetrates the N'' layer.

Due to the difference in diffusion coefficient between the ion-implanted boron 21 and arsenic 23, the boron 21 diffuses deeper than the arsenic 23.
The layer 5 is diffused, which corresponds to the resistance 1 in FIG.
5 and thus the thick I of the rough chia knob welfare
You will be able to get GBT.

In addition, boron 21 diffuses more in the lateral direction than arsenic 23, so if the polysilicon layer 8a is kept in its original shape before etching to el (see FIG. 1), boron 21 and arsenic 23 are ion-implanted using this as a mask. , during diffusion, boron 21 diffuses laterally beyond the N9 source layer 6, crushing the channel forming region of the P base layer 4.In contrast, in the present invention, Like boron 21
After the ion implantation, the polysilicon layer 8a is subjected to isotropic etching, and the window portion is set back so as to increase the lateral distance, so that the N source 116 in FIG. It is possible to secure the channel formation region by forming the channel on the outside.The subsequent steps are shown in Fig. 2 (11).
As shown in FIG. 1, the source electrode 10. By forming gate electrodes and drain electrodes (not shown), a vertical conductivity modulation MOSFET having the same structure as that shown in FIG. 3 can be obtained. Note that the P well 3 shown in FIG. 3 is omitted from the process diagrams (al to +11) in FIGS. 1 and 2 for convenience of explanation.

Further, although the detailed dimensions of the IGBT and power MOSFET differ, their basic element structures are almost the same, and they can be differentiated depending on whether or not a jff M of a conductivity type opposite to that of the source is added to the drain side. Therefore, as a matter of course, the manufacturing method of the present invention can be applied to the power MOSFET.
It is also applicable to power M OS F' E
This has the effect of eliminating the destructive phenomenon caused by the operation of the parasitic transistor during switching in T and increasing the L negative 1IiJ tolerance.

〔Effect of the invention〕

When manufacturing IGBTs, a photomask was conventionally used to form a highly impurity 4-degree P'' layer to prevent latch-up, and the formation position accuracy was not sufficient. As mentioned above, it is possible to bring the P'' layer formed by self-line using a polysilicon layer close to the edge of the N source layer with high precision.
An IGBT with high latch-up resistance can be obtained. Furthermore, the conventionally used photomask is no longer required, and troublesome processes such as photomask alignment can be omitted, which has the great effect of not only improving precision but also simplifying the manufacturing process.

Furthermore, in order to increase the durability of conventional latch amplifiers, when the impurity diffusion in the P base layer that forms the channel is deepened, lateral diffusion also progresses, increasing the channel resistance and increasing the on-state voltage. In the present invention, after enlarging the window by isotropically etching the polysilicon layer, N
Since impurities are introduced to form the source layer, the channel length can be reduced and the on-state voltage can be lowered. Furthermore, by performing isotropic etching of the polysilicon layer, the curvature of a portion of the corner of the polysilicon gate becomes thicker, which also has the effect of improving step coverage of the PSG insulating film laminated thereon.

[Brief explanation of the drawing]

1 and 2 are manufacturing process diagrams of an IGBT according to the present invention, FIG. 3 is a structural sectional view of the IGBT, FIG. 4 is an equivalent circuit diagram, and FIG. 5 is a vicinity of the channel forming part of FIG. 3. FIG. 1: P'' substrate 2: High resistance N-layer, 3: P'' well 4: P
Base layer, 5: P'' high impurity concentration layer, 6: N'' source layer 7: Gate oxide film, 8: Polysilicon gate, 8a: Polysilicon layer, 9: PSG insulating film, lO: Source electrode,
11: Gate electrode (], 12 Nidraine electrode, 13: PN
P) transistor, 14: NPN) transistor, 15; resistor RP, 17: channel, 18: electron flow, 19: hole flow, 20° 21: boron, 22X resist, 23
:arsenic. Figure 2 Shizuku Yakuichi ^ -1' ℃ Scream? \1no
ζ,/Figure 3, Figure 4, Figure 5

Claims (1)

[Claims] (1) A first conductivity type semiconductor substrate, a high resistance second conductivity type semiconductor layer formed on this substrate, a first conductivity type semiconductor base layer diffused on the surface of this semiconductor layer, and this base a first conductivity type semiconductor layer diffused into the second conductivity type semiconductor layer immediately below the layer; a second conductivity type semiconductor source layer diffused into the base layer; and a second conductivity type semiconductor source layer diffused into the base layer. Gate oxidation is performed on the high impurity concentration semiconductor layer of the first conductivity type and the channel region formed on the surface of the second conductivity type semiconductor layer due to the difference in lateral impurity diffusion distance between the base layer and the source layer. a polycrystalline semiconductor gate formed through a film, a source electrode in ohmic contact with both the base layer and the source layer, a gate electrode insulated from the source electrode by an insulating layer and in contact with the gate, and the substrate. A method of manufacturing a conductivity modulated MOSFET comprising a drain electrode formed on the back surface of a conductivity-modulated MOSFET, the method comprising forming the first conductivity type high impurity concentration semiconductor layer by the following steps. A method for manufacturing a degree modulation type MOSFET. (i) a second conductive type semiconductor layer on the first conductive type semiconductor substrate;
A window is opened in the polycrystalline semiconductor layer of a stacked body in which a gate oxide film and a polycrystalline semiconductor layer are formed in this order, and impurities are introduced through the window, and then heat-treated to form a first conductive layer on the surface of the second conductive type semiconductor layer. form a type semiconductor base layer. (ii) introducing impurities to form a first conductivity type high impurity concentration semiconductor layer into the base layer from the polycrystalline semiconductor layer window portion; (iii) The polycrystalline semiconductor layer having the window portion is subjected to isotropic etching to slightly widen the width of the window portion and form a polycrystalline semiconductor gate. (iv) Using the polycrystalline semiconductor gate having the expanded window portion as a mask, impurities are introduced into the surface of the base layer to form a second conductivity type source layer. (v) A first conductivity type high impurity concentration semiconductor layer and a second conductivity type source layer are simultaneously diffused and formed by heat treatment to form an insulating layer on the polycrystalline semiconductor gate.