JPH0555594A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPH0555594A JPH0555594A JP3240316A JP24031691A JPH0555594A JP H0555594 A JPH0555594 A JP H0555594A JP 3240316 A JP3240316 A JP 3240316A JP 24031691 A JP24031691 A JP 24031691A JP H0555594 A JPH0555594 A JP H0555594A
- Authority
- JP
- Japan
- Prior art keywords
- region
- effect transistor
- vertical field
- source
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 24
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000005468 ion implantation Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は縦型電界効果トランジス
タに関し、特にサージ耐量を改善したトランジスタに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field effect transistor, and more particularly to a transistor having improved surge withstand capability.
【０００２】[0002]
【従来の技術】従来、縦型電界効果トランジスタは、図
３にＮチャネル型トランジスタを示すように、Ｎ型シリ
コン基板１の裏面をドレイン電極とし、シリコン基板１
の表面に成長させたエピタキシャル層２に基板と反対導
電型のＰ高ベース領域４及びウェル領域３を形成し、更
にベース領域４に基板と同じ導電型のＮ型ソース領域５
を形成している。ウェル領域３とベース領域４上にはポ
リシリコンのゲート電極７と、アルミニウムのソース電
極９が設けられる。又、ゲート電極７は、ゲート酸化膜
６と層間膜８によって、ベース領域４、ソース領域５、
及びソース電極９と絶縁されている。ソース電極９は、
バックゲート部１０でウェル領域３及びソース領域５と
電気的に接続している。2. Description of the Related Art Conventionally, in a vertical field effect transistor, as shown in an N-channel type transistor in FIG. 3, the back surface of an N-type silicon substrate 1 is used as a drain electrode, and
A P high base region 4 and a well region 3 of opposite conductivity type to the substrate are formed on the epitaxial layer 2 grown on the surface of the substrate, and an N type source region 5 of the same conductivity type as the substrate is further formed in the base region 4.
Is formed. A gate electrode 7 made of polysilicon and a source electrode 9 made of aluminum are provided on the well region 3 and the base region 4. In addition, the gate electrode 7 includes the base region 4, the source region 5, the gate oxide film 6 and the interlayer film 8.
And is insulated from the source electrode 9. The source electrode 9 is
The back gate portion 10 is electrically connected to the well region 3 and the source region 5.
【０００３】この縦型電界効果トランジスタでは、ウェ
ル領域３及びベース領域４とエピタキシャル層２はダイ
オードを形成し、ドレイン電極からソース電極にかけて
は、逆方向になるが、ゲート電極７，ソース電極９間に
電圧を印加することによりチャネル部１５の導電型が反
転し導通する。このような縦型電界効果トランジスタは
バイポーラトランジスタに比べ高速動作が可能であり、
又電圧駆動であることから駆動回路が設計しやすいとい
う利点があり、スイッチング素子として広く使用されて
いる。In this vertical field effect transistor, the well region 3 and the base region 4 and the epitaxial layer 2 form a diode, and the direction from the drain electrode to the source electrode is opposite, but between the gate electrode 7 and the source electrode 9. When a voltage is applied to the channel 15, the conductivity type of the channel portion 15 is inverted and the channel portion 15 becomes conductive. Such a vertical field effect transistor can operate at higher speed than a bipolar transistor,
Further, since it is driven by voltage, it has an advantage that a drive circuit can be easily designed, and is widely used as a switching element.
【０００４】[0004]
【発明が解決しようとする課題】しかし、この種のトラ
ンジスタにおいては、インダクタンス性の負荷を駆動す
るために用いた場合に素子が破壊することがある。これ
は、ターンオフ時に、負荷に発生したサージ電圧（逆起
電力）によって素子内部の寄生トランジスタがオンして
しまい、ソース・ドレイン間に過大な電流が流れるため
である。即ち、ソース領域５，ベース領域４，エピタキ
シャル層２がＮＰＮトランジスタを形成しており、この
寄生トランジスタがオンしてしまうのである。However, in this type of transistor, the element may be destroyed when it is used to drive an inductive load. This is because the parasitic transistor inside the element is turned on by the surge voltage (back electromotive force) generated in the load at the time of turn-off, and an excessive current flows between the source and the drain. That is, the source region 5, the base region 4, and the epitaxial layer 2 form an NPN transistor, and this parasitic transistor is turned on.
【０００５】このように、素子がどの程度の負荷電流、
負荷インダクタンスまで破壊を起こさないかは、Ｌ負荷
耐量と呼ばれており、このＬ負荷耐量を改善するため
に、従来では図４に示すように、ソース領域１４を浅く
形成した構造が提案されている。又、図５に示すように
ベース領域３に不純物濃度の高いＰ+ベース部１３を形
成した構造が提案されている。しかしながら、これらの
対策は、いずれもベース領域３の抵抗を下げる事によっ
て逆起電力がかかった時のベース・ソース間の電圧降下
を小さくし、寄生トランジスタをオンしにくくしようと
するものであるため、逆起電力が大きな場合には充分な
効果を得ることが難しいという問題がある。本発明の目
的は、サージ耐量を改善した縦型電界効果トランジスタ
を提供することにある。In this way, the load current of the element is
Whether or not the load inductance is destroyed is called L load withstand capability. In order to improve this L load withstand capability, a structure in which the source region 14 is formed shallow as shown in FIG. 4 has been conventionally proposed. There is. Further, as shown in FIG. 5, a structure in which a P + base portion 13 having a high impurity concentration is formed in the base region 3 has been proposed. However, all of these measures are intended to reduce the voltage drop between the base and the source when a counter electromotive force is applied by lowering the resistance of the base region 3 to make it difficult to turn on the parasitic transistor. However, when the back electromotive force is large, it is difficult to obtain a sufficient effect. An object of the present invention is to provide a vertical field effect transistor with improved surge withstand capability.
【０００６】[0006]
【課題を解決するための手段】本発明の縦型電界効果ト
ランジスタは、半導体基体に設けたベース領域中の、少
なくともソース領域の下側に高酸素濃度領域を設けてい
る。この高酸素濃度領域は、例えば酸化膜で構成する。In the vertical field effect transistor of the present invention, a high oxygen concentration region is provided at least below the source region in the base region provided in the semiconductor substrate. This high oxygen concentration region is composed of, for example, an oxide film.
【０００７】[0007]
【作用】本発明によれば、高酸素濃度領域によってソー
ス領域、ベース領域、半導体基体からなる寄生トランジ
スタにおけるターンオン電圧が増大され、サージ耐量を
改善する。According to the present invention, the high oxygen concentration region increases the turn-on voltage in the parasitic transistor composed of the source region, the base region and the semiconductor substrate, and improves the surge withstand capability.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の第１の実施例の縦型電界効果トラン
ジスタの断面図である。 600Ｖ耐圧品の場合、２×1018
／cm3 程度にアンチモンをドープしたＮ+ 型シリコン基
板１に25Ωcm（２×1014／cm3 ）程度にリンをドープさ
せた厚さ約65μｍのＮ型エピタキシャル層２をエピタキ
シャル成長させたものを基板として使用する。この基板
に対し、レジストマスク等を用いたイオン注入及び熱拡
散によりウェル領域３を形成する。又、表面に酸化膜を
約1200Å形成後、約6000ÅのボリシリコンをＬＰＣＶＤ
により堆積し、約11Ω／□にリン拡散をした後、フォト
レジスト法により選択エッチングしてゲート酸化膜６及
びゲート電極７を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a vertical field effect transistor according to the first embodiment of the present invention. For 600V withstand voltage, 2 × 10 18
/ Cm 3 of antimony-doped N + type silicon substrate 1 with about 25 μcm (2 × 10 14 / cm 3 ) of phosphorus doped with about 65 μm thick N type epitaxial layer 2 epitaxially grown on the substrate To use as. The well region 3 is formed on this substrate by ion implantation and thermal diffusion using a resist mask or the like. After forming an oxide film on the surface of about 1200Å, about 6000Å poly silicon is LPCVDed.
And then phosphorus is diffused to about 11 Ω / □, and then the gate oxide film 6 and the gate electrode 7 are formed by selective etching by a photoresist method.
【０００９】更に、ゲート電極７をマスクにイオン注入
及び熱拡散を行ってベース領域４を形成する。同様に、
ゲート電極７をマスクにして酸素をイオン注入し、かつ
熱処理を行って前記ベース領域４の底面に近い領域に酸
化膜１１を形成する。又、ソース領域５をレジストマス
クを用いたイオン注入および熱拡散により形成する。そ
の後、層間膜８をＣＶＤにより成長させ、フォトレジス
ト法により、コンタクトホールを形成する。更に、スパ
ッタ法により厚さ 3.5μｍのアルミニウムを形成し、こ
れを選択エッチングしてソース電極９とする。Further, ion implantation and thermal diffusion are performed using the gate electrode 7 as a mask to form the base region 4. Similarly,
Oxygen is ion-implanted using the gate electrode 7 as a mask, and heat treatment is performed to form an oxide film 11 in a region near the bottom surface of the base region 4. Further, the source region 5 is formed by ion implantation and thermal diffusion using a resist mask. After that, the interlayer film 8 is grown by CVD and a contact hole is formed by a photoresist method. Further, aluminum having a thickness of 3.5 μm is formed by the sputtering method, and this is selectively etched to form the source electrode 9.
【００１０】この構成によれば、ソース領域５の下側に
高い酸素濃度の領域である酸化膜１１が形成されている
ため、ソース領域５、ベース領域４、エピタキシャル層
２からなる寄生トランジスタが形成され難くなり、又形
成された場合でも寄生トランジスタのベース電流を遮断
してそのターンオン電圧を極めて高いものとする。この
ため、寄生トランジスタがオンされなくなり、ソース・
ドレイン間に過大な電流が流れなくなり、縦型電界効果
トランジスタのサージ耐量が向上されることになる。
尚、この例の場合、基板の表面からソース領域５の底面
までの距離は約 0.8μｍ、ベース領域４の底面までは
4.5μｍ、ウェル領域の底面までは７μｍであり、この
場合酸素のイオン注入は、エネルギー50KeVドーズ量は
１×1013〜１×1016の範囲で良い効果が得られる。According to this structure, since the oxide film 11 which is a high oxygen concentration region is formed below the source region 5, a parasitic transistor including the source region 5, the base region 4 and the epitaxial layer 2 is formed. If it is formed, the base current of the parasitic transistor is cut off to make the turn-on voltage extremely high. Therefore, the parasitic transistor is not turned on and the source
Excessive current does not flow between the drains, and the surge resistance of the vertical field effect transistor is improved.
In this example, the distance from the surface of the substrate to the bottom of the source region 5 is about 0.8 μm, and the distance to the bottom of the base region 4 is
The thickness is 4.5 μm and 7 μm to the bottom of the well region. In this case, oxygen ion implantation has a good effect when the energy dose is 50 KeV and the dose range is 1 × 10 13 to 1 × 10 16 .
【００１１】又、この実施例の場合、酸化膜１１を形成
する工程において、ベース領域４を形成する時と同様に
ゲート電極７をイオン注入のマスクとして利用している
ため、新たにフォトリソグラフィー工程を導入する必要
がない。又、寄生トランジスタとして最も寄与の大きい
ソース領域５の下部に酸化膜１１を形成し、チャネル部
には形成していないので、電界効果トランジスタの特性
を劣化させることはない。Further, in the case of this embodiment, the gate electrode 7 is used as a mask for ion implantation in the step of forming the oxide film 11 as in the case of forming the base region 4, so that a new photolithography step is performed. Need not be introduced. Further, since the oxide film 11 is formed below the source region 5 that makes the largest contribution as a parasitic transistor and is not formed in the channel portion, the characteristics of the field effect transistor are not deteriorated.
【００１２】図２は本発明の第２の実施例の縦型電界効
果トランジスタの断面図である。この実施例では、第１
実施例と同様にベース領域４を形成した後に、レジスト
マスクを用いて酸素をイオン注入し、ベース領域４内の
ソース領域５相当領域に高酸素濃度領域１２を形成して
いる。しかる後、イオン注入、熱拡散によりソース領域
５を形成している。この実施例においても、高酸素濃度
領域１２をソース領域５の下側に形成したことで、寄生
トランジスタのターンオン電圧を増大させてそのオン動
作を抑制する。これにより、縦型電界効果トランジスタ
のサージ耐量を改善することができる。又、この実施例
では、ソース・ドレイン間がダイオード動作する際の主
たる電流経路であるバックゲート部１０とＰウェル部３
の間は高酸素濃度領域を設けていないので、ダイオード
動作の特性に影響を与えないという利点がある。FIG. 2 is a sectional view of a vertical field effect transistor according to the second embodiment of the present invention. In this embodiment, the first
After forming the base region 4 as in the embodiment, oxygen is ion-implanted using the resist mask to form the high oxygen concentration region 12 in the region corresponding to the source region 5 in the base region 4. Then, the source region 5 is formed by ion implantation and thermal diffusion. Also in this embodiment, since the high oxygen concentration region 12 is formed below the source region 5, the turn-on voltage of the parasitic transistor is increased to suppress its on-operation. As a result, the surge withstand capability of the vertical field effect transistor can be improved. Further, in this embodiment, the back gate section 10 and the P well section 3 which are main current paths when the diode operates between the source and the drain.
Since a high oxygen concentration region is not provided between the two, there is an advantage that it does not affect the characteristics of diode operation.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、ベース領
域の中のソース領域の下側に酸化膜等の高酸素濃度領域
を形成しているので、ドレイン・ソース間に負荷からの
逆起電力がかかった時に高酸素濃度領域によって寄生ト
ランジスタのベース電流を遮断し、寄生トランジスタを
ターンオンし難くすることができ、縦型電界効果トラン
ジスタのサージ耐量を改善することができるという効果
がある。又、ソース領域の下側にのみ高酸素濃度領域を
形成することで、本来の電界効果トランジスタとしての
特性にほとんど影響を与えることはない。As described above, according to the present invention, since a high oxygen concentration region such as an oxide film is formed below the source region in the base region, a back electromotive force from the load is generated between the drain and the source. The high oxygen concentration region cuts off the base current of the parasitic transistor when power is applied, making it difficult to turn on the parasitic transistor and improving the surge withstand capability of the vertical field effect transistor. Further, by forming the high oxygen concentration region only under the source region, the characteristics of the original field effect transistor are hardly affected.
【図１】本発明の縦型電界効果トランジスタの第１実施
例の断面図である。FIG. 1 is a sectional view of a first embodiment of a vertical field effect transistor of the present invention.
【図２】本発明の第２実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】従来の縦型電界効果トランジスタの断面図であ
る。FIG. 3 is a cross-sectional view of a conventional vertical field effect transistor.
【図４】サージ耐量を改善した従来の縦型電界効果トラ
ンジスタの一例の断面図である。FIG. 4 is a cross-sectional view of an example of a conventional vertical field effect transistor with improved surge withstand capability.
【図５】サージ耐量を改善した従来の縦型電界効果トラ
ンジスタの他の例の断面図である。FIG. 5 is a sectional view of another example of a conventional vertical field effect transistor with improved surge withstand capability.
１ 基板（ドレイン領域） ２ エピタキシャル層 ３ ウェル領域 ４ ベース領域 ５ ソース領域 ７ ゲート電極 ９ ソース電極 １１ 酸化膜 １２ 高酸素濃度領域 1 substrate (drain region) 2 epitaxial layer 3 well region 4 base region 5 source region 7 gate electrode 9 source electrode 11 oxide film 12 high oxygen concentration region
Claims (2)
ース領域にソース領域を有する縦型電界効果トランジス
タにおいて、前記ベース領域中の少なくともソース領域
の下側に高酸素濃度領域を有することを特徴とする縦型
電界効果トランジスタ。1. A vertical field effect transistor having a base region in a semiconductor body and a source region in the base region, wherein a high oxygen concentration region is provided at least below the source region in the base region. Vertical field effect transistor.
の縦型電界効果トランジスタ。2. The high oxygen concentration region is an oxide film.
Vertical field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3240316A JP3063278B2 (en) | 1991-08-28 | 1991-08-28 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3240316A JP3063278B2 (en) | 1991-08-28 | 1991-08-28 | Vertical field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555594A true JPH0555594A (en) | 1993-03-05 |
| JP3063278B2 JP3063278B2 (en) | 2000-07-12 |
Family
ID=17057656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3240316A Expired - Lifetime JP3063278B2 (en) | 1991-08-28 | 1991-08-28 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3063278B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0750351A2 (en) * | 1995-06-19 | 1996-12-27 | Siemens Aktiengesellschaft | MOS semiconductor device with improved m-characteristics |
| EP0768717A2 (en) * | 1995-10-13 | 1997-04-16 | Asea Brown Boveri Ag | Power semiconductor device |
| JPH09153609A (en) * | 1995-11-29 | 1997-06-10 | Nec Yamagata Ltd | Vertical insulated gate field-effect transistor |
| JP2007042826A (en) * | 2005-08-03 | 2007-02-15 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| DE102008042170A1 (en) | 2007-10-05 | 2009-04-09 | Denso Corporation, Kariya | The silicon carbide semiconductor device |
| US20180114836A1 (en) * | 2016-10-21 | 2018-04-26 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US10655204B2 (en) | 2015-05-26 | 2020-05-19 | Posco | Hot press formed article having good anti-delamination, and preparation method for same |
-
1991
- 1991-08-28 JP JP3240316A patent/JP3063278B2/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0750351A2 (en) * | 1995-06-19 | 1996-12-27 | Siemens Aktiengesellschaft | MOS semiconductor device with improved m-characteristics |
| EP0750351A3 (en) * | 1995-06-19 | 1997-02-05 | Siemens Ag | |
| EP0768717A2 (en) * | 1995-10-13 | 1997-04-16 | Asea Brown Boveri Ag | Power semiconductor device |
| EP0768717A3 (en) * | 1995-10-13 | 1998-01-28 | Asea Brown Boveri Ag | Power semiconductor device |
| JPH09153609A (en) * | 1995-11-29 | 1997-06-10 | Nec Yamagata Ltd | Vertical insulated gate field-effect transistor |
| JP2007042826A (en) * | 2005-08-03 | 2007-02-15 | Fuji Electric Holdings Co Ltd | Semiconductor device and its manufacturing method |
| DE102008042170A1 (en) | 2007-10-05 | 2009-04-09 | Denso Corporation, Kariya | The silicon carbide semiconductor device |
| US7808003B2 (en) | 2007-10-05 | 2010-10-05 | Denso Corporation | Silicon carbide semiconductor device |
| US10655204B2 (en) | 2015-05-26 | 2020-05-19 | Posco | Hot press formed article having good anti-delamination, and preparation method for same |
| US20180114836A1 (en) * | 2016-10-21 | 2018-04-26 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US10319820B2 (en) | 2016-10-21 | 2019-06-11 | Fuji Electric Co., Ltd. | Semiconductor device having silicon carbide layer provided on silicon carbide substrate |
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| Publication number | Publication date |
|---|---|
| JP3063278B2 (en) | 2000-07-12 |
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