JPH03250660A - Manufacture of bicmos semiconductor device - Google Patents

Abstract

PURPOSE:To make a base extracting electrode of a bipolar transistor low in resistance so as to speed it up by simultaneously forming the gate electrode of low resistance of a CMOS transistor and the base extracting electrode of the bipolar transistor. CONSTITUTION:After an emitter-base forming region 10, a collector forming region 11, an NMOS forming region 12 and a PMOS forming region 13 of a bipolar transistor are formed, an oxide film 14 is formed on each element forming region. Then after the oxide films 14 of the region 10 and the region l1 are etched and a polysilicon film 15 is formed on an entire face, a tungsten silicide film 16 is formed on an entire face. Then after an oxide film 17 is formed and nitride films 19, 20 are formed, an emitter forming region 18 is selectively opened, and etching is done with the region 18, the nitride films 19, 20 of the regions 12, 13, the oxide film 17 and a W-Si film 16 left. An oxide film 21 is formed, and with the film 21, the oxide film 17 and the nitride films 19, 20 used as a mask, the W-Si film 22 is etched and then a base-emitter forming region 23 of the bipolar transistor is formed. Then after phosphorus is ion-implanted into the W-Si film 16 on a region 24, NMOS and PMOS gate forming regions 25, 26 are formed by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a BiCMOS type semiconductor device that can form a high-speed bipolar element and a CMOS element on the same chip.

(Conventional technology) In recent years, 840MO3 technology combines the high-speed performance of bipolar LSIs with the high integration and low power consumption performance of 0MO3LSIs, and has attracted attention as a very effective technology for improving the performance of LSIs. .

In particular, Bi produced using this Bi 0MO3 technology
Various techniques for forming bipolar transistors or CMOS transistors using self-alignment techniques have been proposed for the purpose of increasing the switching speed of 0MO3LS r .

Among these, one of the most typical manufacturing methods is r
ll, extended Abstracts of I
Some are disclosed in EDM 88 P760 to P763 J. 3 f7 (al to 3 fd+ are process cross-sectional views for explaining the manufacturing method disclosed in the above-mentioned document.

First, as shown in FIG. 3(al), N-buried Ji 202 and P-buried N2O3 are formed in a P-type (111) substrate 201, and N-type epitaxial N2O4 is grown.

Next, after forming a LOCO3 oxide film 205 for isolation using a well-known technique, and forming a P well 206 for forming an NMOS, 5isNa 207 is grown over the entire surface and a window is opened in the collector portion 208. , non-doped polysilicon 209 is grown over the entire surface.

Next, as shown in FIG. 3 (bl), the polysilicon 209
The surface of the bipolar transistor is thinly oxidized, 5isN4 is grown on the entire surface, and the collector region 210 of the bipolar transistor, the base/emitter formation region 211, the NMOS formation region 212, and the PM are formed using well-known photolithography and etching techniques.
After selectively leaving the Si3Ng in the OS formation region (not shown) and oxidizing the polysilicon 209 to form an element bone M oxide film 213, the hemisphere/emitter formation region 211 of the bipolar transistor and the PMOS formation region are formed. boron is implanted by ion implantation.

In addition, phosphorus is ion-implanted into the collector region 210 of the bipolar transistor and the NMOS formation region 212, and then 5iJa is removed, and polysilicon in the emitter formation region 214, polysilicon in the NMOS gate formation region 215, and PMOS are removed. Polysilicon (not shown) in the gate formation region is removed by etching.

Next, the S of the polysilicon hole in FIG.
tJ, II 216 is removed by etching as shown in FIG. 3(e).

At this time, perform an appropriate amount of side etching.

Similarly, the SiO□217 in the opening is shown in Figure 3 (Cl
After removing by etching and forming additive-free polysilicon as shown in FIG. 2, this is removed by wet etching.

By this operation, polysilicon 210a is embedded in the overhang portion of the P' or N° polysilicon 6. Then, by performing oxidation, an oxide film 218 for insulation between the emitter, 7, and base is formed. At this time, an oxide film is formed on both the gate portion 219 of the NMOS and the gate portion of the PMOS. Note that the collector portion 208 is filled with P-draped polysilicon.

The process from Figure 3 ('b) to Figure 3 (C) is somewhat complicated, but the details can be found in "Ultrahigh-speed bipolar device"
The detailed explanation is omitted here, as it is described in P.278-P281 of the Baikokukan edited by Minoru Nagata and supervised by Takuo Kanno.

Furthermore, the method for forming the emitter section of the bipolar transistor shown in FIG.
In the following explanation of FIG. 3(d), the explanation will be somewhat simplified.

Next, as shown in FIG. 3 (d+), the base 9 area 220, NMOS (7) VT:l 7
Channel doped region 221 for 0-Ji, PMOS
After forming channel doped regions 222 for VT control and again forming polysilicon on the entire surface, R
Anisotropic etching is performed using IE to form emitter flowering portions 300.

This process will be further explained using FIG. 3(e) and FIG. 3ffl. Figures 3(e) and 3(fl) are enlarged views of the emitter-base boundary of a bipolar transistor. Figure 3(e) shows the state in which polysilicon 223 has been grown on the entire surface. , and the state obtained by etching this by RIE is shown in FIG. 3 ffl.

Furthermore, using this polysilicon as a mask, the oxide film 224 on the emitter portion is removed by etching, and the emitter opening 300 (
Figure 3(d)) is drilled.

At this time, if the PMOS and NMOS element formation regions in dl are masked with resist, the gate oxide film 225 (FIG. 3(d)) will be etched during the oxide film etching in FIG. 3ff. , remains unchipped.

Furthermore, as shown in FIG.
(indicated by the marks) or As (indicated by the many "xj marks" in the figure) (note that the many points are polycrystalline silicon doped with poron (B)) and selectively remove it by etching. Accordingly, the emitter electrode 22 of the bipolar element
6. When the NMOS/PMOS gate electrode 227 is formed and subjected to heat treatment, N-type impurities are diffused into the base layer from the emitter electrode 226, and as is clear from the enlarged view of the emitter section in FIG. 4, the emitter layer 228 is formed. Furthermore, after going through the contact hole/electrode formation process, B
The iCMOS structure is completed.

Generally, in the manufacture of semiconductor integrated circuits, the minimum resolution dimension that can be stably obtained on the manufacturing line is called the integrated circuit design rule, and in order to improve the degree of integration of the integrated circuit,
Each dimension (example: emitter formation region 21 in Fig. 3 (bl)
4, the upper gate of the NMOS section, and FIG. 3 (openings of each contact hole in di) are designed using this design rule. This minimum resolution dimension is then primarily dependent on the performance of the mask aligner.

Now, suppose the conventional design rule is 1. When turned on,
The emitter width of a bipolar transistor is shown in Figure 3 (f).
If the width -1 of the polysilicon 223 in is 1-O,2n, then the emitter width -1,QIn&-2XW=0.61
nn, which makes it possible to realize an emitter width narrower than the design rule.However, in the PMO5/NMOS transistor, the gate part of the PMOS of FIG. 3 fd+ is shown enlarged in FIG. Since the remaining polysilicon 209 and the polysilicon 227 (FIG. 3(d)) in the gate area to be formed later are the same polysilicon, the P or As diffused into the polysilicon 227 in the gate area is It is also diffused into the remaining polysilicon 229, and as a result, the gate width is as shown in FIG.
2, that is, the minimum design rule 1. This results in θμ.

However, as shown in FIG. 3 fdl, the gate electrode 22
When 7 is formed, especially when the gate length -2 is less than 1.5μ, oxidation 11 is caused by a phenomenon called hot carriers.
! A problem arises in that a current is injected into the MOS transistor 230, causing characteristic fluctuations of the MOS transistor.

Here, in FIG. 4, 231 is the source (N"), 2
32 is a drain (No).

To elaborate on this point, the electric field ε in the channel of the MO3I-transistor is simply ε-vos/L-tt...
(1) However, ■, the source-drain voltage Lrr is shown as the effective gate length (see Figure 5), but in the operating state of the pentode, as shown in Figure 6, the electric field is concentrated in the nearby depletion layer region. Therefore, the maximum value ε□8 of the electric field is a much larger value than shown in equation (1).

When downsizing this MOS) transistor, if vns, that is, the power supply voltage (operating voltage) can be lowered in proportion to Lllff, as shown in equation (1), the electric field ε will not increase. At the request of
It is difficult to lower the power supply voltage, and as a result, the electric field ε increases in proportion to the reduction in gate length.

Here, the relationship between the effective gate length 1-aff and the gate length is clear from FIG. 5 (a perspective view showing the structure of a MOS transistor), where the source 231 of the N° diffusion layer,
If the depth of the drain 232 is constant, L = L*r
t +2 a (a is the width of the diffusion layer in the lateral direction)
There is an arithmetic relationship.

In the pre-triode operation, as explained above, the electric field ε increases in proportion to the reduction of the effective gate length, but the same is true for the pre-triode operation, and furthermore, in the pre-triode operation, the drain junction is In addition to increasing the electric field in the depletion layer near the oxide film boundary, the gate oxide film (fifth
If the gate oxide film 233 in the figure is made thinner, this increase in electric field will be further accelerated.

For the reasons explained above, the strong electric field has enough strength to generate sufficient hot carriers.

Carriers flowing in the channel, especially in the drain depletion layer, are accelerated by the strong electric field ε in the depletion layer, and hot carriers with sufficient energy fly out of the channel without being trapped in it. Generates substrate current or is injected into the oxide film. Then, some of the carriers injected into the oxide film are trapped or generated to generate surface levels, resulting in a shift in the threshold It pressure V□, a decrease in the mutual conductance i, This causes characteristic deterioration such as increased leakage in the subthreshold region.

Characteristic deterioration due to this hot carrier occurs when the gate length is 1.
It is said that this phenomenon is noticeable in NMOS transistors (less than 5μ).

(Problems to be Solved by the Invention) As described above in detail about the hot carrier phenomenon, it is extremely difficult to manufacture 1.5n or less MOS transistors with little characteristic deterioration using conventional manufacturing methods. .

As a countermeasure to this problem, there is a method of increasing the gate width by -2 in FIG. 4 or increasing the gate width in FIG. 5, but these methods have the problem of sacrificing the degree of integration.

Furthermore, in general, in order to achieve high speed in bipolar transistors, it is necessary to reduce parasitic capacitance and parasitic resistance.

Among these, effective ways to reduce parasitic capacitance include miniaturizing elements and using thick oxide films for isolation between elements.

Further, in order to reduce the parasitic resistance, it is particularly necessary to reduce the base resistance, and this reduction in the base resistance can be achieved by reducing the emitter width, shortening the distance between the emitter region and the base electrode, etc.

Since this conventional manufacturing method uses the self-line technology, it is possible to miniaturize the device.

In addition, it is possible to form a narrow and fine emitter, reduce the base resistance in the internal base region directly under the emitter, and make it possible to place a low-resistance base polysilicon electrode close to the emitter. It is also possible to reduce base resistance in the external base region.

Therefore, it was an effective method for manufacturing bipolar transistors capable of high-speed operation.

However, in bipolar transistors obtained using this manufacturing method, polysilicon is used as the base extraction electrode, but there is a limit to how low the resistance of polysilicon can be made, and the contribution of the base resistance to the operating speed is still small. This has become a major obstacle to increasing speed.

The present invention provides a method for manufacturing a BiCMOS type semiconductor device that solves the problem of the prior art, which is an obstacle to speeding up due to the use of polysilicon for the base lead-out electrode.

(Means for Solving the Problems) In order to solve the above-mentioned problems, this invention
In a method for manufacturing a type 3 semiconductor device, a polysilicon film and a silicide high-melting point metal are laminated on the entire surface of the base, and these are patterned to form a gate electrode of CMO3 with an LDD structure and a gate lead-out electrode of a bipolar transistor. process, and a process of patterning a silicide high melting point metal by Oha etching.

(Function) According to the present invention, since the above steps are introduced in the method for manufacturing a BiCMOS type semiconductor device, the gate of the CMO3 of the LDD structure is formed by buttering the polysilicon and silicide high melting point metal on the base. The electrodes and the base lead-out electrode of the bipolar transistor are formed of low-resistance polysilicon, and a bipolar transistor with a narrow emitter width and low base resistance that can operate at high speed and a MOS transistor with less characteristic deterioration are formed on the same substrate. will be done.

In addition, by over-etching the silicide high melting point metal, the emifutaborisilicon electrode and the silicide high melting point metal do not silate in the subsequent process.
The above problems can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a BiCMOS type semiconductor device of the present invention will be described based on the drawings.

FIG. 1 ta+ to FIG. 1 fsl are process cross-sectional views of one embodiment.

First, as shown in FIG. 1 (al), antimony was implanted into a P-type (100), resistivity 10-20Ω substrate l using a known ion implantation technique at a dose of 2×10×5a1−” and an acceleration voltage of 40 KeV. Drive-in is performed at 50°C for about 480 minutes to form an N-type buried layer 2 with a sheet resistance of 40Ω/hole and a diffusion depth of 2.5n.

Next, boron is implanted into the substrate 1 using a known ion implantation technique at a dose of 5X10"(J-") and an acceleration voltage of 1201 [eV].
A drive-in process is performed at 1000° C. for about 60 minutes to form a P-type buried layer 3 with a sheet resistance 4 of Ω/hole and a diffusion depth of In.

Next, by a known CVD method, a resistivity of 4Ω and a thickness of 1.
A 4μ thick N-type epitaxial layer 4 is formed.

Next, phosphorus is added to the N-type epitaxial layer 4 by a known ion implantation technique at a dose of 2×10” am acceleration voltage 17
Injected at 0 KeV, drive-in at 1000°C for about 20 minutes, sheet resistance 150Ω/hole, diffusion depth 1.
A 5n N-type layer is simultaneously formed in the bipolar transistor formation region 5 and the PMOS formation region 6.

Next, boron is implanted into the N-type epitaxial layer 4 by a known ion implantation technique at a dose of 4×10”e1m at an acceleration voltage of 10
Injected at 0 KeV, drive-in at 1000°C for about 20 minutes, sheet resistance 6 Ω/hole, diffusion depth 1.5.
A P-type layer of n is simultaneously formed in the isolation region 7 of the bipolar transistor and the NMOS formation region 8.

Furthermore, using a known LOGO3 separation method, LOCO3
Oxide film 9, emitter/base formation region 10 of bipolar transistor, collector formation region 11 and 8MO
After forming the 3-forming region 12 and the PMOS-forming region 13, acid treatment is carried out at 950° C. for about 30 minutes to form an oxide film 14 with a thickness of 200 μm in each element-forming region.

Next, as shown in Part 1), the oxide film 14 of the emitter/base formation region 10 and collector formation region 11 of the bipolar transistor is etched using a known photolithography and etching technique, and the oxide film 14 of the emitter/base formation region 10 and collector formation region 11 of the bipolar transistor is etched. V D (
Low Pressure Chemical Vap
orDeposition) method, the thickness is 1500 mm.
After forming the non-doped polysilicon M*15, a tungsten silicide film 16 with a thickness of 2000 nm is formed over the entire surface using a known vapor deposition technique.

Next, as shown in FIG. 1(c), oxidation is performed at 900° C. for about 15 minutes to form an oxide film 17 with a thickness of about 200 mm. After forming a nitride film 19.20 with a grade 0, holes are selectively opened in the collector formation region 60 and emitter formation region 18 of the bipolar transistor using known photolithography and etching techniques, and nitride is formed so as to surround the emitter formation region 18. membrane 19
, leaving the oxide film 17 and tungsten silicide film 16,
Then, the nitride film 20, oxide film 17, and tungsten silicide film 16 in the NMOS and PMOS forming regions are left, and the nitride film, oxide film, and tungsten silicide film in other regions are etched.

Next, as shown in Figure 1 (dl), 7 atm, 030t
Oxidation is performed for about 15 minutes to oxidize the portion of the polysilicon film 15 that is not covered with the nitride film 19 and 20, resulting in a thickness of 4.
The 0 oxide film 21 is formed by about 1,000 people.

Next, as shown in FIG. 1(e), using the oxide film 17.21 and the nitride film 19.20 as masks, the tungsten silicide film 22 is etched by about 0.1 to 0.2 degrees with aqua regia. .

Hereinafter, details of the technology for forming the emitter part in the emitter/reflection forming region 18 of this bipolar transistor will be described.
CICC”88 r Proceedings of
theIE' 1988 CICCJ P22.4.1
~22.4.4, so the explanation in the subsequent figures will be simplified.

Next, as shown in FIG.
The nitride film 20 and oxide film 17 in other regions are etched, leaving only the nitride film 20 and the oxide film 17 in other regions.

Next, using known ion implantation techniques, the NMOS PMO
Phosphorus is added to the tungsten silicide film 16 on the S formation region 24 at a dose of 1. XIO"c+m-, acceleration voltage 7
Implant at 0 KeV.

Next, as shown in FIG. 1(g), the NMOS gate formation region 25 is etched using known photolithography and etching techniques.
Then, leaving the tungsten silicide film 16 and polysilicon film 15 in the PMOS gate formation region 26, the tungsten silicide film 16 and polysilicon film 15 in other regions are etched.

Next, as shown in FIG. 1(h), the resist 27 is selectively left in the NMOS and PMOS forming regions 24 using a known photolithography technique, and the resist 27 is left selectively in the NMOS and PMOS forming regions 24 using a known ion implantation technique.
Poron is implanted into areas other than the NMOS and PMOS forming regions 24 at a dose of 2×IQISC1a4 and an acceleration voltage of 140 KeV.

Note that, since the thick oxide film 21 is formed in the regions where the internal base and emitter will be formed later and the collector will be formed, poron is not implanted into these regions.

Next, using the resist 27 as a mask, the oxide film 21 is etched by about 4,000 layers by wet etching.

At this time, in the region 28 where the thickness of the oxide film 21 was originally 4,000 nm, the silicon surface is roughened, and in the region 29, where the oxide film thickness was originally 12,000 nm, the LOCO3 oxide film 9 has a field oxide film thickness. Then, as shown in FIG. 1(1), after removing the resist 27, oxidation is performed at 800° C. for about 20 minutes to form an oxide film 30 with a thickness of 180 layers.

Next, using a known photolithography technique, a window is selectively opened in the resist only in the base forming region 31 of the bipolar transistor, and using a known ion implantation technique, poron is implanted into the base forming region 31 at a dose of 1.5×10 13 am.
-, implanted at an accelerating voltage of 10 KeV. After that, 800℃
After annealing for about 30 minutes, the sheet resistance was 1.5, Ω10, and the diffusion depth was 0.15. ffIm internal base 32
form.

This annealing causes poron to diffuse from the tungsten silicon 1916 and the polysilicon film 15 into the N-type layer of the bipolar transistor formation region 5, forming an external base 33 with a sheet resistance of 200Ω10 and a diffusion depth of 0.2n.
is formed.

Next, using a known photolithography technique, a window is selectively opened in the resist only in the source/drain forming region 34 of the PMOS, as shown in FIG. Poron is implanted into the source/drain formation region 34 at a dose of I.times.10@13 cm@- and an acceleration voltage of 3 QMeV to form a PMOS offset layer 35.

Next, a well-known photolithography technique is used to selectively open a window in the resist only in the NMOS source/drain formation region 36, and a well-known ion implantation technique is used to inject phosphor into the NMOS source/drain formation region 36. The dose amount is 1.
5×1013 cm−, implanted at an accelerating voltage of 3QKeV,
An NMOS offset layer 37 is formed.

Next, as shown in Figure 1), an oxide film 38 with a thickness of 1000 nm is formed on the entire surface using the known LPCVD method.
Thereafter, a polysilicon film 39 having a thickness of 2,000 wafers is formed over the entire surface.

Next, as shown in FIG. 1(N), the polysilicon film 39 and oxide films 38 and 30 are anisotropically etched using RIE. In this figure, - is the aperture width of the emitter formation region in FIG. 1(c) (in this example, the minimum resolution dimension is 1p), and 4 is the width of the sidewall. The radius can be varied depending on conditions such as gas flow rate and pressure during etching, and in this example, it is set to 0.2R. 40 is shown in Figure 1 (
1(R), 41 is the remainder of the oxide film 38 in FIG. 1(R), and 42 is the 119th +
This is the remainder of the +1 oxide film 30. The emitter width -5 formed in this way is J=L 2 XL=1.0 2 Xo, 2=
The minimum resolution size is 0.6 Jll, and the minimum resolution size is 1. It is possible to obtain an emitter width smaller than that of On.

In addition, the NMOS formation region 12 and the PMOS formation region
3, for example, 1. 0. compared to OB's -6.
It is possible to realize an offset layer width of 2μ -1.

Next, as shown in FIG. 1(b), oxidation is performed at 900° C. for about 30 minutes to form an oxide film 43 with a thickness of 200 μm.

Next, using photolithography and etching techniques, only the oxide film 43 in the base/emitter forming region 23 of the bipolar transistor is etched.

Next, as shown in FIG. 1 (nl), using a known photolithography technique, windows are selectively opened in the resist only in the source/drain forming region 36 of the NMOS and the collector forming region 11 of the bipolar transistor. NMOS source/drain formation regions 36 are formed using ion implantation technology.
and the collector forming region 11 at a dose of 5 x
l, 0”cs−, implanted at an accelerating voltage of 40 KeV, NMO
A source/drain layer 44 of S and a collector layer 45 of a bipolar transistor are formed at the same time.

Next, as shown in FIG. 1(0), a polysilicon film 46 with a thickness of 3000 nm is formed on the entire surface using the known LPCVD method, and oxidized at 800° C. for about 20 minutes to form a polysilicon film 46 with a thickness of 160 nm. A human oxide film 47 is formed.

Thereafter, using a known ion implantation technique, hiso is implanted into the polysilicon film 46 at a dose of 1 xl Q I 6 Rho 2 at an acceleration voltage of 40 eV.

Next, as shown in FIG. 1 (ρ), using a known photolithography and etching technique, the polysilicon film 50 with the oxide film 49 that will become the emitter electrode 48 of the bipolar transistor is left, and the other regions are oxidized. The film 47 and polysilicon film 46 are etched.

Next, as shown in FIG. 1+q+, a window is selectively opened in the resist only in the source/drain formation region 34 of the PMOS using a known photolithography technique, and a window is formed in the resist using a known ion implantation technique. Boron is implanted into the source/drain formation region 34 at a dose of 2 XIO"cs- and an acceleration voltage of 40 KeV, and
Form 1.

After that, oxidation was carried out at 800℃ for about 20 minutes to obtain a thickness of 9.
An oxide film 52 of 0.00000000000 is formed on the entire surface.

Next, as shown in FIG. 1 tr+, the nitride film 19 on the base/emitter forming region 23 of the bipolar transistor is etched using phosphoric acid and using the oxide 11u52 as a mask.

Next, as shown in FIG. 1, a BPSG film 53 is formed as an insulating film to a thickness of about 7,000 using a known CVD method.

Thereafter, the surface is flattened by annealing at 920° C. for about 30 minutes.

By this annealing, the hisso from the polysilicon film 50 serving as the emitter electrode is diffused into the internal base layer 32 of the bipolar transistor, forming an emitter layer 54 having a sheet resistance of 20Ω10 and a diffusion depth of 0.1μ.

Thereafter, a contact hole for electrode connection is formed and a metal electrode is formed using a known technique, thereby completing a Bi CMO3 type semiconductor device.

In addition, according to the experimental data of the inventors, when the manufacturing method of the present invention is used, the life time (change time of 10% g, VB, 3= 8
V, Vcs-4V) r, B with r=ixto5ec (gate length 1.0μ, gate width 20n)
i A CMO3 type semiconductor device was realized.

As for the cause of the increase in the lifetime τ of NMO5, FIG. 2 shows the results of simulating the electric field strength near the gate and drain of the NMOS transistor manufactured according to the present invention. A in FIG. 2 is an example of the present invention, and B is a conventional example.

From FIG. 2, it is considered that the electric field strength can be significantly reduced compared to the conventional method, and as a result, the hot electron effect is suppressed, and the lifetime of the transistor is improved.

In addition, the bipolar transistor has an emitter width smaller than the minimum resolution dimension, and the resistance value of the base extraction electrode is 4X4J1.
1”, and the sheet resistance value of the polysilicon film is 150Ω.
10. The sheet resistance value of the tungsten silicide film is 10.
When manufactured under the conditions of Ω/mouth, the resistance value of the conventional example is 1
The resistance value of this invention example was 9.4Ω.

As described above, the resistance value of the base lead-out electrode portion of the present invention is approximately 1716 compared to the conventional example, and high-speed operation is possible.

(Effects of the Invention) As described above in detail, according to the present invention, the oxide film/polysilicon film of the spacer that determines the emitter dimension of the bipolar transistor is also used in the MOS transistor to produce an MO3I-transistor with an LDD structure. Since this configuration allows the formation of a CMOS transistor with a sidewall structure while retaining the feature of forming a bipolar transistor with an emifter width smaller than the minimum resolution dimension.

In addition, by forming the low resistance gate electrode of the CMOS transistor and the base electrode of the bipolar transistor at the same time, it is possible to reduce the resistance of the base electrode of the bipolar transistor, which improves the high speed of the bipolar transistor and the reliability of the CMOS transistor. This can also be achieved by improving sexual performance.

[Brief explanation of drawings]

1al to 1al are BiCMs of the present invention.
A process cross-sectional view of an embodiment of a method for manufacturing an OS type semiconductor device,
Fig. 2 is a comparative characteristic diagram of the electric field strength near the gate and drain of conventional NMOS transistors and NMOS transistors obtained by the present invention, and Fig. 3 (al to Fig. 3 (d+ is a conventional BiCMO transistor)
Process cross-sectional diagram of the method for manufacturing an S-type semiconductor device, FIG. 3 (el
3ffl is an enlarged sectional view of the emitter-base boundary of a conventional bipolar transistor, and FIG. 4 is an enlarged sectional view of the emitter of a conventional bipolar transistor.
FIG. 5 is a perspective view of a conventional MOS transistor, and FIG. 6 is an electric field distribution diagram in a channel of the conventional MOS transistor. DESCRIPTION OF SYMBOLS 1... Substrate, 5... Bipolar transistor formation area, 6 -PMOS formation area, 8.24-NMO
S formation region, 15, 39, 40, 46.50... polysilicon film, 16... tungsten silicide film, 3
2... Internal base, 33... External base, 34...
・PMOS source/drain formation region, 36...N
MOS source/drain formation region, 3841.42.
52... Oxide film, 44.51... Source/drain layer, 45... Collector layer, 54... Emitter layer. Kenito Drain Pime Electric Enthusiasm Zu 1 Ao Tsui Otsu No. 2 Figure City ε Mime Kochangu-su Old PJ4 Dai 1 Town-IE2] No. 3
Arts and Crafts (Shiku death flash)

Claims (1)

[Claims] (a) After forming a first oxide film on the semiconductor substrate in areas other than the bipolar transistor formation area separated from the CMOS transistor formation area, a first polysilicon film, a tungsten silicide film, and a second oxide film are formed on the entire surface. After the step of sequentially forming an oxide film and a nitride film, and (b) opening the emitter formation region and collector formation region of the bipolar transistor, a tungsten silicide film and a first (c) After implanting an impurity only into the emitter formation region of the bipolar transistor, forming an internal base and an external base in the opening of the emitter formation region by implanting impurities and heat treatment. and (d) forming the PMOS and NMOS sources in the CMOS transistor formation region.
Forming an offset layer in the drain formation region by sequentially implanting impurities; and (e) forming a third oxide film and a second polysilicon film on the entire surface and etching them to form an opening in the emitter formation region and A step of forming sidewalls in each gate formation region of PMOS and NMOS, and (f) implanting impurities into the collector formation region of the bipolar transistor and the source/drain formation region of the NMOS, and simultaneously forming the collector layer and source/drain region. (g) After forming a third polysilicon film and an oxide film on the entire surface and implanting impurities into the third polysilicon film, this third polysilicon film is formed only in the opening of the emitter formation region of the bipolar transistor. (h) Injecting impurities into the PMOS transistor formation region to form a source/drain layer, and then diffusing impurities from the third polysilicon into the internal base by heat treatment. A method of manufacturing a BiCMOS type semiconductor device, comprising: forming an emitter layer using the same method.