JPH02196434A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To form a transistor of LDD structure having a source drain diffusion interval equal to minimum resolution dimension by a method wherein a mask layer left in a gate region is used as a mask, and a polysilicon gate electrode whose section has a trapezoidal shape is formed by selectively oxidizing a polysilicon film. CONSTITUTION:On the surface of a semiconductor substrate 601, a polysilicon film 605 is formed via a gate oxide film 604. A mask layer 609 formed on the film 605 is left only on a gate region. The polysilicon film 605 is oxidized by high pressure oxidizing method using the mask layer 609 as a mask. Thus a gate electrode 612 whose section has a trapezoidal shape is formed under the mask layer 609, by using the residual polysilicon film 605. The other polysilicon films are all converted into an oxide film 610. After unnecessary oxide films except gate electrode are eliminated, impurity is ion-implanted by using the mask layer 609 as a mask, and the diffusion layers 614, 615 for a source drain are formed. After that, the mask layer 609 is eliminated, and impurity is ion-implanted on the whole surface, thereby forming a low concentration layer 616 under both sides of the gate electrode 612 whose section has a trapezoidal shape.

Description

[Detailed description of the invention] (Industrial application field) The present invention is based on LDD (Lightly dope)
The present invention relates to a method of manufacturing a MOS transistor having a d drain structure.

(Prior art) MO3) transistor, specifically MO3 type field effect transistor (MOS FET; Metal-Oxid)
e-5e+m1eonduetorField Eff
eet Transistor) as a component.
In one circuit, the element size of an MO3+- transistor formed on a semiconductor substrate is generally reduced in order to improve the integration density of an integrated circuit.

By the way, the basic structure of a MOS transistor is
As shown in the figure, a schematic diagram of a basic n-channel type MOS transistor, an St substrate (P-type silicon substrate 101)
) on both sides of a so-called MOS capacitor on which a metal electrode (polysilicon electrode 104) is provided via a thin oxide film (gate oxide film 103), a source 10 serving as a carrier supply source is placed.
5 and the drain 106 from which carriers are taken out are formed by a diffusion layer (N
+ diffusion layer 102), and the adjacent MO
S) Separation from transistor is thick field oxide film 107
It is carried out by

In reducing the element dimensions of this MOS transistor, it is essential to reduce the gate length as shown in the figure in addition to reducing the area of the source, drain 105, 106, etc. The scaling law is well known as a method for scaling down MOS transistors. According to this scaling law, the MOS transistor shown in FIG.
1/K.

The thickness of the gate oxide @103 is reduced to 1/1, and the N+ diffusion layer 102 is
When the depth of the gate is reduced to 1/1 and the gate length is reduced to 1/1, especially when the gate length becomes about 1.5 μm or less,
A current is injected into the oxide film 103 due to a phenomenon called hot carriers, causing a problem of causing characteristic fluctuations of the MOS transistor.

To elaborate on this point, in the extreme state of bipolar operation, the electric field C in the channel of a MOS transistor is simply ε"vOJ/L-ff (1) However,
voe is the source-drain voltage, and fμ is the effective gate length (see Figure 6). In the pentode operating state,
As shown in FIG. 7, the electric field is concentrated in the depletion layer region near the drain. Therefore, the maximum value of the electric field ε71. is a much larger value than shown in equation (1).

When scaling down this MOS transistor, as shown in equation (1), V is proportional to elf, that is, the power supply voltage (
If the electric field ε could be lowered (11 operating voltage), the electric field ε would not increase, but due to the requirements of using MO8ta product circuits, it is difficult to lower the power supply voltage, and as a result, the electric field C is proportional to the reduction in gate length. This will result in an increase.

Here, regarding the relationship between the effective gate length, #, and the gate length, as is clear from FIG. 6, if the depth of the diffusion layer 102 is constant, L=L,...+2 a ( There is an arithmetic relationship with a (the extent of the N+ diffusion layer in the tank direction).

As explained above, in dipole operation, ε increases in proportion to the reduction in the effective gate length, but the same holds true for pentode operation, and furthermore, in pentode operation, the drain junction decreases due to the influence of the gate electrode. In addition to the increase in the electric field in the depletion layer near the oxide film boundary, if the gate oxide film (gate oxide film 103 in Figure 6) is thinned according to the shrinkage period, this increase in electric field will be further accelerated. Become.

For the reasons explained above, a strong electric field has enough strength to generate sufficient hot carriers. Carriers flowing in the channel, especially in the drain depletion layer, are accelerated by the strong electric field C in the depletion layer, and hot carriers with sufficient energy jump out of the channel without being trapped in the channel, increasing the substrate current. or injected into the oxide film. Then, some of the carriers injected into the oxide film of and/or are trapped or generate surface levels, resulting in a shift in the threshold voltage v7H, a decrease in the mutual conductance g, This causes characteristic deterioration such as increased leakage in the subthreshold silt region. It is said that this deterioration in characteristics due to hot carriers is remarkable in NMOS transistors with a gate length of 1.5 μm or less.

In order to prevent characteristic fluctuations due to hot carriers of NMOS transistors, a method has been proposed in which a lightly doped N offset layer is provided between a heavily doped N+ drain and a P- layer below the gate.

This structure is called LDD (Lightly Doped
The idea is to alleviate the peak electric field strength of the drain depletion layer that occurs in a pinch-off state. In other words, by lowering the concentration of the drain, the depletion layer is extended to the drain side, and the voltage on the substrate side is reduced to weaken the electric field.

A first example of the conventional manufacturing method of an N-channel MOS transistor having an LDD structure is shown in FIGS.
1 and will be explained below.

First, a thick isolation oxide film (7000 Ω deposited) 202 and an element formation region 203 are formed on a P-type (100) 3.5 Ω substrate 201 using the well-known LOCO8 method.
A gate oxide film 204 with a thickness of 200 layers is formed at 0.degree.

Next, a polysilicon film 205 was formed to a thickness of 3000 nm over the entire surface of the substrate using the low pressure CVC method, and then a polysilicon film 205 was formed at 900°C.
Perform the debojishi seal in the atmosphere of OCj3 + N2 + 02,
Phosphorus is diffused into the polysilicon film 205 to make the polysilicon a phosphorus-doped film (FIG. 8(b)).

Next, a positive resist is applied to the entire surface of the substrate, and a resist 206 for forming gate polysilicon is formed by a well-known photolithography technique (FIG. 8(C)). At this time, the gate length is here 1 μm as shown in the figure.

Next, the polysilicon film 205 other than the area covered with the resist 206 is removed by etching, and the resist 206 is removed.
By removing the gate polysilicon electrode 207 made of the remaining polysilicon film 205 under the resist 206,
is obtained (Fig. 8(d)).

Next, using the gate polysilicon electrode 207 as a mask,
1.5×10'3/P (phosphorus) was added by ion implantation method.
By implanting cIl at a dose of 33 keV and an acceleration energy of 33 keV, the two-layer resistance at a depth of 0.18 μm was reduced to 1.6 Ω.
An offset N-layer 208 is formed (FIG. 8).
e)).

Then, P2O6vIA was applied to the entire surface of the substrate by low pressure CVD method.
12 wt % of PSGg[209] was formed to a thickness of 3000 mm (FIG. 8(f)).

Next, the PSG film 209 is etched by RIE (reactive ion etching) to form a gate sidewall oxide film 210 made of the remaining PSG film 209 (FIG. 8(g)). At this time, the width W of the sidewall is 0.3 μm.

Next, heat treatment is performed at 900°C in 02 atmosphere, and the following As
Oxide film 211 that serves as a protective oxide film during ion implantation
A 200-person-thickness 0 game is created (Figure 8 (h)).

Next, As is ion-implanted under the conditions of 40 keV and lXl0''/d to obtain the source/drain layer 212 (FIG. 8(i)). At this time, the sidewall 210
The N layer 208 in the region where s was not ion-implanted remains,
A φN offset layer (that is, LD DI) is formed by N-11208 in that portion.

Next, BPSGllJ213 is formed as an interlayer insulating film to a thickness of 7,000 wafers over the entire surface, contact holes 214 and 215 for source and drain are opened, and then metal evaporation and metal patterning are performed to form the source.

By forming the drain electrodes 216 and 217,
An N-channel type MO8 transistor having an LDD structure is completed (FIG. 8(j)).

Figure 12 1g) to td) are from Japanese Patent Application Laid-Open No. 80-12776.
This is a second example of a method for manufacturing a conventional LDDW N-channel type MO3) transistor disclosed in Publication No. 1. Next, this method will be explained.

In step fa) shown in FIG. 12 [a], an oxide film 300 with a thickness of 6000 mm is formed on a P-type (100) substrate 301 by selective oxidation.
After forming a gate oxide film 303 with a thickness of 200 mm, a tungsten silicide film 304 that will become a gate electrode is deposited on the entire surface to a thickness of 2000 mm, and then
000 oxidation to form an oxide film 305, and then 1000
After depositing a human-thick Si3N4 film 306, Si, N4!1I306 and oxide film 305 are deposited using photolithography technology.
was left on the gate.

Next, in step (b) shown in FIG. 12 (bl), 3000 people selective oxidation is performed to form an oxide film 307. Next, the oxide film 307 is removed by wet etching containing HF, and the remaining thin film is removed. The tungsten silicide film is etched using an anisotropic etching solution to form the shape shown in FIG. 12(C), thereby forming a tapered gate electrode 308.

Next, after removing the 5t3N4 film 306, as shown in FIG. 12(d), 4 x 1018 am'' As ions were implanted at an acceleration energy of 60 kaV, and the ion implantation was performed at 950°C for 3
By performing heat treatment for 0 minutes, a MOS transistor having an LDD structure drain 309 is completed.

Figures 13 [a] to (f) are from Japanese Patent Application Laid-Open No. 17006-1986.
This is a third example of a method for manufacturing a conventional LDD structure N-channel type MO3) transistor disclosed in Japanese Patent No. 4. Next, this method will be explained.

First, as shown in FIG. 13(a), a field oxide film 402 is formed using a P-type silicon substrate 401 by a conventional selective oxidation method. Next, as shown in FIG. 13(b), a gate oxide film 403 is formed on the P-type silicon substrate 401 by thermal oxidation, and a polysilicon film 403 that will become the gate electrode is formed.
04 was deposited to a thickness of 400 nm on the occlusal membrane by the CVD method. Then, in order to make the polysilicon 404 conductive, it is doped with phosphorus at a concentration of 5×10 effI, and then an oxide film 405 with a thickness of 30 nm is formed on the surface of the polysilicon by thermal oxidation. Furthermore, a silicon nitride film 406 is deposited to a thickness of 150 nm using the CVD method.

Next, as shown in FIG. 13(e), the resist 407 is patterned, and the resist 407 is used as a mask.
The silicon nitride film 406 is etched by dry etching using F. gas. At this time, polysilicon 40
The oxide film 405 on 4 serves as an etching stopper.

Next, after removing the resist 407, the silicon nitride film 406 is used as an oxidation-resistant mask as shown in FIG.
The exposed portion of the polysilicon 404 is completely converted to SiO□ in a wet oxygen atmosphere at 0°C to 1000°C. At this time, since 5in2 sinks under the silicon nitride film 406, a taper 404m is formed at the edge of the polysilicon 404, as shown in FIG. If the film thickness, phosphorus concentration, and oxidation conditions are kept constant, then it becomes almost constant.

Next, as shown in FIG. 13(e), the silicon nitride film 4
06 is removed, and unnecessary portions of S i O, are further etched with a buffered hydrofluoric acid solution.

Next, as shown in FIG. 13(f), using the gate polysilicon 404 as a mask, arsenic is implanted to form an N+ diffusion layer 408 in a self-aligned manner. At this time, the taper 4 of the edge of the gate polysilicon 404 is
At the same time, low concentration N@409 is formed by 04a.

Thereafter, an insulating film is formed using a known technique (not shown), contact holes are formed, wiring is provided, and padding is performed to complete the device.

(Problem W1 to be Solved by the Invention) However, among the conventional techniques described above, the first method of forming an LDD layer shown in FIG. 8 (1) makes it difficult to obtain a gate length with minute dimensions (2) There is a problem in that the electric field is concentrated at the interface between the N- layer 208 and the N+ drain layer 212. This problem will be explained in detail below.

(1) Regarding gate miniaturization In general, in the production of semiconductor integrated circuits, the minimum resolution dimension that can be stably obtained on the production line is called the i8I circuit design rule, and the degree of integration of integrated circuits using MOS transistors is called the i8I circuit design rule. In order to improve this, the dimensions of the contact holes 214 and 215 and the gate polysilicon electrode 207 in FIG. 8(j) are designed using this design rule. This minimum resolution size mainly depends on the performance of the mask aligner. Now, if we were to design an N-channel MOS transistor (NMO8) with this LDD structure using the 1 μm design rule, it would be shown in Figure 9 (the same parts as in Figure 8 are given the same symbols as 8FI!J). Between N+ source and N+ drain (source and drain F
l 212 mutual) is 1μm + 2X0.3μm = 1.6
.mu.m, the distance between the N+ source and N+ drain becomes wider than the photolithographic minimum resolution dimension, and the characteristics of 1 .mu.m NMO3 deteriorate.

To shorten this N+ source/N+ drain distance,
For example, it is possible to prepare a mask aligner with a minimum resolution of 0.8 μm or 0.6 μm, but in general, thin aligners with minimum resolution dimensions are expensive, and NMO3 transistors (i.e. The problem is that it is difficult to obtain the G7's large high-performance transistor.

(2) f! FIG. 10 shows the relationship between the concentration of the N- layer and the electric field (V/cm) in the N- layer and the N+ drain layer regarding the concentration of the four fields. As can be seen from the figure, when the N~ concentration is low, the electric field is concentrated at the N7N+ boundary. This is because the N- layer is thin, and when a voltage is applied to the source/drain, the N'- layer is quickly depleted. Conversely, if the concentration is high, such as in the case of 9.8X 10 l7cm-3 in the figure, depletion of the N-layer is difficult to occur, and the electric field is concentrated at the boundary between the gate and the N-layer, causing a rough N-
The electric field becomes stronger than when the concentration is lowered, and has a value close to causing deterioration of the MOS transistor as described above. Therefore, it is necessary to determine the concentration of the offset layer so that the electric field is uniform within the N offset layer and is not concentrated in a particular region. In the case of FIG. 1θ, the N- concentration shown by the profiles of ■ and ■ is uniform. However, if the concentration of the N-layer is made too low, parasitic drain resistance will be introduced, and by choosing a value that is as small as possible and has a low electric field concentration in the N-layer, the drain resistance will be reduced somewhat near the gate, as shown by the broken line O in Figure 10. Although the electric field is high, it has been common practice to select an N-layer concentration that affects the characteristics of the transistor.

One way to prevent the electric field concentration in the N-layer from concentrating directly under the gate or at the N/N'' layer boundary is to give the N-layer a concentration gradient in the lateral direction. Axis on Electron Devices (IEEE Transaction
s on Electron Devices) E
D-29, 1982, P611 and shown in FIG.
ffusedDrainHDDD), that is, the same opening 5 is formed using the gate polysilicon 501 as a mask.
From 02 onwards, ions of phosphorus for forming an N- layer and arsenic for forming an N+ layer are sequentially implanted through the gate oxide film 503 to form an N- layer 504. N'' layer 505 to P-substrate 50
6 has been proposed. in this way,
Although it is true that the N-layer has a sloped profile as shown in the lower part of the figure, the short channel effect of the MOS FET cannot be ignored because the phosphor must be diffused from the edge of the gate electrode. , 1.5
It has been difficult to realize a MOS FET with a gate length of less than μm.

The second example in Figure 12 and the third example in Figure 13 are methods devised to solve the drawbacks of the first example, but these methods also have drawbacks as summarized below. .

(1) As to form the LDD layer directly under the gate
When attempting to implant impurities such as these by ion implantation, high energy is required. However, since the source and drain layers are formed at the same time with these impurities, when ion implantation is performed at high energy, the diffusion depth of the source and drain layers becomes deep (or shallow) due to subsequent heat treatment. It becomes impossible to form a source/drain junction, and as a result, an increase in the m-integrity of the device is prevented.

(2) In both methods, the gate electrode is oxidized at normal pressure, so the taper is gentle, and when the gate is viewed from the cross section, for example, Fig. 12 fd) and Fig. 13 (
There is a problem that the area of the trapezoid of the gate in (g) is small, and if this area is small, there is a problem that the resistance component of the gate electrode becomes large.

This invention provides an LD having a source-drain distance larger than the photolithography minimum resolution dimension of the first conventional example described above.
This solves the problem that only the D structure can be realized, ■ The structure in which the electric field directly under the gate increases to obtain drain current, so the deterioration of the MOS transistor becomes faster. ■ Minimum photolithographic resolution dimension = source-drain distance , (2) It is an object of the present invention to provide a method for manufacturing an LDD structure MOS transistor that can make the electric field distribution in the LDDlii uniform without sacrificing the drain current.

Furthermore, this invention is based on the above-mentioned 2. ■L in the third conventional example
Since the DD layer and the source/drain layer cannot be controlled independently, the source/drain diffusion layer becomes deep, making it impossible to realize a fine transistor. ■The gate electrode has a gentle taper, making it impossible to reduce the gate resistance. ■The LDD layer and the source/drain layer can be controlled independently to realize a fine transistor.■The taper of the gate electrode can be made steeper to lower the gate south pole resistance. The purpose is to provide a manufacturing method.

(Means for Solving the Problems) In the present invention, after forming a gate insulating oxide film on the surface of a semiconductor substrate, a polysilicon film for forming a gate electrode is formed on this gate insulating oxide film, and this polysilicon film is formed on the gate insulating oxide film. By forming a mask layer on the silicon film, leaving this mask layer selectively only on the gate region, and then oxidizing the polysilicon film by high-pressure oxidation using the mask layer remaining on the gate region as a mask, A gate oxide film with a trapezoidal cross section is formed under the mask layer using the remaining polysilicon film, and all other polysilicon films are converted to oxide films, including the converted oxide film.
After removing unnecessary oxide films other than the gate electrode portion, impurity ions are implanted using the mask layer in the gate region as a mask to form source/drain diffusion layers in the substrate on both sides of the gate electrode, and then, By removing the mask layer and implanting impurity ions over the entire surface, a low concentration layer connected to the source/drain diffusion layer is formed in the substrate under both sides of the gate electrode having a trapezoidal cross section.

(Function) In the above invention, for example, as shown in FIG.
Using the mask layer left in the gate region as a mask, source/drain diffusion layers are formed with minimum resolution dimension=source/drain interval.

In addition, by using the eaves of the polysilicon gate electrode formed to have a trapezoidal cross section by selective oxidation of the polysilicon film using the mask layer as a mask, Utilizing the fact that a certain amount of impurity is ion-implanted into the substrate, a low concentration layer having a sloped concentration profile is formed in the substrate under the eaves, as shown in FIG. 4, for example.

In addition, when forming a polysilicon gate electrode with a trapezoidal cross section by selective oxidation of the polysilicon film, the polysilicon film is selectively oxidized using a high pressure oxidation method, so that the gate electrode with a trapezoidal cross section made of the remaining polysilicon film is For example, a steep side surface (tapered surface) can be obtained as shown in FIG.

In addition, the source/drain diffusion layers are formed by ion implantation using the mask layer as a mask, and then the mask layer is removed and the low concentration layer is formed by the second ion implantation. layers can be controlled independently, and therefore the electric field strength can be optimized without affecting the formation of the source/drain diffusion layers.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1(a) to (jl).

First, P-type (100) 3.5Ω (to) silicon substrate 6
In 2001, a thick isolation oxide film (7
000 C) 602 and an element formation region 603, the surface of the substrate 601 in the element formation region 603 is heated at 950°C.
, 0□ atmosphere to form a 0 gate oxide film 604 with a thickness of 200 layers (FIG. 1(a)).

Next, a polysilicon film 605 was formed to a thickness of 3,000 mm over the entire surface of the substrate including the top of the gate oxide film 604 by low pressure CVD, and then a polysilicon film 605 was formed to a thickness of 900 mm.

Phosphorus is diffused into the polysilicon film 605 by deposition in an atmosphere of POCJ3+N2+O, thereby making the polysilicon film 605 a phosphorus-doped film. Furthermore, a part of the surface layer of this polysilicon film 605 is oxidized at 900° C. in a 0° atmosphere to form a 200-layer thick 0-germ film 606.
On top of that, a 3,000-layer thick Si, N4 film 6 was applied using the low-pressure CVD method.
07 (first opening)).

Next, a positive resist is applied to the entire surface of the substrate, and a resist pattern 608 is formed using a well-known photolithography technique (
Figure 1 (C)). At this time, the resist pattern size is 1 μm as shown in the figure.

Next, by etching, the Si3N4 film 607 is removed from areas other than those covered by the resist pattern 608, and by subsequently removing the resist pattern 608, a remaining pattern (Si3N4 film pattern) 609 of the Si3N4 film is obtained. Figure (d)). Please leave the St3N4 film pattern 609 in the gate region.

Next, using the Si, N, film pattern 609 as a mask, oxidation (high pressure oxidation) is performed for about 40 minutes in a wet 02 atmosphere at 7 atmospheres and 950°C.
05-n Note S All parts not covered with the 13N4 film pattern 609 are converted into an oxide film (FIG. 1(e)).

As a result, in the element formation region 603, gate oxidation l14
An oxide film 610 with a thickness of 8,000 wafers including the oxide film 604 and a part of the oxide film 606 is formed, and in the field region where the isolation oxide film 602 was located, an oxide film 610 with a thickness of 8,000 wafers including the isolation oxide film 602 is formed.
An oxide film 611 having a thickness of 500 nm is formed. At this time, S
The polysilicon group 605 under the i3N4 film pattern 609 is not oxidized and becomes the polysilicon gate electrode f pole 612, but oxidation progresses partially due to the diffusion of oxygen from the edge of the Si3N4 film pattern 609, as shown in FIG. The polysilicon film 605 is oxidized so that both ends of the Si, N4 film pattern 609 are raised as shown in el.
5 is oxidized at an angle of about 45° with the bottom surface (θ#45 in the figure).
), if the polysilicon film thickness is 0.3 μm, Si3N
The oxidation progressed to a position of JW=0.3 μm (at the end of the film pattern 609). In other words, the width of the eaves is 3 μm,
A trapezoidal polysilicon gate electrode 612 with a steeply tapered side surface of 445° was obtained. This gate electrode 61
The shape of No. 2 is shown enlarged in FIG. In addition, in Figure 2,
The broken line indicates the shape of a polysilicon gate electrode when selective oxidation of polysilicon is performed by normal pressure oxidation. In the inventor's experiments, the side surface was gently tapered to 35 to 40 inches in normal pressure oxidation, although of course there are influences such as the oxidation temperature of 2 hours.

Next, the oxide films 610 and 611 are etched by 500 mm. As a result, all the oxide film is removed on both sides of the gate electrode in the element formation region 603, the surface of the silicon substrate 601 is exposed, and in the field region,
A part of the oxide film 611 is a field oxide film 622 for isolation.
(Fig. 1(f)).

Next, the exposed surface of the substrate on both sides of the gate electrode was heated at 900°C.
The protect oxide film 613 is oxidized in 0.02 atmosphere.
After depositing 0.00 ke of As (at this time, an oxide film is also formed on the side surfaces of the gate electrode 612), 40 ke of As is deposited.
Ions are implanted into the entire surface under the conditions of V, lXl0''/d.

At this time, the thickness is 3000 people (7) S i3N4gl
Since the zf turns 609 and the oxide film 622 with a thickness of 6,500 yen act as a mask and cover the gate region and field region, As is applied only to the substrate portions on both sides of the gate electrodes, that is, to the source/drain formation regions. is ion-implanted, and 84 layers 61 of source and drain are formed there.
4°615 is formed by self-alignment (FIG. 1(g)).

Next, the 5t3N4 film pattern 609 is removed by etching with hot phosphoric acid to obtain the structure shown in FIG. 1 (hl).

Next, P was applied to the substrate 60 using the ion implantation method at a dose of 1.5×10!3 pieces/cd and an acceleration voltage of θV to 100.
Inject into 1. Then, P is the source and source on both sides of the gate electrode.
In addition to the drain formation region, ions are implanted into the substrate under the eaves through both side eaves of the trapezoidal polysilicon gate electrode 612. Therefore, N ions connected to the source and drain N''1i 1614 and 615 are implanted under the eaves. - Form an offset layer 616 (FIG. 1(1)).

Moreover, at this time, the trapezoidal polysilicon gate electrode 612
Since the amount of impurity implanted corresponds to the thickness of the eaves,
The N-off upper 98 layer 616 will have a graded concentration profile. Regarding the concentration profile of the N offset layer I-IJ 61s, the concentration is highest at the boundary with the 84 layer 614°615, and gradually becomes thinner toward the lower part of the P- layer, that is, the center of the gate electrode.

Next, a 70% BPSG film 617 is applied to the entire surface as an insulating film between the eyebrows.
After forming contact holes 618 and 619 for the source and drain, metal vapor deposition and metal patterning are performed to form electrodes 620 and 619 for the source and drain.
By forming 621, an N-channel type MO3) transistor having an LDD structure with a gradient concentration profile is completed (FIG. 1(j)).

In the above embodiment, the case of forming an N-type MO3) transistor was described, but the conductivity type of each layer is reversed, and a P-type MO3) transistor is formed.
When forming a type MO3) transistor, also 0MO
It goes without saying that this embodiment can be easily applied to the case where NMO3 and PMO8 are simultaneously formed in the 8 structure.

(Effects of the Invention) As described above in detail, according to the present invention, a polysilicon gate electrode having a trapezoidal cross section is formed by selective oxidation of a polysilicon film using the mask layer left in the gate region as a mask. The source/drain diffusion layers were formed by ion implantation using the mask layer as a mask, and then after the mask layer was removed, a low concentration layer was formed under the eaves using the eaves on both sides of the gate electrode. ■ Minimum It is possible to form a transistor with an LDD structure that has the same source-drain diffusion layer spacing as the resolution dimension ■ A low-concentration layer with a graded concentration profile makes the electric field distribution uniform in the low-concentration layer without sacrificing drain current. It has the feature that it can be made low with a high [1] MO8@product circuit. This effect will be explained in detail below with reference to the above embodiments.

(1) Regarding the miniaturization of gates, Figure 3 shows an enlarged view of the vicinity of the gate during As ion implantation in Figure 1 (g)! ! Shown in gJ. In FIG. 3, when the film thickness of the Si3N4 film pattern 609 placed on the gate region is thin, data close to the right angle of θl#80 to 85° is obtained as shown in the figure, but in the case of the above-mentioned example. By increasing the film thickness to 3000 mm, data of θ=5° to 10° was obtained under the oxidation conditions shown in this example.

Therefore, Si and N serve as a mask during As ion implantation.

The convergence W of the film pattern 609 is W2=1.0 pm-2X0.3μm+2Xo, 3
・Co5 (5° ~ lO°) μm = Q, 998 ~ 0.9
90 μm #1.0 μm In other words, approximately 1.0 μm is obtained. This indicates that the distance between the N''' source and N9 drain indicated by W3 in the figure is 1.0 μm, which is almost the same as the 7-otolithography resolution dimension.

That is, in the first conventional example, only an NMO8) transistor with an N+ source/N+ drain spacing of the minimum resolution dimension of photolithography + twice the sidefall width was obtained, whereas according to the present invention, the source/N+ drain spacing is An NMOS transistor whose drain spacing is the same as the photolithographic resolution dimension is obtained. This can greatly contribute to the degree of integration of the device.

(2) Low concentration i (N offset layer) FIG. 4 shows an enlarged view of the vicinity of the gate when forming the N offset layer in FIG. 1(i). Using the thickness of the eaves of the gate electrode 612, an acceleration voltage of 100 keV is applied.

When the implantation dose is 1.5 x 101s particles/d, the drain offset layer 616 with a sloped concentration profile is 0.0 mm from the end of the drain diffusion layer 615 as indicated by W4 in the figure.
．． It is formed up to a position of 15 μm. In addition, by increasing the implantation acceleration voltage, the maximum thickness of ff1li (0.3 μm), which is the same as the gate polysilicon thickness, is
) can be controlled.

When we simulated the electric field value for the N offset layer with this gradient concentration profile at a dose that gives the same drain current, we found that the offset layer has a single profile as shown in Figure 5. It has become clear that a lower and more uniform electric field distribution can be obtained. This made it possible to improve the reliability of transistor characteristics without sacrificing the performance of the device.

Furthermore, according to the present invention, in contrast to the conventional second and third examples, (1) forming source/drain diffusion layers by ion implantation using a mask layer as a mask, and then removing the mask layer; In the above, since a low concentration layer is formed by ion implantation on the second day, both layers can be controlled independently, and therefore the electric field strength can be optimized without affecting the formation of the source/drain diffusion layer. Not only can the characteristics be easily controlled, but as a result, fine transistors can be formed.

(2) Since the tapered surface of the side surface of the gate electrode is made steep by high-pressure oxidation, an LDD MOS transistor can be formed without causing an increase in the resistance value of the gate electrode.

This effect can be expected.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing one embodiment of the method for manufacturing a MOS transistor of the present invention, FIG. 2 is a cross-sectional view showing the gate electrode shape in one embodiment, and FIG. 3 is an As ion ion in one embodiment. FIG. 4 is an enlarged view of the vicinity of the gate during implantation, FIG. 4 is an enlarged view of the vicinity of the gate when forming the N offset layer in one example, and FIG. 5 is a characteristic diagram showing the simulation results of the electric field value in the N offset layer. , Fig. 6 is a schematic diagram of a basic N-channel type MOS transistor, Fig. 7 is a diagram of the electric field distribution in the channel of a MOS)-transistor in a pentode operating state, and Fig. 8 is a diagram of the first conventional manufacturing method. FIG. 9 is a cross-sectional view of the essential parts of a transistor according to the first conventional example, and FIG. 10 shows the relationship between the concentration of the N- layer and the electric field in the N- layer and the N+ drain layer. Characteristic diagram shown,
FIG. 11 is a cross-sectional view showing a conventional double-diffused drain structure.
FIG. 12 is a process sectional view showing a second example of the conventional manufacturing method, and FIG. 13 is a process sectional view showing a third example of the conventional manufacturing method. 601...Silicon substrate, 604...Gate oxide film, 605...Polysilicon film, 607...Si3N
4 films, 609...Si3N4M pattern, 610...
・Oxide film, 612...Polysilicon gate electrode, 61
4,615...source/drain N+ layer, 616...
・N offset layer. Fig. 1 71S-Complete light - "Understanding the 8th figure A of the punishment-1" and the 1st column of the craftsman's 1st column 8th figure 1---- N-Layer 1-----------4---- r) Nirain y1 fork and electric spear, Figure 10; /I Ryouta's Third Da'' Figure 13

Claims (1)

[Claims] (a) a step of forming a gate insulating oxide film on the surface of a semiconductor substrate; (b) a step of forming a polysilicon film for forming a gate electrode on the gate insulating oxide film; (c) forming a mask layer on the polysilicon film and selectively leaving this mask layer only on the gate region; and (d) using the mask layer remaining on the gate region as a mask, applying a high pressure to the polysilicon film. By oxidizing with oxidation method,
A step of forming a gate electrode with a trapezoidal cross section under the mask layer using the remaining polysilicon film, and converting all other polysilicon films to oxide films, and (e) removing unnecessary parts other than the gate electrode part, including the converted oxide film. (f) Then, using the mask layer in the gate region as a mask, impurity ions are implanted to form source/drain diffusion layers in the substrate on both sides of the gate electrode; g) Thereafter, by removing the oxide film and implanting impurity ions over the entire surface, a low concentration layer is formed in the substrate under both sides of the trapezoidal gate electrode to be connected to the source/drain diffusion layer. A method for manufacturing a MOS transistor, comprising the steps of: