JPH0818042A - Method for manufacturing mos transistor - Google Patents
Method for manufacturing mos transistorInfo
- Publication number
- JPH0818042A JPH0818042A JP6148856A JP14885694A JPH0818042A JP H0818042 A JPH0818042 A JP H0818042A JP 6148856 A JP6148856 A JP 6148856A JP 14885694 A JP14885694 A JP 14885694A JP H0818042 A JPH0818042 A JP H0818042A
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- recess
- layer
- drain
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ＭＯＳトランジスタ
の製造方法に関し、さらに詳しくは、ゲート電極及びゲ
ート酸化膜を半導体基板に埋め込む構造のＭＯＳトラン
ジスタの製造方法に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor, and more particularly to a method for manufacturing a MOS transistor having a structure in which a gate electrode and a gate oxide film are embedded in a semiconductor substrate.
【０００２】[0002]
【従来の技術】従来、この種のＭＯＳトランジスタとし
ては、図６に示すように簡単な構造のものが知られてい
る。同図中１はシリコン基板であり、このシリコン基板
１の表面にゲート酸化膜２を介してゲート電極３が形成
され、このゲート電極３の両脇にソース領域４及びドレ
イン領域５が形成されている。しかし、このようなトラ
ンジスタでは、ゲート長が短くなるに従い、横方向電界
が大きくなり、ドレイン近傍でのホットキャリア発生
や、しきい値電圧（Ｖｔｈ）の低下をはじめとするショ
ートチャネル効果が生じる。このため、その対策とし
て、図４及び図５に示すようなＬＤＤ構造のＭＯＳトラ
ンジスタがある。このＬＤＤ構造は、ゲート電極３をマ
スクにイオン注入して形成した不純物低濃度領域７と、
ゲート電極の側壁にサイドウォール６形成し、これをマ
スクとしてイオン注入を行ってソース領域４とドレイン
領域５とを形成したものである。このように、ゲート電
極３とソース・ドレイン領域との間に、ソース・ドレイ
ン領域に比較し不純物濃度の低い低濃度領域５を形成す
ることにより、ドレイン近傍の電界強度を小さくしよう
とするものである。2. Description of the Related Art Conventionally, as this type of MOS transistor, a MOS transistor having a simple structure as shown in FIG. 6 is known. In the figure, reference numeral 1 denotes a silicon substrate. A gate electrode 3 is formed on the surface of the silicon substrate 1 via a gate oxide film 2, and a source region 4 and a drain region 5 are formed on both sides of the gate electrode 3. There is. However, in such a transistor, as the gate length becomes shorter, the lateral electric field becomes larger, and hot channel generation near the drain and a short channel effect such as a decrease in threshold voltage (Vth) occur. Therefore, as a countermeasure against this, there is a MOS transistor having an LDD structure as shown in FIGS. This LDD structure has a low impurity concentration region 7 formed by ion implantation using the gate electrode 3 as a mask,
The sidewall 6 is formed on the sidewall of the gate electrode, and the source region 4 and the drain region 5 are formed by performing ion implantation using the sidewall 6 as a mask. Thus, by forming the low concentration region 5 having a lower impurity concentration than the source / drain regions between the gate electrode 3 and the source / drain regions, the electric field strength near the drain is reduced. is there.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のＭＯＳトランジスタにあっては、構造が複雑
であるため、ＬＤＤ領域（低濃度領域）の形成や、サイ
ドウォールの形成などの工程が必要となり、特に各領域
を形成するためのイオン注入用のマスクをそれぞれの形
成工程に応じて形成しなくてはならず、工程数が多くな
る問題があった。また、ＬＤＤ構造のＭＯＳトランジス
タは、ゲート電極の側壁にサイドウォールを形成するた
め、装置が大きくなる問題がある。さらに、サイドウォ
ールを形成するには、ゲート電極３をパターニングした
後に、ＳｉＯ2系の絶縁膜をＣＶＤ法にて全面に堆積さ
せた後、ゲート電極３の側壁のみにこの絶縁膜が残るよ
うにエッチバックを行う必要があるため、エッチバック
の条件によりサイドウォール幅ひいてはＬＤＤ領域幅が
微妙に変化する問題がある。However, since such a conventional MOS transistor has a complicated structure, steps such as formation of LDD regions (low concentration regions) and formation of sidewalls are required. Therefore, in particular, an ion implantation mask for forming each region must be formed in accordance with each forming step, and there is a problem that the number of steps increases. In addition, the LDD structure MOS transistor has a problem that the device becomes large because the sidewall is formed on the side wall of the gate electrode. Further, in order to form the side wall, after patterning the gate electrode 3, a SiO 2 -based insulating film is deposited on the entire surface by the CVD method, and the insulating film is left only on the side wall of the gate electrode 3. Since it is necessary to perform etch back, there is a problem that the sidewall width, and thus the LDD region width, slightly changes depending on the etch back conditions.
【０００４】この発明が解決しようとする課題は、小型
でしかもパンチスルーを抑制でき、製造工程数が少ない
ＭＯＳトランジスタの製造方法を得るにはどのような手
段を講じればよいかという点にある。The problem to be solved by the present invention is what kind of means should be taken to obtain a method for manufacturing a MOS transistor which is small in size, can suppress punch-through, and has a small number of manufacturing steps.
【０００５】[0005]
【課題を解決するための手段】そこで、この発明は、半
導体基体の表面にゲート幅の凹部を形成する工程と、凹
部の内側面に沿って薄い絶縁膜層を形成する工程と、そ
の凹部にゲート電極材料を充填する工程と、半導体基体
の該凹部を挟む部分の、表層に不純物濃度の高いソース
・ドレインを形成し、該ソース・ドレインの下層に不純
物濃度の低い低濃度層を形成する工程とを備えること
を、その解決手段としている。また、前記絶縁膜層の形
成方法は、半導体基体表面に沿ってＣＶＤ法にてＳｉＯ
2膜を堆積させた後、エッチバックを行って該凹部の側
壁のみに該ＳｉＯ2膜を残し、次いで熱酸化を行って該
凹部の底面に酸化膜を形成することを特徴としている。
さらに、低濃度層の下端がチャネル形成位置と略同じ深
さに位置することを特徴としている。Therefore, according to the present invention, a step of forming a recess having a gate width on the surface of a semiconductor substrate, a step of forming a thin insulating film layer along the inner side surface of the recess, and A step of filling the gate electrode material, and a step of forming a source / drain having a high impurity concentration in a surface layer and a low concentration layer having a low impurity concentration in a lower layer of the source / drain in a portion sandwiching the recess of the semiconductor substrate. The solution is to have and. Further, the insulating film layer is formed by CVD along the surface of the semiconductor substrate by the SiO method.
After depositing the two films, etching back is performed to leave the SiO 2 film only on the sidewalls of the recess, and then thermal oxidation is performed to form an oxide film on the bottom surface of the recess.
Further, it is characterized in that the lower end of the low-concentration layer is located at substantially the same depth as the channel formation position.
【０００６】[0006]
【作用】この発明においては、凹部内にゲート電極及び
ゲート酸化膜を埋め込むことにより、ゲート印加電圧に
より形成されたチャネルと接するソース・ドレイン領域
が不純物濃度の低い部分となり、ドレイン近傍の電界強
度を小さくすることができる。このように、低濃度層の
ジャンクション深さが、チャネル形成位置と略同じ深さ
になるため、空乏層の広がりを抑えることができると共
に、例えばＮチャネルＭＯＳトランジスタの場合Ｐ領域
とのジャンクション部分が低濃度層だけであるため、ソ
ース・ドレイン領域（高濃度層）がＰ領域と接する従来
型のＭＯＳトランジスタに比較して、空乏層の発生その
ものを抑えることができ、パンチスルーを抑制する作用
を奏する。また、凹部の形成工程とゲート電極及びゲー
ト酸化膜の埋め込み工程で形成できるため、工程数を削
減することが可能となる。According to the present invention, by embedding the gate electrode and the gate oxide film in the recess, the source / drain regions in contact with the channel formed by the gate applied voltage have a low impurity concentration, and the electric field strength near the drain is reduced. Can be made smaller. In this way, the junction depth of the low-concentration layer becomes substantially the same as the channel formation position, so that the depletion layer can be suppressed from spreading and, for example, in the case of an N-channel MOS transistor, the junction portion with the P region is formed. Since only the low-concentration layer is formed, the generation of the depletion layer itself can be suppressed and punch-through can be suppressed as compared with the conventional MOS transistor in which the source / drain region (high-concentration layer) is in contact with the P region. Play. Further, since it can be formed in the step of forming the recess and the step of filling the gate electrode and the gate oxide film, the number of steps can be reduced.
【０００７】[0007]
【実施例】以下、この発明に係るＭＯＳトランジスタの
製造方法の詳細を図面に示す実施例に基づいて説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for manufacturing a MOS transistor according to the present invention will be described below with reference to the embodiments shown in the drawings.
【０００８】まず、図１（Ａ）に示すように、ｐ型のシ
リコン基板１の表面に、リソグラフィー技術及び異方性
エッチング技術を用いて、ゲート長に相当する幅で且つ
ソース・ドレインのジャンクション深さ程度の深さの凹
部１２を形成する。First, as shown in FIG. 1A, a source / drain junction having a width corresponding to a gate length is formed on the surface of a p-type silicon substrate 1 by using a lithography technique and an anisotropic etching technique. The recess 12 having a depth of about the depth is formed.
【０００９】次に、ゲート酸化膜及び、ゲート電極とソ
ース・ドレイン領域を分離する絶縁層（酸化膜）を形成
する。これらの形成は、図１（Ｂ）に示すように、シリ
コン基板１１の表面及び凹部１２の内側面に熱酸化を施
すことにより、均一の厚さで酸化膜１３を形成すること
ができる。なお、ゲート電極とソース・ドレイン領域と
を高耐圧で絶縁する必要がある場合は、絶縁層の厚さで
全体に酸化膜を堆積させておき（酸化でもよい）、図１
（Ｃ）に示すように、ゲート酸化膜部分の酸化膜層がな
くなるまでエッチバックを行い、図２（Ａ）に示すよう
にゲート酸化膜厚だけ酸化を行い、凹部１２の底面とシ
リコン基板１１の表面に酸化膜１４を形成すればよい。Next, a gate oxide film and an insulating layer (oxide film) for separating the gate electrode from the source / drain regions are formed. In forming these, as shown in FIG. 1B, the oxide film 13 can be formed with a uniform thickness by subjecting the surface of the silicon substrate 11 and the inner surface of the recess 12 to thermal oxidation. When it is necessary to insulate the gate electrode from the source / drain regions with a high breakdown voltage, an oxide film is deposited over the entire thickness of the insulating layer (oxidation may be used), and the structure shown in FIG.
As shown in (C), etching back is performed until the oxide film layer in the gate oxide film portion is removed, and as shown in FIG. 2A, oxidation is performed by the gate oxide film thickness, and the bottom surface of the recess 12 and the silicon substrate 11 are etched. The oxide film 14 may be formed on the surface of the.
【００１０】次に、ゲート電極材料であるポリシリコン
膜１５を全面に堆積させ、図２（Ｂ）に示すように、ゲ
ート電極となる部分だけが残るように、パターニングす
る。その後、このポリシリコン膜１５を注入用マスクと
して用いてｎ型の不純物を低濃度でイオン注入して、酸
化膜１４の深さと同程度の深さまでソース・ドレインの
低濃度層１６、１７を形成する。次に、同じくポリシリ
コン膜１５を注入用マスクとして用いてｎ型の不純物を
高濃度でイオン注入してソース１８とドレイン１９を形
成する。その後、シリコン基板１１の表面より突出する
ポリシリコン膜１５をエッチングすることにより、図２
（Ｃ）に示すようなＭＯＳトランジスタが完成する。Next, a polysilicon film 15 which is a gate electrode material is deposited on the entire surface and is patterned so that only a portion which will be a gate electrode remains, as shown in FIG. 2B. Thereafter, using the polysilicon film 15 as an implantation mask, n-type impurities are ion-implanted at a low concentration to form the low-concentration layers 16 and 17 of the source / drain to a depth approximately equal to the depth of the oxide film 14. To do. Next, similarly using the polysilicon film 15 as an implantation mask, n-type impurities are ion-implanted at a high concentration to form a source 18 and a drain 19. After that, by etching the polysilicon film 15 protruding from the surface of the silicon substrate 11, as shown in FIG.
A MOS transistor as shown in (C) is completed.
【００１１】このようにして形成されたＭＯＳトランジ
スタは、図３に示すように、ゲート電極としてのポリシ
リコン膜１５に電圧を印加することにより、ゲート酸化
膜（酸化膜１４）の下に反転層領域が形成される。この
チャネルは、ソース・ドレイン部分の低濃度層１６、１
７に接するため、従来のｎ型ＭＯＳトランジスタと全く
同じ動作をする。そして、電流の経路は、ソース１８→
ソース側の低濃度層１６→チャネル領域→ドレイン側の
低濃度層１７→ドレイン１９となり、従来のＬＤＤ構造
をもつＭＯＳトランジスタと同じであり、ドレイン側の
低濃度層１７で電界強度を緩和することができ、インパ
クトイオン化等のショートチャネル効果を抑えることが
できる。In the MOS transistor thus formed, as shown in FIG. 3, by applying a voltage to the polysilicon film 15 as a gate electrode, an inversion layer is formed under the gate oxide film (oxide film 14). A region is formed. This channel is formed by the low concentration layers 16 and 1 in the source / drain portions.
Since it is in contact with 7, it operates exactly the same as a conventional n-type MOS transistor. The current path is the source 18 →
The source side low concentration layer 16 → the channel region → the drain side low concentration layer 17 → the drain 19, which is the same as the conventional MOS transistor having the LDD structure, and the drain side low concentration layer 17 relaxes the electric field strength. Therefore, the short channel effect such as impact ionization can be suppressed.
【００１２】また、低濃度層１６、１７のジャンクショ
ン深さが、チャネル形成位置と略同じ深さにあること
は、図４に示すような従来型のＭＯＳトランジスタのシ
ャロー（浅い）ジャンクション構造と同じ（またはそれ
以上）に空乏層の広がりを抑えることができるととも
に、ｐ領域（ｎチャネルＭＯＳの場合）とのジャンクシ
ョン部分が低濃度層だけであるため、図４及び図５に示
すような高濃度（ｎ+）の領域がｐ領域と接している従
来型のＭＯＳトランジスタに比較して、空乏層の発生そ
のものを抑えることができ、パンチスルーを抑止する作
用がある。図３〜図５に示したＭＯＳトランジスタのパ
ンチスルーの起こり易さを比較すると、図５＞図４＞図
３の関係となり、本実施例のＭＯＳトランジスタがパン
チスルーを最も抑えることができる。Further, the fact that the junction depths of the low-concentration layers 16 and 17 are substantially the same as the channel formation position is the same as in the shallow junction structure of the conventional MOS transistor as shown in FIG. (Or more), the depletion layer can be suppressed from spreading, and since the junction with the p region (in the case of n-channel MOS) is only a low concentration layer, the high concentration as shown in FIGS. Compared to a conventional MOS transistor in which the (n + ) region is in contact with the p region, the generation of the depletion layer itself can be suppressed, and punch through can be suppressed. Comparing the susceptibility of punch through of the MOS transistors shown in FIGS. 3 to 5, the relationship of FIG. 5> FIG. 4> FIG. 3 is established, and the MOS transistor of the present embodiment can suppress punch through most.
【００１３】以上、実施例について説明したが、本発明
はこれに限定されるものではなく、構成の要旨に付随す
る各種の設計変更が可能である。すなわち、実質的に、
半導体基体の表面にゲート幅の凹部を形成し、その凹部
の内側面に沿って薄い絶縁膜層を形成し、凹部にゲート
電極材料を充填し、半導体基体の該凹部を挟む部分の、
表層に不純物濃度の高いソース・ドレインを形成し、該
ソース・ドレインの下層に不純物濃度の低い低濃度層を
形成する方法であれば、材料、成膜方法等の変更が可能
である。特に、絶縁膜の形成方法は、ＣＶＤ法によるＳ
ｉＯ2系膜を堆積した後、凹部底面の絶縁膜をエッチン
グし、その底面に熱酸化により薄い絶縁膜を形成しても
よく、または、耐圧をさほど必要としない場合は、凹部
を形成した後、単に熱酸化するだけでもよい。Although the embodiment has been described above, the present invention is not limited to this, and various design changes accompanying the gist of the configuration can be made. That is, in effect,
A recess having a gate width is formed on the surface of the semiconductor substrate, a thin insulating film layer is formed along the inner surface of the recess, and the recess is filled with a gate electrode material.
As long as the source / drain having a high impurity concentration is formed on the surface layer and the low-concentration layer having a low impurity concentration is formed below the source / drain, the material, the film forming method, and the like can be changed. In particular, the method for forming the insulating film is S by the CVD method.
After depositing the iO 2 -based film, the insulating film on the bottom surface of the recess may be etched and a thin insulating film may be formed on the bottom surface by thermal oxidation, or if the breakdown voltage is not so required, after forming the recess. Alternatively, it may be simply thermally oxidized.
【００１４】[0014]
【発明の効果】以上の説明から明らかなように、この発
明によれば、従来のＬＤＤ構造をもつＭＯＳトランジス
タに比べ、サイドウォールがなくてよいため、その分小
型化を図ることができる。このように、サイドウォール
の形成が省略できるため、工程数を少なくする効果を奏
する。また、従来のＬＤＤ構造のＭＯＳトランジスタに
比較し、パンチスルーを抑制できる効果を奏する。As is apparent from the above description, according to the present invention, the side wall is not necessary as compared with the conventional MOS transistor having the LDD structure, and therefore the size can be reduced accordingly. In this way, the formation of the side wall can be omitted, so that the number of steps can be reduced. Further, as compared with the conventional LDD structure MOS transistor, punch-through can be suppressed.
【図１】（Ａ）〜（Ｃ）は本発明の実施例の工程を示す
断面図。1A to 1C are cross-sectional views showing the steps of an embodiment of the present invention.
【図２】（Ａ）〜（Ｃ）は本発明の実施例の工程を示す
断面図。2A to 2C are cross-sectional views showing a process of an embodiment of the present invention.
【図３】本発明の実施例のＭＯＳトランジスタの説明
図。FIG. 3 is an explanatory diagram of a MOS transistor according to an embodiment of the present invention.
【図４】従来のＭＯＳトランジスタの説明図。FIG. 4 is an explanatory diagram of a conventional MOS transistor.
【図５】従来のＭＯＳトランジスタの説明図。FIG. 5 is an explanatory diagram of a conventional MOS transistor.
【図６】従来のＭＯＳトランジスタの断面図。FIG. 6 is a sectional view of a conventional MOS transistor.
１１…シリコン基板 １２…凹部 １３…酸化膜 １４…酸化膜 １５…ポリシリコン膜 １６、１７…低濃度層 １８…ソース １９…ドレイン 11 ... Silicon substrate 12 ... Recess 13 ... Oxide film 14 ... Oxide film 15 ... Polysilicon film 16, 17 ... Low concentration layer 18 ... Source 19 ... Drain
Claims (3)
成する工程と、 該凹部の内側面に沿って薄い絶縁膜層を形成する工程
と、 該凹部にゲート電極材料を充填する工程と、 該半導体基体の該凹部を挟む部分の、表層に不純物濃度
の高いソース・ドレインを形成し、該ソース・ドレイン
の下層に不純物濃度の低い低濃度層を形成する工程と、
を備えることを特徴とするＭＯＳトランジスタの製造方
法。1. A step of forming a recess having a gate width on a surface of a semiconductor substrate, a step of forming a thin insulating film layer along an inner side surface of the recess, and a step of filling the recess with a gate electrode material. A step of forming a source / drain having a high impurity concentration in a surface layer and a low-concentration layer having a low impurity concentration in a lower layer of the source / drain in a portion sandwiching the recess of the semiconductor substrate;
A method of manufacturing a MOS transistor, comprising:
沿ってＣＶＤ法にてＳｉＯ2膜を堆積させた後、エッチ
バックを行って該凹部の側壁のみに該ＳｉＯ2膜を残
し、次いで熱酸化を行って該凹部の底面に酸化膜を形成
してなる請求項１記載のＭＯＳトランジスタの製造方
法。2. The insulating film layer is formed by depositing a SiO 2 film along the surface of the semiconductor substrate by a CVD method and then etching back to leave the SiO 2 film only on the sidewalls of the recess. 2. The method for manufacturing a MOS transistor according to claim 1, wherein an oxide film is formed on the bottom surface of the recess by thermal oxidation.
と略同じ深さに位置する請求項１記載のＭＯＳトランジ
スタの製造方法3. The method of manufacturing a MOS transistor according to claim 1, wherein the lower end of the low concentration layer is located at substantially the same depth as the channel formation position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6148856A JPH0818042A (en) | 1994-06-30 | 1994-06-30 | Method for manufacturing mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6148856A JPH0818042A (en) | 1994-06-30 | 1994-06-30 | Method for manufacturing mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0818042A true JPH0818042A (en) | 1996-01-19 |
Family
ID=15462276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6148856A Pending JPH0818042A (en) | 1994-06-30 | 1994-06-30 | Method for manufacturing mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0818042A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09326489A (en) * | 1996-06-06 | 1997-12-16 | Nec Corp | Mosfet and its manufacturing method |
| KR20000003980A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Transistor of semiconductor devices and method thereof |
| KR100327659B1 (en) * | 1998-12-28 | 2002-08-21 | 주식회사 하이닉스반도체 | Transistor Formation Method of Semiconductor Device |
| JP2007524233A (en) * | 2003-10-10 | 2007-08-23 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Embedded channel flash structure to reduce short channel effects |
| JP2007526651A (en) * | 2004-03-02 | 2007-09-13 | タエ−ボク リー | High breakdown voltage semiconductor device and manufacturing method thereof |
| KR100905174B1 (en) * | 2002-12-30 | 2009-06-29 | 주식회사 하이닉스반도체 | Forming method for semiconductor device |
-
1994
- 1994-06-30 JP JP6148856A patent/JPH0818042A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09326489A (en) * | 1996-06-06 | 1997-12-16 | Nec Corp | Mosfet and its manufacturing method |
| KR20000003980A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Transistor of semiconductor devices and method thereof |
| KR100327659B1 (en) * | 1998-12-28 | 2002-08-21 | 주식회사 하이닉스반도체 | Transistor Formation Method of Semiconductor Device |
| KR100905174B1 (en) * | 2002-12-30 | 2009-06-29 | 주식회사 하이닉스반도체 | Forming method for semiconductor device |
| JP2007524233A (en) * | 2003-10-10 | 2007-08-23 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Embedded channel flash structure to reduce short channel effects |
| JP2007526651A (en) * | 2004-03-02 | 2007-09-13 | タエ−ボク リー | High breakdown voltage semiconductor device and manufacturing method thereof |
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