KR0160917B1 - Method for fabricating self-alignment type mosfet - Google Patents

Abstract

The present invention relates to a method for fabricating a self-aligned MOS transistor, wherein a gate electrode is self-aligned in a channel region to form a source / drain region symmetrically, thereby improving the characteristics of the device and at the same time making a high integration MOS transistor. It's about.

According to the present invention, the process of forming a second opening so that the upper portion of the channel forming region is exposed, and depositing and patterning the polysilicon 17 on the front surface, the polysilicon 17 is formed only inside the second opening 14. This is achieved by minimizing the width of the gate electrode 20 by remaining and forming it as the gate electrode 20 so that the channel region and the gate electrode 20 are self-aligned.

Description

Manufacturing method of self-aligned MOS transistor

1A to 1E are cross-sectional views of a manufacturing process of a MOS transistor having a recessed channel according to the prior art.

2A to 2I are cross-sectional views of a manufacturing process of a MOS transistor having a self-aligning recessed channel according to a first embodiment of the present invention.

3A to 3H illustrate a method of manufacturing a MOS transistor having a self-aligning recessed channel according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 pad oxide film

13 nitride film 14 first opening

15: first oxide film 16,16a: second opening

17 gate oxide film 18 polysilicon

19: second oxide film 20: third oxide film

21: gate electrode 22, 23: source / drain region

24: channel region 25: sidewall oxide film

The present invention relates to a method of manufacturing a self-aligned MOS transistor, and more particularly, to a method of manufacturing a self-aligned MOS transistor suitable for minimizing the width of the gate electrode of the MOS transistor and at the same time self-aligning the gate electrode in a channel region. It's about.

In manufacturing a semiconductor device, when manufacturing a MOS transistor having a gate width of 0.1 μm or less, a shallow lightly doped drain (LDD) junction must be formed to prevent performance degradation of the device. For a 0.1 μm gate width, the LDD junction depth is on the order of 35 nm. In case of 0.1㎛ NMOS, LDD formation of shallow junction depth is solved by low energy arsenic ion implantation or diffusion of impurities into silicon from phosphosilicate glass (PSG), but the resistance is relatively higher than 0.1μm or more devices. .

In addition, the formation of LDD by ion implantation in a PMOS having a gate width of 0.1 μm or less is practically considerably difficult, and many methods have been investigated because of the low uniformity of device characteristics.

A p-type LDD with a shallow junction causes a relatively significant increase in resistance, which severely degrades the current-voltage characteristics of the device. In order to improve device performance, not only the junction depth of the LDD region but also the junction of the source / drain region having a conductivity type of n ⁺ / p ⁺ must be formed shallowly. In this case, heat treatment by simply contacting an existing aluminum metal with an electrode results in an increase in leakage current due to problems such as junction spiking. To solve this, a barrier metal such as WN _X must be used. One of the structures that can solve the problem mentioned here is to selectively sink only the channel region.

1 is a cross-sectional view illustrating a manufacturing process of a MOS transistor according to the prior art, which will be described below with reference to this embodiment. First, referring to FIG. 1A, an oxide film 2 and a nitride film 3 are sequentially formed on an entire surface of a semiconductor substrate 1 on which a field oxide film (not shown) defining an element formation region is formed, and then the nitride film 3 ) Is patterned by photolithography to form a first opening 4 having a predetermined width.

Subsequently, as shown in FIG. 1B, a thick oxide film 5 is formed on the oxide film 2 by thermal oxidation of the semiconductor substrate 1 exposed by the opening 4. At this time, as the semiconductor substrate 1 exposed through the first opening 4 is oxidized, the semiconductor substrate 1 in the channel forming region is concave and oxidized into a convex shape.

next. As shown in FIG. 1C, the oxide film 5 exposed by the opening 4 is etched to the same width as the opening 4 to form a second opening 4a, and then exposed to the exposed semiconductor substrate 1. Ions are implanted with impurities of the first conductivity type. Subsequently, the exposed portion of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 6.

Subsequently, as shown in FIG. 1D, polysilicon 7 is deposited on the entire surface as a metal for forming a gate electrode.

Next, as shown in FIG. 1E, the polysilicon 7 and the nitride film 3 are sequentially patterned by a photolithography method to contact the gate oxide film 6 through the second opening 4a, and the second opening ( The gate electrode 8 and the nitride film pattern 3a having a width wider than that of 4a are formed. Subsequently, the gate electrode 8 is used as an impurity ion implantation mask to ion implant a second conductive impurity on the entire surface, and the semiconductor substrate 1 is heat-treated to define source / drain regions 9a and 9b. Define the area 10. In this case, the gate electrode 8 and the nitride film pattern 3a are patterned using the same etching mask, and the nitride film pattern 3a existing between the gate electrode and the oxide film 5 is formed between the gate electrode 8 and the source / drain ( 9a, 9b) to reduce the capacitance.

Accordingly, the MOS transistor of the prior art as described above has a gate electrode and a source in order to prevent the gate electrode 8 and the source / drain electrodes 9a and 9b from overlapping to generate capacitance between the gate electrode and the source / drain regions. Since the nitride film pattern 3a is interposed between the drain and drain electrodes, there is a limit to substantially reducing the width of the gate electrode 8, thereby making the transistor unsuitable for high integration. For example, the above-described conventional MOS transistor is self-aligned when the impurity profile of the source / drain regions 9a and 9b is self-aligned in the channel region 10 but is misaligned during the photolithography process for forming the gate electrode 8. It may not be.

Therefore, the transistor having the above structure is unsuitable for the ultra-high density semiconductor device because of the overlap of the gate electrode 8 in terms of integration degree as well as in manufacturing problems.

Accordingly, an object of the present invention is to provide a method for manufacturing a MOS transistor capable of high integration of a semiconductor device by minimizing a gate width while self-aligning a gate electrode in a channel region.

In accordance with another aspect of the present invention, a pad opening and a nitride are sequentially formed on a semiconductor substrate, and the first opening is formed so that the top of the channel formation region is exposed by patterning the nitride and pad oxide by photolithography. Forming a thick first oxide film by thermally oxidizing the semiconductor substrate exposed by the opening, and removing the second oxide layer to form a second opening, and a first conductive layer on the semiconductor substrate exposed through the second opening. Implanting a type impurity, forming a gate oxide film on the exposed semiconductor substrate, and then forming polysilicon on the entire surface, and etching the polysilicon to a predetermined thickness to provide a predetermined thickness on the surface of the nitride film. Thermally oxidizing the same to form a second oxide film and removing the same to remove polysilicon from only the inside of the second opening; Thermally oxidizing the surface of the polysilicon to form a third oxide film, removing the nitride film using the third oxide film as an etch mask, and using the third oxide film and polysilicon as an ion implantation mask A process of ion implanting biconductive impurities and a process of defining a gate electrode by etching the side surface of the polysilicon protruding to the side of the width of the third oxide film using the third oxide film as an etching mask and removing the third oxide film. Characterized in that it comprises a.

The second embodiment of the present invention for achieving the above object is to form a pad oxide film and a nitride film on a semiconductor substrate in turn, and then patterning the nitride film and the pad oxide film by photolithography to expose the first opening to expose the upper portion of the channel formation region. Forming a thick first oxide film by thermally oxidizing the semiconductor substrate exposed by the first opening, and removing a portion of the first oxide film in the same width as the first opening to form a second opening having a vertical side surface. And implanting a first conductive impurity into the semiconductor substrate exposed through the second opening, forming a gate oxide film on the exposed semiconductor substrate, and then forming polysilicon on the entire surface of the semiconductor substrate; The polysilicon is etched to a predetermined thickness to leave a predetermined thickness on the surface of the nitride film, and then thermally oxidized to form a second oxide film, which is then removed. A process of remaining polysilicon only in the two openings, thermal oxidation of the surface of the polysilicon to form a third oxide film, removing the nitride film using the third oxide film as an etching mask, and the third And ion implanting a second conductive impurity onto the entire surface by using the oxide film and the polysilicon ion implantation mask, and defining the gate electrode by removing the third oxide film.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; 2A to 2I are cross-sectional views of a manufacturing process of a self-aligned MOS transistor according to the present invention.

Referring to FIG. 2A, a pad oxide film 12 having a thickness of 5 nm to 100 nm is formed on a semiconductor substrate 11 on which a field oxide film (not shown) is formed by a LOCOS method to define a formation region of a semiconductor device. ) Is formed by thermal oxidation or CVD and a nitride film 13 having a thickness of between 50 nm and 300 nm is formed on the pad oxide film 12. Subsequently, in order to define the channel forming region and the gate electrode forming region in the semiconductor substrate 11, the first opening 14 is formed by sequentially etching the nitride layer 13 and the pad oxide layer 12 of the channel forming region by photolithography. . At this time, during the photolithography process, the nitride layer 13 is etched dry, and the pad oxide layer 12 is removed by anisotropic dry etching or wet etching.

Subsequently, as shown in FIG. 2B, the surface of the semiconductor substrate 11 exposed by the first opening 14 is wet oxidized to form a thick first oxide film 15 having a thickness between 10 nm and 100 nm. Form. The first oxide film 15 is performed at a high temperature in order to recess the exposed surface of the semiconductor substrate 11, and the first oxide film 15 is formed into the semiconductor substrate 11 to form the surface of the semiconductor substrate 11. It will have a concave shape.

Next, as shown in FIG. 2C, the first opening 15 grown for the depression of the channel formation region is anisotropically dry etched by about 70 to 80%, and the rest is wet etched to form a second opening having a lower width at the lower side thereof. A thin thermal oxide film (not shown) is formed on the surface of the semiconductor substrate 11 exposed through the second opening 16 to prevent damage to the surface of the substrate. In order to control the threshold voltage, an ion is implanted with impurities of the first conductivity type. When implanting impurities into the channel formation region in the ion implantation step of the channel formation region, non-uniformity of impurity implantation due to the shadow effect caused by the sidewall of the nitride film 13 can be expected. 16, when the second oxide film 15 is formed on the surface of the semiconductor substrate 11 exposed through the nitride film 13, the side of the nitride film 13 is lifted upward and the side surface thereof is inclined, thereby removing the shadow effect.

Subsequently, as shown in FIG. 2D, after implanting impurity ions into the channel formation region, the thin thermal oxide film is wet-etched and removed, and the surface of the exposed semiconductor substrate 11 is thermally oxidized between 3 nm and 10 nm. A gate oxide film 17 having a thickness is formed and polysilicon 18 having a thickness of between 100 nm and 500 nm is deposited on the entire surface. At this time, the edge of the nitride film 13 which is patterned and inclined at the side may remove voids that may occur when polysilicon 18 is deposited.

Next, as shown in FIG. 2E, the polysilicon 18 is dry etched by an etch back process, leaving as thin as possible on the surface of the nitride film 13. This is to remove the size effect caused by anisotropic dry etching of polysilicon and to leave polysilicon having a constant thickness between the recessed channel formation region and the nitride film 13. Subsequently, the polysilicon 18 remaining in a thin thickness on the horizontal line of the nitride film 13 is wet oxidized at a temperature between 800 ° C. and 900 ° C. to form a second oxide film 19, and then wet etched with a hydrofluoric acid solution. To remove it.

Subsequently, as shown in FIG. 2F, the surface of the polysilicon 18 formed in self-alignment with the channel formation region and remaining in the opening 14 is oxidized by dry or wet method at a temperature between 800 ° C and 900 ° C. Oxidation forms a third oxide film 20 having a thickness between about 10 nm and 50 nm.

Next, as shown in FIG. 2G, after wet etching the nitride film 13 using the third oxide film 20 as an etching mask, the third oxide film 20 and the polysilicon 18 are impurity ion implantation masks. The second conductive impurity ion is injected into the front surface.

Subsequently, as shown in FIG. 2H, the gate electrode 21 is defined by anisotropically dry etching the portion protruding from the lower side of the polysilicon 18 to the side using the second oxide film 20 as an etching mask.

Next, as shown in FIG. 2i, heat treatment is performed in the semiconductor substrate 11 electric furnace and rapid thermal annealing (RTA) to form the source / drain regions 22 and 23, and the channel region 24 is defined. The pad oxide film 12 remaining on the surface of the semiconductor substrate 11 is removed, a thick oxide film is formed on the entire surface, and then anisotropic dry etching is performed by an etch back process to form a sidewall insulating film 25 on the side of the gate electrode.

3A through 3H are cross-sectional views illustrating a method of manufacturing a MOS transistor according to another exemplary embodiment of the present invention.

Referring to the manufacturing method of the transistor according to another embodiment of the present invention.

First, referring to FIG. 3A, a pad oxide film having a thickness of 5 nm to 100 nm is formed on a semiconductor substrate 11 on which a field oxide film (not shown) is formed by a LOCOS method to define a formation region of a semiconductor device. (12) is formed by thermal oxidation or CVD and a nitride film 13 having a thickness of between 50 nm and 300 nm is formed on the pad oxide film 12. Subsequently, in order to define the channel forming region and the gate electrode forming region in the semiconductor substrate 11, the first opening 14 is formed by sequentially etching the nitride layer 13 and the pad oxide layer 12 of the channel forming region by photolithography. . At this time, during the photolithography process, the nitride layer 13 is etched dry, and the pad oxide layer 12 is removed by anisotropic dry etching or wet etching.

Subsequently, as shown in FIG. 2B, the surface of the semiconductor substrate 11 exposed by the opening 14 is wet thermally oxidized to form a thick first oxide film 15 having a thickness between 10 nm and 100 nm. do. The first oxide film 15 is performed at a high temperature in order to recess the exposed surface of the semiconductor substrate 11, and the first oxide film 15 is formed into the semiconductor substrate 11 to form the surface of the semiconductor substrate 11. It will have a concave shape.

Next, as shown in FIG. 3C, a portion of the first oxide film 15 is non-dried in a dry manner so that the first oxide film 15 grown for the depression of the channel formation region has the same width as the first opening 14. Isotropic etching to form a second opening (16a) having a straight side of the side and a thin in order to prevent damage to the surface of the substrate during ion implantation on the surface of the semiconductor substrate 11 exposed through the second opening (16a) After the thermal oxide film (not shown) is grown, impurities of the first conductivity type are implanted to control the threshold voltage of the transistor. When implanting impurities into the channel formation region in the ion implantation step of the channel formation region, non-uniformity of impurity implantation due to the shadow effect caused by the sidewall of the nitride film 13 can be expected. When the first oxide film 15 is formed on the surface of the semiconductor substrate 11 exposed through 16a), the side surface is inclined while the nitride film 13 is lifted up, so that such a shadow effect can be removed.

Subsequently, as shown in FIG. 3D, the thin thermal oxide film is wet-etched and removed, and the surface of the exposed semiconductor substrate 11 is thermally oxidized to form a gate oxide film 17 having a thickness of between 3 nm and 10 nm. And depositing polysilicon 18 having a thickness between 100 nm and 500 nm on the front side.

Then, as shown in FIG. 3E, the polysilicon deposited as the polysilicon 18 is dry etched by the etch back process, but remains as thin as possible on the surface of the nitride film 13. This is to eliminate the size effect caused by anisotropic dry etching of polysilicon and to leave the polysilicon 18 having a constant thickness between the recessed channel formation region and the nitride film 13. Subsequently, the polysilicon remaining in a thin thickness on the horizontal line of the surface of the nitride film 13 is wet oxidized at a temperature between 800 ° C. and 900 ° C. to form a second oxide film 19, and then wet etched with a hydrofluoric acid solution to remove it. .

Subsequently, as shown in FIG. 3f, the surface of the polysilicon 18 formed in self-alignment with the channel formation region and remaining in the opening 14 is oxidized by dry or wet method at a temperature between 800 ° C and 900 ° C. Oxidation forms a third oxide film 20 having a thickness between about 10 nm and 50 nm.

Next, as illustrated in FIG. 2G, the nitride electrode 13 is wet-etched using the second oxide film 20 as an etching mask to define the gate electrode 21, and the second oxide film 20 and the gate electrode 21 are formed. ) As the impurity ion implantation mask, the second conductive impurity ion is implanted into the entire surface.

Subsequently, as shown in FIG. 2h, the semiconductor substrate 11 is heat-treated in an electric furnace, and RTA (Rapid Thermal Annealing) forms the source / drain regions 22 and 23 to define the channel region 24. After forming a thick oxide film on the entire surface, anisotropic dry etching is performed by an etch back process to form a sidewall insulating film 25 on the side of the gate electrode.

According to the present invention described above, it is possible to prevent a problem caused by misalignment of the channel region and the gate electrode of the recessed channel transistor of the prior art MOS transistor and a decrease in the operating characteristics of the transistor due to the asymmetry of the source / drain region. In addition, the width of the gate electrode can be finely patterned, and the gate electrodes can be self-aligned to improve the degree of integration of the transistor.

Claims (9)

After the pad oxide film 12 and the nitride film 13 are sequentially formed on the semiconductor substrate 11, the first openings are exposed to pattern the nitride film 13 and the pad oxide film 12 by photolithography to expose the upper portion of the channel formation region. A process of forming a 14 and a process of thermally oxidizing the semiconductor substrate 11 exposed by the opening 14 to form a thick first oxide film 15 and removing the second opening 16. And injecting a first conductive type impurity into the semiconductor substrate 11 exposed through the second opening 16, and forming a gate oxide film 17 on the exposed semiconductor substrate 11. Forming the polysilicon 18 on the substrate, etching the polysilicon 18 to a predetermined thickness, leaving a predetermined thickness on the surface of the nitride film 13, and then thermally oxidizing the second silicon film 19 To form and remove the polysilicon 18 only inside the second opening 16. Forming a third oxide film 20 by thermally oxidizing the surface of the polysilicon 18; removing the nitride film 13 by using the third oxide film 20 as an etching mask; Using the third oxide film 20 and the polysilicon 18 as an ion implantation mask to ion implant a second conductive impurity onto the entire surface, and using the third oxide film 20 as an etching mask Fabricating a self-aligned MOS transistor comprising etching the side surface of the polysilicon 18 protruding laterally than the width of the oxide film and removing the third oxide film 20 to define the gate electrode 21. Way. The method of claim 1, wherein the nitride film (13) is dry etched and the pad oxide film (12) is removed by anisotropic dry etching or wet etching. The method of claim 1, wherein the first oxide film (15) is wet oxidized to form a thickness between 10 nm and 100 nm. 2. The self-aligned MOS transistor of claim 1, wherein the etching process of the first oxide layer 15 to form the second opening 16 comprises anisotropic dry etching of 70 to 80% of the total thickness and wet etching of the rest. Manufacturing method. The self-aligned MOS of claim 1, further comprising forming a thin thermal oxide film to prevent the surface of the semiconductor substrate 11 from being damaged during the first conductivity type impurity ion implantation process. Method for manufacturing a transistor. The method of manufacturing a self-aligned MOS transistor according to claim 1, wherein the polysilicon (18) is etched by anisotropic dry etching during protruding side etching. The method of manufacturing a self-aligned MOS transistor according to claim 1, wherein the first oxide film (15) is formed to a thickness such that a portion of the side nitride film (13) of the first opening (14) can be sufficiently lifted. After the pad oxide film 12 and the nitride film 13 are sequentially formed on the semiconductor substrate 11, the first openings are exposed to pattern the nitride film 13 and the pad oxide film 12 by photolithography to expose the upper portion of the channel formation region. (14) forming a thick first oxide film (15) by thermal oxidation of the semiconductor substrate (11) exposed by the opening (14), and removing a portion of the same width as the first opening (14). Forming a second opening 16a having vertical sides, injecting first conductive impurities into the semiconductor substrate 11 exposed through the second opening 16a, and exposing the exposed semiconductor substrate. Forming a polysilicon 18 on the entire surface after forming the gate oxide film 17 on the front surface; and etching the polysilicon 18 to a predetermined thickness to provide a predetermined thickness on the surface of the nitride film 13 After the thickness remains, it is thermally oxidized to form a second oxide film 19 and And the process of leaving the polysilicon 18 only inside the second opening 16a, thermally oxidizing the surface of the polysilicon 18 to form a third oxide film 20, and the third oxide film ( 20) removing the nitride film 13 using the etching mask, ion implanting a second conductive impurity onto the entire surface using the third oxide film 20 and the polysilicon 18 ion implantation mask, And removing the third oxide film (20) to define a gate electrode (21). The method of claim 8, wherein the first oxide film (15) is patterned by anisotropic dry etching.