KR0144882B1 - Method of manufacturing double-diffusion MOS field transistor - Google Patents

Abstract

A novel method of manufacturing a double-diffusion MOS field transistor is disclosed. After the epitaxial layer of the first conductive type is formed on the semiconductor substrate of the first conductive type, a plurality of gates are formed therebetween with a gate oxide film interposed thereon and capped with the first insulating layer. After forming the body region of the second conductivity type on the epitaxial layer surface between the gates, the first, second and third material layers are sequentially formed on the resultant. The third material layer is etched until the second material layer is exposed, and the second material layer is etched using the remaining third material layer as a mask. After removing the third material layer, the first material layer is etched using the remaining second material layer as a mask. The first material layer is etched using the gate and the remaining second material layer as a mask. A source region of the first conductivity type is formed using the gate and the remaining second and first material layers as masks. An oxide film is formed on the source region by performing a thermal oxidation process using the remaining first material layer as a mask. After removing the first material layer, an impurity region of the second conductivity type for body contact is formed using the oxide film as a mask. In a simplified process, self-aligned double-diffusion MOS field transistors can be implemented.

Description

Method of manufacturing double-diffusion MOS field transistor (DMOS)

1A to 1D are cross-sectional views illustrating a method of manufacturing a DMOS transistor by a conventional method.

2A to 2F are cross-sectional views illustrating a method of manufacturing a DMOS transistor according to the present invention.

* Explanation of symbols for the main parts of the drawings

101,201: semiconductor substrate 102: epitaxial layer

103,202 gate oxide film 104,203 gate

105: first insulating layer 106: P ^- body region

107,108,109: First, second and third material layers 110: N ⁺ source region

111: spacer 112: P-type region

115: P ⁺ region 116: second insulating layer

117,208: First metal pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a double diffused metal oxide semiconductor field effect transistor (hereinafter referred to as a DMOS transistor).

Recently, the trend of semiconductor technology is to integrate power semiconductor devices with high density. To this end, it is necessary to provide a critical alignment of the very small geometry of the device conductive regions. Thus, a separate masking step for stringent critical alignment has been used, which not only lowers yield, but also adds manufacturing time and cost. In conventional DMOS transistors, six or more masking steps are required to achieve high resolution.

U.S. Patent No. 4,716,126 discloses a method of simplifying a method of manufacturing a high density DMOS transistor having a self-aligning shape and eliminating a high resolution masking step. A method of manufacturing the above-described DMOS transistor will be described with reference to FIGS. 1A to 1D.

Referring to FIG. 1A, an N ⁻ type epitaxial layer 201 is grown on an N ⁺ type semiconductor substrate (not shown), and thereafter, a gate oxide film 202, a polysilicon gate 203, and The first oxide film 204 is formed in sequence. Subsequently, a first masking process is performed to sequentially etch the first oxide film 204, the gate 203, and the gate oxide film 202, thereby opening the first window 213 between the gate regions. Next, after ion implantation of nitrogen (N ₂ ) on the resultant product, a high temperature heat treatment step is performed. As a result, the ion implanted nitrogen acts as an retardant or inhibitor. Subsequently, a thermal oxidation process is performed on the resultant product. At this time, while the oxide is growing on the vertical sidewall 211 of the gate region, the growth of the oxide is suppressed due to the ion implanted nitrogen in the exposed substrate surface of the first window portion 213. As a result, a relatively thick second oxide film 205 is formed on each sidewall 211 of the gate region, and a very thin pad oxide film 212 is formed on the exposed surface of the first window portion 213. Next, P-type impurities such as boron (B) are ion-implanted to form a P ⁻ region on the surface of the first window portion 213.

Referring to FIG. 1B, after the silicon nitride film 206 is formed on the resultant, a second masking process is performed to etch the silicon nitride film 206 to open the second window 214. Subsequently, P-type impurities such as boron (B) are ion-implanted through the second window 214 to form a P ⁺ region.

Referring to FIG. 1C, a thermal oxidation process is performed using the silicon nitride film 206 as an anti-oxidation mask. As a result, a localized oxide plug 207 is formed on top of the P + region, and the P ⁻ and P ⁺ regions are further diffused into the substrate 201. Subsequently, after the silicon nitride film 206 is removed, an N ⁺ source region is formed by a self-aligning method.

Referring to FIG. 1D, the oxide plug 207 is removed in a third masking process, and an etching process for the gate contact G and the source contact S is performed. Subsequently, after the metal layer is formed on the resultant, the metal layer is patterned by a fourth masking process to form a first metal pattern 208 on the gate contact G and the source contact S. Referring to FIG. Next, a DMOS transistor is manufactured by stacking a passivation layer 209 on the resultant product on which the first metal pattern 208 is formed.

According to the conventional method described above, the masking step of the critical alignment can be eliminated by providing an oxide film that is self-aligned on the sidewall of the polysilicon gate. However, a high concentration of nitrogen ion implantation process is required to form the self-aligned oxide film, and a total of four masking steps are required.

Accordingly, an object of the present invention is to provide a method of manufacturing a self-aligned DMOS transistor that can achieve a more simplified process by reducing the masking step than the conventional method.

The present invention to achieve the above object,

Forming an epitaxial layer of a first conductivity type on the semiconductor substrate of the first conductivity type;

Forming a plurality of gates on the epitaxial layer of the first conductivity type, the plurality of gates having a gate oxide layer interposed therebetween and capped on the first insulating layer;

Forming a body region of a second conductivity type on a surface of the epitaxial layer between the gates;

Sequentially forming first, second and third material layers on the resultant;

Etching the third material layer until the second material layer is exposed;

Etching the second material layer using the remaining third material layer as a mask;

Removing the third material layer;

Etching the first material layer using the remaining second material layer as a mask;

Forming a source region of a first conductivity type by ion implanting impurities of a first conductivity type using the gate and the remaining second and first material layers as masks;

Forming an oxide film on the source region of the first conductivity type by performing a thermal oxidation process using the remaining first material layer as a mask;

Removing the first material layer; And

And ion implanting an impurity of a second conductivity type using the oxide film as a mask to form a second conductivity type impurity region for body contact.

According to an aspect of the present invention, in the etching of the second material layer using the remaining third material layer as a mask, the second material layer is etched until one end of the gate is exposed.

According to another aspect of the present invention, prior to forming the oxide film, forming a spacer on the sidewall of the gate by depositing and anisotropically etching an insulating material on the resultant material of the first conductivity type source region; And forming a second conductivity type impurity region for suppressing bipolar operation by ion implanting impurities of a second conductivity type using the spacer and the remaining first and second material layers as masks.

According to another aspect of the present invention, the first insulating layer and the second material layer are formed of the same material.

The third material layer is preferably formed of a material having an etching rate different from that of the material constituting the second material layer for any anisotropic etching process or isotropic etching process.

According to another aspect of the invention, after the step of forming the impurity region of the second conductivity type, forming a second insulating layer on the resultant; Removing the second insulating layer and the oxide layer at the portion where the gate contact and the source contact are to be formed by a masking process; Forming a metal layer on the resultant; And forming a first metal pattern on the gate contact and the source contact by patterning the metal layer through a masking process.

According to the present invention, not only the high concentration of nitrogen ion implantation process used in the conventional method is required, but also the DMOS transistor can be realized even more improved than the conventional method by only three masking steps.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a DMOS transistor according to the present invention.

2A shows the step of forming an N ⁻ type epitaxial layer 102, a gate 104 and a P ⁻ body region 106. An N ⁻ type epitaxial layer 102 having a thickness of several μm is grown on the high concentration N type, that is, N ⁺ type semiconductor substrate 101. Subsequently, a gate oxide film 103 having a thickness of about 500 GPa is formed on the N ⁻ type epitaxial layer 102 by a thermal oxidation process, and then a conductive layer 104 having a thickness of about 500 GPa is formed thereon, for example, N ⁺ . The stacked polysilicon layer and the first insulating layer 105, for example, an oxide layer, having a thickness of about 5000 kPa are sequentially stacked. Next, a plurality of gates 104 are formed by etching the first insulating layer 105 and the conductive layer 104 in a first masking process for forming a gate. Subsequently, using the gate 104 as an ion implantation mask, P-type impurities such as boron (B) are implanted with an energy of 50 keV and a dose of 5.0E13 / cm ^{2 to form} a P ⁻ body region 106. ) And a drive-in process of about 4 hours at about 1150 ° C. to diffuse and activate the P ⁻ body region 106. In this case, the P ⁻ body region 106 includes a channel region partially overlapping the gate 104.

2B illustrates the steps of forming the first, second and third material layers 107, 108, 19. On the resulting P ^- body region 106, silicon nitride and oxide are sequentially deposited to a thickness of 1500 kPa and 300 kPa, respectively, to form a first material layer 107 and a second material layer 108. Subsequently, by depositing photoresist or polysilicon on the second material layer 108 to form a third material layer 109, the third material may be etched back or polished. The material layer 109 is etched until the top of the second material layer 108 leaks. As a result, the third material layer 109 remains only between the gates 104. Here, the third material layer 109 may be formed of a material having an etching rate different from that of the material constituting the second material layer 108 for any anisotropic etching process or isotropic etching process.

2C illustrates the step of forming the N ⁺ source region 110. Using the remaining third material layer 109 as an etch mask, side etching, that is, undercut etching, of the exposed second material layer 108 is performed until one end of the gate 104 is opened. do. Subsequently, after the third material layer 109 is removed, the first material layer 107 is etched using the remaining second material layer 108 as an etching mask. At this time, the etching of the first material layer 107 is stopped at the end of the second material layer 108. Next, the N ⁺ source region 110 is formed by ion implanting N-type impurities such as arsenic using the gate 104 and the remaining second and first material layers 108 and 107 as ion implantation masks.

2D shows the step of forming the spacer 111 and the P-type impurity region 112. The spacer 111 is formed on the sidewall of the gate 104 by depositing an anisotropic material, for example, an oxide, on the resulting N ⁺ source region 110 and then anisotropically etching the same. In this case, the second material layer 108 and the first insulating layer 105 are over-etched to a point where the height of the spacer 111 is minimized. During this overetch, the second material layer 108 is completely etched due to the thickness difference, and the first insulating layer 105 is an insulator between the gate 104 and the first metal pattern to be formed in a subsequent process. It is left to maintain sufficient thickness to act as. Subsequently, the P-type impurity region 112 is formed by ion implanting P-type impurities such as boron using the spacer 111 and the remaining first and second material layers 107 and 108 as ion implantation masks. By the spacer 111, the P-type impurity region 112 above to effectively suppress the standing parasitic bipolar operation without an increase in the threshold voltage (threshold voltage) of the channel region (113), N ⁺ source region ( 110 is formed only at the bottom.

2E shows the step of forming the P ⁺ impurity region 115. By performing a thermal oxidation process using the remaining first material layer 107 as an anti-oxidation mask, an oxide film 114 having a thickness of about 2500 kV is formed on the N ⁺ source region 110. Subsequently, after removing the first material layer 107, P-type impurities such as boron are implanted with energy of 30 keV and a dose of 5.0E15 / cm ² to form a P ⁺ impurity region 115 for body contact. . Subsequently, a drive-in process is performed to diffuse and activate the P ⁺ impurity region 115.

FIG. 2F illustrates forming the second insulating layer 116 and the first metal pattern 117. The second insulating layer 116 is formed by depositing an insulating material, for example, an oxide, on the resulting P ⁺ impurity region 115. Subsequently, a second masking step for forming the gate contact and the source contact is performed to remove the second insulating layer 116 and the oxide layer 114 at the portions where the contacts are to be formed. Subsequently, after depositing the metal layer on the resultant, the metal layer is patterned by a third masking step for forming the first metal pattern, thereby forming the first metal pattern 117 on the gate contact and the source contact. . As a result of the above process, the DMOS transistor according to the present invention is manufactured.

As described above, according to the present invention, not only the high concentration of nitrogen ion implantation process used in the conventional method is required, but also the DMOS transistor which is more improved than the conventional method can be realized by only three masking steps. In a specific pattern, a contact hole that is self-aligned is formed using a spacer formed on the sidewall of the gate, so that only one photomask can be completed until the first metal pattern is formed. Therefore, it is possible to realize reduction in device characteristic variation and economic benefit by self-alignment.

It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (6)

Forming an epitaxial layer of a first conductivity type on the semiconductor substrate of the first conductivity type; Forming a plurality of gates on the first conductivity type epitaxial layer, the gate oxide film interposed therebetween and capped on the first insulating layer; Forming a body region of a second conductivity type on a surface of the epitaxial layer between the gates; Sequentially forming first, second and third material layers on the resultant; Etching the third material layer until the second material layer is exposed; Etching the second material layer using the remaining third material layer as a mask; Removing the third material layer; Etching the first material layer using the remaining second material layer as a mask; Forming a first conductivity type source region by ion implantation of a first conductivity type impurity using the gate and the remaining second and first material layers as masks; Forming an oxide film on the source region of the first conductivity type by performing a thermal oxidation process using the remaining first material layer as a mask; Removing the first material layer; And ion implanting impurities of a second conductivity type using the oxide film as a mask to form a second conductivity type impurity region for body contact. The method of claim 1, wherein in the etching of the second material layer using the remaining third material layer as a mask, the second material layer is etched until one end of the gate is exposed. Method of manufacturing a double-diffused MOS field transistor. The method of claim 1, further comprising depositing an anisotropic material on the resultant formed source region of the first conductivity type and anisotropically etching the same to form a spacer on the sidewall of the gate before forming the oxide layer. And forming a second conductivity type impurity region for suppressing bipolar operation by ion implantation of a second conductivity type impurity using the spacer and the remaining first and second material layers as masks. Method of manufacturing a double-diffusion MOS field transistor. The method of claim 1, wherein the first insulating layer and the second material layer are formed of the same material. The method of claim 1, wherein the material constituting the third material layer is characterized by using a material having an etching rate different from the material constituting the second material layer for any anisotropic etching process or isotropic etching process. Method of manufacturing a double-diffused MOS field transistor. The method of claim 1, further comprising: forming a second insulating layer on the resultant after forming the second conductivity type impurity region; Removing the second insulating layer and the oxide layer at the portion where the gate contact and the source contact are to be formed by a masking process; Forming a metal layer on the resultant; And forming a first metal pattern on the gate contact and the source contact by patterning the metal layer in a masking process.