JPH04306881A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a fine transistor of high breakdown strength by a method wherein a gate electrode is formed in a groove provided to a semiconductor substrate, and a gate oxide film on the side wall of the groove is formed thicker than that on the base. CONSTITUTION:A groove is provided to a P-type semiconductor substrate 1, and a gate electrode 13 is provided inside the groove. A gate oxide film 11 formed on the side wall of the groove is thicker than that formed on the base of the groove. Source/drainregions are composed of a high concentration N-type diffusion layer 15 and an N well 5. The well 5 is made to slightly overlap the thin gate oxide film formed on the base of the groove. The end of the N well 5 at the thin gate oxide film is separated from the high concentration N-type diffusion layer 15 in the longitudinal direction, whereby a semiconductor device of this design can be enhanced in breakdown strength. Therefore, a gate electrode can be lessened in area. As an N well is located self-aligning with a gate electrode, a transistor which is high in breakdown strength and stable in characteristics can be realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage and a method for manufacturing the same.

0002

2. Description of the Related Art A conventional MOS type high voltage transistor has a structure shown in FIG. 7(c).

A gate oxide film 29 is formed on the P-type semiconductor substrate 20.
, 31, there is a gate electrode 32 therebetween. The gate oxide film is thicker at the ends of the gate electrode and thinner inside. Highly doped N-type diffusion layers 34 for source and drain are formed in the semiconductor substrate 20 outside the gate electrode 32 . An N well 25 is provided to cover the high concentration N type diffusion layer 34. N
Well 25 is formed down to the thin portion of the gate oxide film.

The breakdown voltage of the source and drain is high because the source/drain diffusion layer is covered with a lightly doped N-well and the gate oxide film above the N-well is thick.

Next, a conventional manufacturing method will be explained with reference to FIGS. 5 to 7.

As shown in FIG. 5(a), an oxide film 21 is formed on a P-type semiconductor substrate 20. As shown in FIG. Using the resist 22 as a mask, approximately 1×10 13 cm −2 of phosphorus is implanted into the substrate.

Next, as shown in FIG. 5(b), by removing the resist and performing heat treatment, the phosphorus 24 is diffused, and as shown in FIG. 5(c), the N-well 24 with a depth of several microns is formed.
becomes. The oxide film on the substrate is removed, and an oxide film 26 and a nitride film 27 are formed.

Next, as shown in FIG. 6(a), a nitride film 27 is formed.
is etched into a predetermined shape. Next, by thermal oxidation, a thick field oxide film 28 for element isolation is formed on the substrate without the nitride film, as shown in FIG. 6(b). After removing the nitride film 27 and the oxide film 26, the first gate oxide film 2 is removed.
9 with a thickness of about 1000 Å.

Next, as shown in FIG. 6(c), the resist 3
A portion of the first gate oxide film 29 is removed using 0 as a mask. After removing the resist 30, the substrate is oxidized again, as shown in FIG.
As shown in (a), the second gate oxide film 31 has a thickness of approximately 300 Å.
form.

Next, as shown in FIG. 7(b), polysilicon is deposited and etched into a predetermined shape to form the gate electrode 32. By performing arsenic implantation 33 at a high dose using the gate electrode as a mask and performing heat treatment, a high concentration N-type diffusion layer 34 is obtained as shown in FIG. 7(c).

[0011]

The conventional high voltage transistor described above has the following problems.

First, in order to prevent offset in the IV characteristics of the transistor, the N-well must overlap the thin region of the gate oxide film. However, if this amount of overlap is large, there is a problem that the withstand voltage decreases. In other words, the accuracy of position control at the end of the N well must be high. Therefore, the withstand voltage and current of the transistor become unstable due to misalignment of the mask and instability in the amount of lateral expansion of the N-well due to diffusion.

In order to further ensure a high breakdown voltage, it is necessary to widen the width C of the N-well. This is because when K is small, the depletion layer on the N-well side reaches the heavily doped N-type diffusion layer when voltage is applied, limiting the breakdown voltage. Therefore, there is a problem that the distance between the source and drain of the transistor is large.

Let us estimate the distance between the source and drain high concentration N type diffusion layers. N-well in Figure 7(c)
The distance between N wells (L) is 3 to prevent punch-through.
A thickness of μm or more is required. Considering the breakdown voltage, the distance between the N well and the high concentration N type diffusion layer is required to be 2 μm or more. Therefore, the total is L+C+C=7 μm.

[0015] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that solve the above problems.

[0016]

[Means for Solving the Problems] In order to achieve the above-mentioned object, a semiconductor device according to the present invention includes a semiconductor substrate of one conductivity type, a groove provided in the semiconductor substrate, and a groove formed at the bottom of the groove. a gate insulating film whose film thickness is smaller than that at the side surfaces of the trench; a gate electrode provided in the trench via the gate insulating film; and a trench in the semiconductor substrate adjacent to the trench. A low concentration diffusion layer of an opposite conductivity type provided deeper than the groove, and a high concentration diffusion layer of an opposite conductivity type provided in the low concentration diffusion layer adjacent to the gate electrode and shallower than the groove. It is.

The method for manufacturing a semiconductor device according to the present invention further includes the steps of introducing an impurity of an opposite conductivity type into a semiconductor substrate of one conductivity type, forming a groove in the semiconductor substrate, and performing heat treatment. a step of diffusing the impurity of the opposite conductivity type to form a low concentration diffusion layer of the opposite conductivity type deeper than the groove in the semiconductor substrate adjacent to the groove; and insulating the surface of the semiconductor substrate including the inside of the groove. a step of forming a film; a step of removing the insulating film at the bottom of the trench by anisotropic etching the insulating film, leaving an insulating film on the side surfaces; and a step of forming a gate insulator at the bottom of the trench. a step of forming a film, a step of forming a gate electrode covering at least a bottom portion of the trench, and a highly concentrated diffusion layer of an opposite conductivity type shallower than the trench on the surface of the semiconductor substrate adjacent to the gate electrode. It has a step of forming.

[0018]

[Operation] The position of the gate electrode and the position of the N-well are formed in self-alignment with respect to the groove formed in the substrate.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

(Embodiment 1) FIGS. 1 to 3 are cross-sectional views showing Embodiment 1 of the present invention in the order of steps.

First, the structure of the semiconductor device of the present invention is shown in FIG.
). In the figure, 1 is a P-type semiconductor substrate, 5 is an N-well, 8 is a field oxide film, 11 is a gate oxide film, 13 is a gate electrode, and 15 is a heavily doped N-type diffusion layer. The gate electrode 13 is a groove 1 made in a semiconductor substrate.
It is formed within 4. The gate oxide film 11 consists of a relatively thick groove side portion and a thin bottom portion. Highly doped N-type diffusion layer 15 is formed in a substrate region surrounded by gate electrode 13 and field oxide film 8 . The N well 5 is deeper than the trench and overlaps the edge of the thin gate oxide film at the bottom of the trench.

Next, a method for manufacturing a semiconductor device according to the present invention will be explained. First, as shown in FIG. 1(a), a P-type semiconductor substrate 1
An oxide film 2 having a thickness of about 2000 Å is formed thereon by thermal oxidation.

Next, as shown in FIG. 1(b), phosphorus implantation 3 was performed at an energy of 150 keV and an implantation amount of 1×1013 cm−2.
Do it with Next, although not shown in the drawings, the oxide film 2 is removed into a predetermined shape using a resist as a mask. After removing the resist, the P-type semiconductor substrate 1 is anisotropically etched to a depth of 2 μm using the oxide film 2 as a mask, as shown in FIG. 1(b).
A groove 4 having a width of about 3 μm is formed.

[0024] Next, heat treatment was performed at 1000°C for several hours,
Phosphorus 3 in the substrate is diffused to form an N well 5 shown in FIG. 1(c). During the heat treatment, an oxide film 6 of about 500 Å is formed in the trench. Next, a nitride film 7 is formed in a predetermined shape.

Next, heat treatment is performed for several hours in a 980° C. steam atmosphere to form a field oxide film 8 of about 6000 Å as shown in FIG. 2(a). By removing the nitride film 7 and isotropically etching the oxide film 6, an oxide film 9 with a thickness of about 1000 Å is left on the substrate other than the groove portion.

Next, as shown in FIG. 2(b), the thickness is about 100 mm.
An oxide film 10 having a thickness of 0 Å is formed by chemical vapor deposition under reduced pressure. The total thickness of the oxide film on the substrate other than the groove portion is 2000 Å, including the thermal oxide film of about 1000 Å already on the base.

Next, as shown in FIG. 2(c), the oxide film 10 is removed by anisotropic etching to the extent that the oxide film on the bottom surface of the trench is removed.
remove. Approximately 1
An oxide film of 000 Å remains.

Next, as shown in FIG. 3A, heat treatment is performed in an oxygen atmosphere at 900° C. to form a gate oxide film 11 with a thickness of 300 Å.
form. Next, polysilicon 12 is grown to a thickness of about 1 μm.

Next, as shown in FIG. 3(b), the polysilicon 1
2 is etched into a predetermined shape using a resist or the like as a mask to obtain a gate electrode 13. Next, using the gate electrode 13 and field oxide film 8 as a mask, arsenic implantation 14 is performed at 70 keV.
, 5 x 1015 cm-2. After heat treatment, Figure 3
As shown in (c), a highly doped N-type diffusion layer 15 is obtained.

In Example 1, the distance between the highly doped N-type diffusion layers of the source and drain will be estimated. The N-well-to-N-well distance (L in FIG. 3(c)) needs to be approximately 3 μm or more. The distance between the N-well end and the heavily doped N-type diffusion layer is determined by the margin for alignment of the gate electrode 13 with respect to the groove (
Since A) in FIG. 3(c) is sufficient, approximately 0.5 μm is sufficient. Therefore, the total is L+A+A=4 μm.

On the other hand, in the conventional example, as mentioned earlier, 7μ
m was necessary. This embodiment results in a size reduction of approximately 60%. In addition, since the position of the N-well and the position of the gate electrode are determined in a self-aligned manner with respect to the groove, there is the advantage that the withstand voltage value and current-voltage characteristics are stable without depending on the alignment accuracy of the mask process. have Furthermore, since the diffusion of phosphorus during the heat treatment for forming the N-well proceeds along the sidewalls of the trench, the position of the N-well with respect to the gate oxide film hardly changes even if there are variations in the heat treatment conditions. In other words, the position of the N-well end can also be said to be self-aligned with the groove. This point also contributes to stabilization of transistor characteristics.

(Embodiment 2) FIG. 4 is a cross-sectional view of the process order for explaining a second embodiment of the present invention. In this embodiment, the steps shown in FIGS. 1 to 2 are carried out in the same manner as in the first embodiment.

Next, as shown in FIG. 4(a), a gate oxide film 11 is formed on the bottom of the trench, and a polysilicon film 16 is formed to a thickness of about 2 μm.
Formed by m.

Next, although not shown in the drawings, a resist is applied to flatten the surface and then etched back under conditions where the etching rates of the resist and the polysilicon are approximately equal, thereby flattening the polysilicon surface. Etching is further continued until the polysilicon remains only inside the groove, as shown in FIG. 4(b). The polysilicon inside the groove becomes the gate electrode 17. Next, using the gate electrode and field oxide film as a mask, arsenic implantation 18 was performed at 70 keV and 5 x 1015 cm-
Do it in 2. By performing heat treatment and diffusing arsenic, a high concentration N-type diffusion layer 19 is formed as shown in FIG. 4(c).

In this embodiment, since the gate electrode 17 exists only inside the groove, there is no need to consider the alignment margin between the gate electrode and the groove. Therefore, the distance between the N-well and the heavily doped N-type diffusion layer (B in FIG. 4(c)) may be approximately 0.2 μm. The spacing between the source and drain high concentration N-type diffusion layers is L+B
+B = 3.4μm, 48% compared to the conventional example of 7μm
can be reduced to

In the first and second embodiments described above, the area can be reduced because the lateral distance between the N well and the heavily doped N type diffusion layer is small. In high-voltage transistors, this interval is secured in the lateral direction in order to increase the breakdown voltage, which leads to an increase in area.

On the other hand, in the present invention, the distance between the N well and the high concentration N type diffusion layer is set in the vertical direction. In other words, when a voltage is applied to the drain, the depletion layer extending from the N-well end at the end of the gate oxide film reaches the heavily doped N-type diffusion layer along the sidewall of the trench.

[0038] Therefore, the lateral spacing that was necessary in the conventional example is no longer necessary in the present invention. This point contributes to a significant reduction in area.

Furthermore, by making the groove deeper and forming the N-well deeper, it is possible to increase the distance between the end of the N-well and the heavily doped N-type diffusion layer. Therefore, there is also the advantage that further improvement in breakdown voltage can be realized without increasing the area.

[0040]

As explained above, according to the present invention, the area can be reduced to 40 to 60% of the conventional example. Furthermore, since the positions of the gate electrode and the N-well are formed in a self-aligned manner with respect to the groove formed in the substrate, there is an effect that the withstand voltage and current-voltage characteristics are stable.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in order of steps.

FIG. 2 is a cross-sectional view showing Example 1 of the present invention in order of steps.

FIG. 3 is a cross-sectional view showing Example 1 of the present invention in order of steps.

FIG. 4 is a cross-sectional view showing a second embodiment of the present invention in order of steps.

FIG. 5 is a cross-sectional view showing a conventional example in the order of steps.

FIG. 6 is a cross-sectional view showing a conventional example in the order of steps.

FIG. 7 is a cross-sectional view showing a conventional example in the order of steps.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Oxide film 3. Phosphorus injection 4 groove 5 N well 6 Oxide film 7 Nitride film 8 Field oxide film 9 Oxide film 10 Oxide film 11 Gate oxide film 12 Policy series 13 Gate electrode 14 Arsenic injection 15 High concentration N type diffusion layer 16 Policy series 17 Gate electrode 18 Arsenic injection 19 High concentration N-type diffusion layer 20 P-type semiconductor substrate 21 Oxide film 22 Resist 23 Phosphorus injection 24 Rin 25 N well 26 Oxide film 27 Nitride film 28 Field oxide film 29 First gate oxide film 30 Resist 31 Second gate oxide film 32 Gate electrode 33 Arsenic injection 34 High concentration N type diffusion layer

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, a groove provided in the semiconductor substrate, and a gate insulating film having a thickness smaller at a bottom surface of the groove than at a side surface of the groove; a gate electrode provided in the groove via the gate insulating film; a low concentration diffusion layer of an opposite conductivity type provided deeper than the groove in the semiconductor substrate adjacent to the groove; An insulated gate type semiconductor device comprising: a high concentration diffusion layer of an opposite conductivity type shallower than the groove and provided in the adjacent low concentration diffusion layer. 2. A step of introducing an impurity of an opposite conductivity type into a semiconductor substrate of one conductivity type, a step of forming a groove in the semiconductor substrate, and a heat treatment to diffuse the impurity of the opposite conductivity type into the groove. forming a low concentration diffusion layer of a reverse conductivity type deeper than the groove in the semiconductor substrate adjacent to the groove; forming an insulating film on the surface of the semiconductor substrate including the inside of the groove; A step of removing the insulating film at the bottom of the trench by performing directional etching and leaving an insulating film on the side surfaces, a step of forming a gate insulating film at the bottom of the trench, and a step of forming a gate insulating film at the bottom of the trench; An insulation characterized by comprising the steps of: forming a gate electrode covering the bottom surface; and forming a highly concentrated diffusion layer of an opposite conductivity type shallower than the trench on the surface of the semiconductor substrate adjacent to the gate electrode. A method for manufacturing a gate type semiconductor device.