JP2011049410A - Inverter circuit and logic gate circuit using silicon carbide insulated gate field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic gate circuit device comprising an SiC MISFET whose operating speed can be made fast. <P>SOLUTION: An inverter and a NAND/NOR logic gate circuit comprise an n-channel enhancement type SiC MISFET (22) and n-channel depletion type SiC MISFETs (22, 22b). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inverter circuit and a logic gate circuit configured using silicon carbide insulated gate field effect transistors.

  Silicon carbide (SiC) has excellent physical properties such as a wider band gap, a higher breakdown electric field strength, and a higher electron saturation drift velocity than silicon (Si). Therefore, by using SiC as a starting material, a power semiconductor element having a high breakdown voltage and a low resistance exceeding the limit of Si can be manufactured. Further, SiC has a feature that an insulating layer can be formed by thermal oxidation like Si. From these, it is considered that an insulated gate field effect transistor (hereinafter referred to as a MISFET, typically known as a MOSFET) having a high withstand voltage and a low on-resistance can be realized using a SiC single crystal as a raw material. Research and development is in progress.

  SiC is also known to have excellent transient response characteristics, and can be used in a high frequency region exceeding 100 kHz. A power IC having a high frequency and a high power density that cannot be realized with Si can be manufactured. Such performance is suitable not only for power ICs but also for practical use of logic circuits that require high-speed operation.

  As described above, although SiC MISFETs have superior characteristics as compared with Si elements, there are very few reports on application to logic circuits, and almost no technology at practical level has been introduced. FIG. 18 shows a CMOS inverter circuit which is one of typical examples of logic circuits known so far, and is widely used in the field of Si devices because it can perform high-speed operation with low power consumption.

  Non-Patent Document 1 discloses a development example of a CMOS inverter using SiC MOSFET. An n-channel MOSFET and a p-channel MOSFET are fabricated on an n-type 4H—SiC epitaxial layer formed on an n + -type substrate. Both devices have a channel length of 3 μm, a gate oxide film thickness of 40 nm, a source, The drain region has a dimension of 300 nm. In SiC MISFET, it is said that the on-resistance can be reduced by two orders of magnitude compared to Si MISFET, and reduction of on-resistance is an important factor for speeding up device operation. In this respect, the gate length (or channel length = source / drain region spacing) of the SiC MOS device treated in the non-patent literature is not so short as 3 μm, so it is expected to contribute significantly to reducing the on-resistance of the device. Can not.

  In the MOSFET for SiC CMOS inverter, the gate length (channel length) can be produced only at about 3 μm because it is difficult to use the self-alignment technique in the SiC process. In the SiC process, the temperature of activation annealing performed after impurity ion implantation is higher than that of the Si process (about 1600 ° C.), and the gate oxide film cannot withstand the high temperature treatment. Therefore, the gate oxide film and the gate electrode are implanted. This is because it is formed by a separate mask alignment after the impurity region is formed (non-self-alignment).

“Development of A 4H-SiC CMOS Inverter” Mater. Res. Soc. Symp. Proc. Vol. 911, 2006 (Figure1, Figure4, Figure8)

  The SiC CMOS inverter described in the above-mentioned non-patent document is one of the few application examples to the logic circuit of the SiC MOSFET, but the field mobility of the NMOSFET shown in FIG. 4 and the field mobility of the PMOSFET shown in FIG. From the comparison, the mobility of the PMOSFET is overwhelmingly low. For this reason, if the characteristics of the PMOSFET are made closer to the mobility of the NOMSFET, the device size has to be made extremely large, and there is a problem that a practical logic circuit design cannot be performed. The occurrence of such a phenomenon is unavoidable and inevitable due to the physical properties of SiC, and it is difficult to practically use a CMOS-structured inverter that is commonly used in Si devices. Therefore, in order to realize high-speed operation by making use of the characteristics of SiC, it is an issue to clarify how a logic circuit is configured without using a PMOSFET.

  Factors to be considered in achieving high-speed operation are the reduction of resistance and parasitic capacitance, and the structure of the SiC MISFET to be used is also an issue to be considered.

  The SiC MISFET is said to be capable of lowering the on-resistance by two orders of magnitude than the Si MISFET, and the reduction of the on-resistance is an important factor for speeding up the device operation. A straightforward approach to reducing the on-resistance is to shorten the gate length (= channel length). In general, when manufacturing a MISFET having a short gate length, not only the gate length but also a gate insulating film (oxide film) ) And the thicknesses of the source and drain regions must also be reduced (scaled down). When the gate length of a SiC MISFET having a gate length of 3 μm, a gate oxide film thickness of 40 nm, and a source and drain region thickness of 300 nm is set to 1 μm, the gate oxide film is 13 nm and the source and drain region thicknesses. Is reduced to 100 nm. As a result, the on-resistance is reduced at the point where the gate length is shortened, while the sheet resistance in the source and drain regions, which are the other main components constituting the on-resistance, is increased from 13 kΩ / □ to 20 kΩ / □. Therefore, there is a problem that the effect of reducing the on-resistance due to the shortening of the gate (channel) length is offset. Conversely, if the gate (channel) length is shortened while maintaining a certain amount of thickness in the source and drain regions, the short channel effect occurs and the device threshold voltage ( There was a risk of encountering the problem of Vth) becoming unstable.

  In addition, when the SiC MISFET is to be manufactured, the restriction that the self-alignment technique generally used in the Si MISFET manufacturing process cannot be used is not only disadvantageous for realizing a short gate (channel) length MISFET, Due to the non-self-aligned manufacturing process of mask alignment → electrode patterning, parasitic capacitance is generated at the overlapping portion of the gate electrode and the source / drain regions in the completed device, and this reduction is also a problem to be solved.

In view of the above problems, an object of the present invention is to provide a logic circuit constituted by a SiC MISFET without using a PMOSFET.
It is another object of the present invention to provide a logic circuit configured using a SiC MISFET having a low on-resistance.
A further object of the present invention is to provide a logic circuit configured using a SiC MISFET with reduced parasitic capacitance.

  The present invention has been made in order to achieve the above object, and in accordance with the present invention, an n-channel enhancement type insulated gate field effect transistor (22) having a source, a drain and a gate, and a source and a drain are provided. , An n-channel depletion type insulated gate field effect transistor (21) having a gate, and an input signal (23) and a first power supply potential (1) are respectively connected to the gate and source of the enhancement type insulated gate field effect transistor. 25), a second power supply potential (24) is supplied to the drain of the depletion type insulated gate field effect transistor, and the gate of the depletion type insulated gate field effect transistor and the depletion type insulated gate field effect transistor. The source of the transistor is electrically connected; The drain of the enhancement type insulated gate field effect transistor and the source of the depletion type insulated gate field effect transistor are electrically connected, and an output signal (26) is extracted from the connection point. The insulated gate field effect transistor and the depletion insulated gate field effect transistor are inverter circuits characterized by being formed using a silicon carbide material.

  The present invention has been made to achieve the above object, and according to the second aspect of the present invention, at least one of the enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect transistor is a main one. A substrate (1) including a silicon carbide semiconductor region (2) of one conductivity type having a surface, and the first conductivity type silicon carbide semiconductor region (2) in contact with the main surface and spaced apart from each other Source and drain regions (3D, 4D, 3E, 4E) having a conductivity type opposite to the one conductivity type, and opposing edges of the spaced apart source and drain regions (3D, 4D, 3E, 4E) A first side surface formed on one main surface side of the sandwiched one conductivity type silicon carbide semiconductor region (2) and in contact with the source region (4D, 4E), and a first side surface in contact with the drain region (3D, 3E). Two sides, A recess (bottom surface) which is located at a predetermined depth from the one main surface and is connected to the first and second side surfaces and which is spaced from the source and drain regions (3D, 4D, 3E, 4E). 5D, 5E) and a part of the one main surface that the source and drain regions (3D, 4D, 3E, 4E) are in contact with, and on the first and second side surfaces of the recess (5D, 5E) and Insulating films (6D, 6E) formed on the bottom surface, gate electrodes (7D, 7E) formed on the insulating films (6D, 6E), and source and drain regions (3D, 4D, 3E, 4E) having a source or drain electrode (9 or 10) electrically connected to at least one of them, and adjacent to the bottom surface connecting the source and drain regions (3D, 4D, 3E, 4E) A channel forming region is formed by the silicon carbide semiconductor region. It is an inverter circuit of claim 1, wherein the silicon carbide field effect transistor having a composed recess gate structure.

  The present invention has been made to achieve the above object, and in the enhancement type insulated gate field effect transistor according to claim 3, an insulating film (6E) covering a part of the one main surface is provided. The capacitance relaxation region (12E, 12E) of the one conductivity type is formed in the source / drain regions (3E, 4E) immediately below the gate electrode (7E) formed thereon. It is an inverter circuit.

  The present invention has been made to achieve the above object, and in the depletion type insulated gate field effect transistor according to the present invention, an insulating film (6D) covering a part of the one main surface is provided. 3. The inverter circuit according to claim 2, wherein the one conductivity type capacitance relaxation region (12D) is formed in the drain region (3D) immediately below the gate electrode (7D) formed thereon.

  The present invention has been made to achieve the above object, and the inverter according to claim 5 is characterized in that the inverter circuit is formed on the same substrate. Circuit.

  The present invention has been made to achieve the above object, and according to the present invention, the inverter circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide. The inverter circuit according to claim 1.

The present invention has been made in order to achieve the above object, and the present invention as described in claim 7 includes a substrate (1) including a silicon carbide semiconductor region (2) of one conductivity type having one main surface, A first source / drain region (4E, 3E) having a conductivity type opposite to the one conductivity type formed in the one conductivity type silicon carbide semiconductor region (2) in contact with the main surface and spaced apart from each other; , Formed on one main surface side of the one-conductivity-type silicon carbide semiconductor region (2) sandwiched between opposing edges of the first source and drain regions (4E, 3E) formed apart from each other, A first side surface in contact with the first source region (4E); a second side surface in contact with the first drain region (3E); and the first and second surfaces located at a predetermined depth from the one main surface. A first bottom surface connecting the first source and drain regions (4E, 3E) formed continuously and spaced apart from the two side surfaces; A first recess (5E) comprising the first source and drain regions (4E, 3E) is in contact with a part of the main surface, and the first and second recesses (5E) of the first and second recesses (5E) are covered. A first insulating film (6E) formed on the second side surface and the first bottom surface; a first gate electrode (7E) formed on the first insulating film (6E); A first source, and a first source electrode (10) electrically connected to (4E), on the first bottom surface connecting the first source and drain regions (4E, 3E) An enhancement type insulated gate silicon carbide field effect transistor having a recess gate structure in which a channel forming region is formed by the adjacent silicon carbide semiconductor region portion;
A substrate (1) including a one-conductivity-type silicon carbide semiconductor region (2) having the one main surface, and a single-conductivity-type silicon carbide semiconductor region (2) in contact with the one main surface and spaced apart from each other The second source and drain regions (4D, 3D) of the opposite conductivity type to the one conductivity type formed, and the opposing edges of the second source and drain regions (4D, 3D) formed apart from each other A third side surface that is formed on one main surface side of the one-conductivity-type silicon carbide semiconductor region (2) sandwiched between two layers and is in contact with the second source region (4D); and the second drain region (3D) A fourth side surface in contact with the second source and drain regions (4D, 3D) located at a predetermined depth from the one main surface and connected to the third and fourth side surfaces and spaced apart from each other A second recess (5D) having a second bottom surface to be in contact with the second source and drain regions (4D, 3D). A second insulating film (6D) that covers a part of the one main surface and is formed on the third and fourth side surfaces and the second bottom surface of the second recess (5D); A second gate electrode (7D) formed on the second insulating film (6D) and a second drain electrode (9) electrically connected to the second drain region (3D) A depletion type silicon carbide having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the second bottom surface connecting the second source / drain regions (4D, 3D) An insulated gate field effect transistor;
The first gate electrode and the first source electrode of the enhancement type silicon carbide insulated gate field effect transistor are connected to an input signal and a first power supply potential, respectively, and the second type of the depletion type silicon carbide field effect transistor is The drain electrode is connected to a second power supply potential, the second gate electrode of the depletion type silicon carbide insulated gate field effect transistor is electrically connected to the second source region, and the enhancement type silicon carbide. The first drain region of the insulated gate field effect transistor and the second source region of the depletion type silicon carbide insulated gate field effect transistor are electrically connected, and an output signal is taken out from the connection point (11). It has a recess structure characterized by being configured as follows A silicon hydride insulated gate field effect transistor inverter circuit.

  The present invention has been made to achieve the above object, and according to an eighth aspect of the present invention, there is provided at least one of the enhancement type silicon carbide insulated gate field effect transistor and the depletion type silicon carbide insulated gate field effect transistor. The portions near both ends of the first or second bottom surface are in contact with the thin regions (3a, 3a) of the first or second source / drain regions (4E, 3E, 4D, 3D). A silicon carbide insulated gate field effect transistor inverter circuit having a recessed structure according to claim 7.

  The present invention has been made to achieve the above object, and according to the present invention, the first source / drain region (4E, 3E) or the second source / drain region (4D, 3D) is formed at a first predetermined depth from the one main surface, and the first or second bottom surface is formed at a second predetermined depth from the one main surface, and the enhancement At least one of the silicon carbide field effect transistor and the depletion type silicon carbide field effect transistor is selected such that the second predetermined depth is substantially equal to or shallower than the first predetermined depth, 8. A silicon carbide insulated gate field effect having a recess structure according to claim 7, wherein a channel forming region is constituted by the silicon carbide semiconductor region adjacent to the entire length of the second bottom surface. This is a transistor inverter circuit.

  The present invention has been made to achieve the above object, and in the enhancement type insulated gate field effect transistor according to claim 10, an insulating film (6E) covering a part of the one main surface is provided. 8. The one-conductivity type capacitance relaxation region (12E, 12E) is formed in a source / drain region (3E, 4E) immediately below a gate electrode (7E) formed thereon. It is a silicon carbide insulated gate field effect transistor inverter circuit having a recess structure.

  The present invention has been made to achieve the above object, and according to an eleventh aspect of the present invention, there is provided an insulating film (6D) covering a part of the one main surface in the depletion type insulated gate field effect transistor. 8. The silicon carbide having a recess structure according to claim 7, wherein said one conductivity type capacitance relaxation region (12D) is formed in a drain region (3D) immediately below the gate electrode (7D) formed thereon. It is an insulated gate field effect transistor inverter circuit.

  The present invention has been made to achieve the above object, and according to claim 12, the channel formed in the enhancement type silicon carbide field effect transistor and the depletion type silicon carbide field effect transistor is n. 8. A silicon carbide insulated gate field effect transistor inverter circuit having a recessed structure according to claim 7, wherein the inverter circuit is a type.

  The present invention has been made to achieve the above object, and according to claim 13, a first n-channel enhancement type insulated gate field effect transistor (22b) having a source, a drain and a gate; A second n-channel enhancement type insulated gate field effect transistor (22) having a source, a drain and a gate; and an n-channel depletion type insulated gate field effect transistor (21) having a source, a drain and a gate, The drain of the first enhancement type insulated gate field effect transistor and the source of the second enhancement type insulated gate field effect transistor are electrically connected, and the gate and the depletion of the depletion type insulated gate field effect transistor Type insulated gate field effect And the source of the first enhancement type insulated gate field effect transistor is connected to a first power supply potential (25), and the drain of the depletion type insulated gate field effect transistor is electrically connected to the source of the transistor. Is connected to a second power supply potential (24), and the respective gates of the first and second enhancement type insulated gate field effect transistors are connected to first and second input signals (23b, 23), The drain of the second enhancement type insulated gate field effect transistor and the source of the depletion type insulated gate field effect transistor are electrically connected, and an output signal (26) is extracted from the connection point. The enhancement type insulated gate field effect transistor and the depletion type The insulated gate field effect transistor is a NAND logic gate circuit formed using a silicon carbide material.

  The present invention has been made to achieve the above object, and according to claim 14, the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor are provided. At least one of the substrate (1) including one conductivity type silicon carbide semiconductor region (2) having one principal surface and the one conductivity type silicon carbide semiconductor region (2) in contact with the one principal surface and spaced apart from each other The source and drain regions (4D, 3D, 4E, 3E, 4bE, and 3bE) of the opposite conductivity type to the one conductivity type formed, and the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) formed on one main surface side of the one-conductivity-type silicon carbide semiconductor region (2) sandwiched between opposing edges, and in contact with the source regions (4D, 4E, 4bE). , A second side surface in contact with the drain region (3D, 3E, 3bE), a predetermined depth from the one main surface, and the first side surface and the second side surface are continuously spaced from each other. Recesses (5D, 5E, 5bE) having a bottom surface connecting the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE), and the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) covering a part of the one main surface in contact with the insulating film formed on the first and second side surfaces and the bottom surface of the recess (5D, 5E, 5bE), and on the insulating film The formed gate electrode (7D, 7E, 7bE) and the source or drain electrode (9, or electrically connected to at least one of the source / drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) 10) and the source It consists of a silicon carbide field effect transistor having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the bottom surface connecting drain regions (4D, 3D, 4E, 3E, 4bE, 3bE). 14. The NAND logic gate circuit according to claim 13.

  The present invention has been made to achieve the above object, and according to claim 15, in the first or second enhancement type insulated gate field effect transistor, a part of the one main surface is formed. The one-conductivity type capacitance relaxation regions (12E, 12E, 12bE, 12bE) are formed in the source and drain regions (3E, 4E, 3bE, 4bE) immediately below the gate electrodes (7E, 7bE) formed on the insulating film to be covered. 15. The NAND logic gate circuit according to claim 14, wherein the NAND logic gate circuit is formed.

  The present invention has been made to achieve the above object, and according to the sixteenth aspect of the present invention, the depletion type insulated gate field effect transistor is formed on an insulating film covering a part of the one main surface. 15. The NAND logic gate circuit according to claim 14, wherein the one conductivity type capacitance relaxation region (12D) is formed in the drain region (3D) immediately below the gate electrode (7D) formed.

  The present invention has been made to achieve the above object, and according to a seventeenth aspect of the present invention, the NAND logic gate circuit is formed on the same substrate. NAND logic gate circuit.

  The present invention has been made to achieve the above object, and according to the present invention, the NAND logic gate circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide. 14. The NAND logic gate circuit according to claim 13, wherein:

  The present invention has been made to achieve the above object, and according to claim 19, the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor are provided. 15. At least one of the portions of the bottom surface near both ends is in contact with a thin region (3a, 3a) of the source / drain region (3D, 4D, 3E, 4E, 3bE, 4bE). It is a NAND logic gate circuit of description.

  The present invention has been made to achieve the above object, and according to claim 20, the first source and drain regions (3D, 4D, 3E, 4E, 3bE, 4bE) are arranged on the one main surface. The first and second enhancement type silicon carbide insulated gate field effects are formed at a first predetermined depth from the first main surface and the bottom surface is positioned at a second predetermined depth from the one main surface. At least one of the transistor and the depletion type silicon carbide insulated gate field effect transistor is selected such that the second predetermined depth is substantially equal to or shallower than the first predetermined depth, and is adjacent over the entire length of the bottom surface. 15. The NAND logic gate circuit according to claim 14, wherein a channel forming region is constituted by the silicon carbide semiconductor region portion.

  The present invention has been made to achieve the above object, and according to claim 21, there is provided a first n-channel enhancement type insulated gate field effect transistor (22b) having a source, a drain and a gate; A second n-channel enhancement type insulated gate field effect transistor (22) having a source, a drain and a gate; and an n-channel depletion type insulated gate field effect transistor (21) having a source, a drain and a gate, The source of the first enhancement type insulated gate field effect transistor and the source of the second enhancement type insulated gate field effect transistor are electrically connected, and the connection point is connected to the first power supply potential (25). Before the first enhancement type insulated gate field effect transistor. A drain and the drain of the second enhancement type insulated gate field effect transistor are electrically connected and electrically connected to the gate and source of the depletion type insulated gate field effect transistor, from the connection point thereof An output signal (26) is extracted, the drain of the depletion type insulated gate field effect transistor is connected to a second power supply potential (24), and the first and second enhancement type insulated gate field effect The gates of the transistors are connected to first and second input signals (23b, 23), respectively, and the enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect transistor are made of silicon carbide material. NOR characterized by It is a logic gate circuit.

  The present invention has been made to achieve the above object, and according to a twenty-second aspect of the present invention, there is provided the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistors. At least one of the one conductivity type silicon carbide semiconductor region having one principal surface and the one conductivity type formed in contact with the one principal surface and spaced apart from each other in the one conductivity type silicon carbide semiconductor region Is formed on one main surface side of the one-conductivity-type silicon carbide semiconductor region sandwiched between opposing source and drain regions of the opposite conductivity type and the oppositely formed edges of the source and drain regions, A first side surface in contact with the source region, a second side surface in contact with the drain region, and located at a predetermined depth from the one main surface and continuous with the first and second side surfaces Covering a recessed portion formed of a bottom surface connecting the spaced-apart source and drain regions, a part of the one main surface with which the source and drain regions are in contact, and on the first and second side surfaces of the recessed portion and the An insulating film formed on a bottom surface; a gate electrode formed on the insulating film; and a source or drain electrode electrically connected to at least one of the source and drain regions. The NOR logic gate circuit according to claim 21, comprising a silicon carbide field effect transistor having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the bottom surface connecting the regions. is there.

  The present invention has been made in order to achieve the above object, and according to a twenty-third aspect of the present invention, in the first or second enhancement type insulated gate field effect transistor, a part of the one main surface is formed. 23. The NOR logic gate circuit according to claim 22, wherein the one conductivity type capacitance relaxation region is formed in a source / drain region directly under the gate electrode formed on the insulating film to be covered.

The present invention has been made to achieve the above object, and in the depletion type insulated gate field effect transistor, the present invention is formed on an insulating film covering a part of the one main surface. 23. The NOR logic gate circuit according to claim 22, wherein the one conductivity type capacitance relaxation region is formed in a drain region directly under the gate electrode.

  The present invention has been made to achieve the above object, and according to claim 25, the NOR logic gate circuit is formed on the same substrate. This is a NOR logic gate circuit.

  The present invention has been made to achieve the above object, and according to a twenty-sixth aspect, the NOR logic gate circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide. 22. The NOR logic gate circuit according to claim 21, wherein:

  The present invention has been made to achieve the above object, and according to a twenty-seventh aspect, the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor are provided. 23. The NOR logic gate circuit according to claim 22, wherein at least one portion near both ends of the bottom surface is in contact with a thin region of the source and drain regions.

  The present invention has been made to achieve the above object, wherein the first source and drain regions are formed at a first predetermined depth from the one main surface, and A bottom surface is formed to be located at a second predetermined depth from the one main surface, and the first and second enhancement type silicon carbide insulated gate field effect transistors and the depletion type silicon carbide insulated gate field effect transistor At least one of the second predetermined depth is selected to be substantially equal to or shallower than the first predetermined depth, and a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the entire length of the bottom surface. 23. The NOR logic gate circuit according to claim 22, wherein

The inverter circuit, NAND logic gate circuit, and NOR logic gate circuit of the present invention have the following effects.
That is, since the logic circuit is configured using only the n-channel SiC MISFET, the on-resistance and the parasitic capacitance can be reduced, and higher speed operation can be realized than the CMOS-structured logic circuit.
Also, by adopting SiC MISFET having a recessed gate structure, the thickness of the source and drain regions adjacent to the gate electrode can be selectively made thin or substantially zero, so that the short channel effect can be suppressed, and the short gate length (channel length) Since a SiC MISFET having a low on-resistance can be obtained, the operation speed of the logic circuit is further improved. In addition, since it is not necessary to reduce the thickness of the source and drain regions away from the adjacent portion of the gate electrode, there is no risk of an increase in the sheet resistance of the source and drain regions. Contributes to high-speed operation.
Further, since the capacitance parasitic to the gate electrode can be reduced by forming the capacitance relaxation region, the operation of the logic circuit can be further speeded up.

FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2, showing an inverter circuit device configured using the SiC MISFET to which the first embodiment of the present invention is applied. The top view which shows the inverter circuit device shown in FIG. FIG. 3 is a circuit configuration diagram showing the inverter circuit device shown in FIGS. 1 and 2. The figure which shows the circuit structure which added the parasitic capacitance to the inverter circuit shown in FIG. The figure which shows the circuit structure of the CMOS inverter comprised by SiC. Sectional drawing which shows the inverter circuit device comprised using SiC MISFET to which Embodiment 2 of this invention was applied. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. Process drawing which shows the manufacturing method of the inverter circuit device shown in FIG. The figure which shows the NAND logic gate circuit structure comprised using SiC MISFET to which Embodiment 4 of this invention was applied. Sectional drawing which shows the NAND logic gate circuit device comprised using SiC MISFET to which Embodiment 4 of this invention was applied. The figure which shows the NOR logic gate circuit structure comprised using SiC MISFET to which Embodiment 5 of this invention was applied. Sectional drawing which shows the inverter circuit device comprised using SiC MISFET to which Embodiment 3 of this invention was applied. The figure which shows the circuit structure which shows the conventional CMOS inverter.

EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated in detail based on drawing. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof is omitted unless necessary.
[Embodiment 1]
FIG. 1 and FIG. 2 show the structure of an inverter circuit device configured using the SiC MISFET according to the first embodiment. FIG. 1 is an enlarged sectional view, and FIG. 2 is a plan view thereof (FIG. 1 is a diagram). 2 is a cross-sectional view taken along one-dot chain line). A base having a p-type SiC semiconductor region 2 formed on a SiC substrate 1 is prepared, and an n-channel enhancement type SiC MISFET 22 and a depletion type SiC MISFET 21 are formed in the SiC semiconductor region 2. Each SiC MISFET is adjacent to one main surface in the SiC semiconductor region 2 and is separated and opposed to n + type source, drain regions 4D and 3D (for forming a depletion type SiC MISFET) and 4E and 3E (enhancement type SiC MISFET). Forming) is selectively provided. Since the drain region 3E of the enhancement type SiC MISFET and the source region 4D of the depletion type SiC MISFET are electrically connected, they are formed as an integral region, but may be formed separately. A channel formation scheduled region (a surface region of the semiconductor region 2 sandwiched between the source and drain regions) of the depletion type SiC MISFET is previously doped with an n-type impurity. As a result, the enhancement type SiC MISFET operates normally off, and the depletion SiC MISFET operates normally on. Here, the SiC substrate 1 is either p-type, n-type, or semi-insulating, and the crystal plane is a (0001) Si plane, a (000-1) C plane, or other planes. It may be an azimuth. The p-type semiconductor region 2 is an active layer in which a region constituting the device is formed. For example, the p-type semiconductor region 2 is an epitaxially grown layer having a thickness of 10 μm doped with an impurity concentration of about 5 × 10 ¹⁵ / cm ³ . The impurity concentration of the source / drain regions 4D, 3D, 4E, 3E is about 1 × 10 ²⁰ / cm ³ and the thickness is 250 nm. The separation distance (opposite distance) between the source / drain regions 4D, 3D, 4E, and 3E is 1 μm, and this distance defines the gate length Lg (channel length).

The depletion type SiC MISFET 21 and the enhancement type SiC MISFET 22 include recesses 5D and 5E provided on one main surface side of the semiconductor region 2, and gate electrodes 7D and 6E formed on the gate insulating films 6D and 6E covering the respective recesses. There is a recess gate structure consisting of 7E. That is, the recesses 5D and 5E are formed in the semiconductor region 2 sandwiched between the opposing edges of the source and drain regions 4D and 3D or 4E and 3E (the ends of the source and drain regions on one main surface of the semiconductor region 2). A source formed on one principal surface side, two side surfaces in contact with the source and drain regions 4D, 3D or 4E, 3E, and a source located at a predetermined depth from the one principal surface and continuously spaced from the two side surfaces; The drain region 4D, 3D or 4E, 3E is composed of a bottom surface for connecting. In this example, the recess can be formed with a width of 2 μm and a depth of 150 nm.
As the gate insulating films 6D and 6E, a silicon oxide film can be used, and the thickness thereof is, for example, 13 nm. In FIG. 1, the gate insulating films 6D and 6E have a uniform thickness over the bottom surface and both side surfaces of the recess and the surface of the source and drain regions 3D and 4D or 3E and 4E. However, without being limited thereto, for example, the gate insulating film on a part of the surface of the source / drain regions 4D, 3D or 4E, 3E may be made thicker than that in the recess. Thereby, an increase in capacitance due to an overlap between the gate electrode and the source / drain regions can be suppressed.
For the gate electrodes 7D and 7E, a polysilicon material can be used, and an n-type impurity doped with about 1 × 10 ²⁰ / cm ³ is used.
In the structure of FIG. 1, a part of the source / drain regions 4D, 3D or 4E, 3E immediately below both ends of the recesses 5D, 5E exist as thin regions 3a, 3a (in FIG. 1, the thin region 3a is Each SiC MISFET is labeled at one location, but actually the same structure exists in each of the source region and the drain region (the same applies to FIGS. 6 and 15). Further, the portions of the source / drain regions 4D, 3D or 4E, 3E immediately below the source / drain electrodes 9, 10, 11 are kept relatively thick. As a result, this SiC MISFET has the characteristics that even if the gate length (channel length) is shortened, the short channel effect can be suppressed and the on-resistance can be reduced.

The insulating film 8 is formed on the SiC semiconductor region 2 for electrode / wiring formation, and may be a silicon oxide film. In general, a field insulating film is formed on the surface of the semiconductor region 2 on the substrate 1 prior to the formation of the insulating film 8, but the illustration thereof is omitted here.
The source / drain electrodes 9, 10, 11 are electrically connected to the source / drain regions 4D, 3D or 4E, 3E through contact openings formed in the insulating film 8. As shown in FIG. 2, the contact opening has a quadrangular shape and a size of 2 μm square. Further, the pitch of the contact openings in FIG. 2 is 4 μm. The gate electrodes 7D and 7E are composed of layers different from the source and drain electrodes 9, 10, and 11, but actually, the gate electrodes 7D and 7E extend upward in the plan view of FIG. A gate lead electrode made of the same material as the source and drain electrodes is formed through another contact opening provided in the insulating film 8.

  FIG. 3 is a circuit configuration diagram of the inverter circuit device shown in FIGS. 1 and 2, in which the drain of the enhancement type SiC MISFET 22 and the source of the depletion type SiC MISFET 21 are electrically connected, and the connection point is an output node. 26, the gate and the source of the depletion type SiC MISFET 21 are electrically connected, the source of the enhancement type SiC MISFET 22 is connected to the first power supply potential 25, and the drain of the depletion type SiC MISFET 21 is connected to the second power supply potential. The gate of the enhancement type SiC MISFET 22 is connected to an input node 23 to which an input signal is input. Such a circuit configuration is also called an ED inverter because it is composed of an enhancement type device and a depletion type device. Since the ED inverter is a combination of n-channel devices, it is a single-channel inverter. Enhancement type devices and depletion type devices are usually called switching devices / transistors and load devices / transistors, respectively.

Next, with reference to FIG. 4 and FIG. 5, a high-speed comparison between the ED inverter and the CMOS inverter in the case where the SiC MOSFET using the SiC material is used will be described.
FIG. 4 shows the ED inverter circuit shown in FIG. 3 added with parasitic capacitance added due to the structure of the device. 27 is the gate overlap (overlap) capacitance of the depletion type SiC MOSFET 21, and 28 is the enhancement type SiC MOSFET 22. The gate overlap capacity is shown. FIG. 5 shows a CMOS inverter circuit composed of SiC, in which the gates and drains of an n-channel enhancement type MOSFET (hereinafter referred to as nMOSFET) 22C and a p-channel enhancement type MOSFET (hereinafter referred to as pMOSFET) 21C are electrically connected. The former connection point is connected to the input node 23 to which the input signal is supplied, the latter connection point is connected to the output node 26, the source of the nMOSFET 22C is connected to the first power supply potential 25, and the source of the pMOSFET 21C is the second node. Is connected to the power supply potential 24 of the circuit.
Here, 27C represents the gate overlap capacitance of the pMOSFET 21C, and 28C represents the gate overlap capacitance of the nMOSFET 22C.

First, the intrinsic delay time τ _pdC of the CMOS inverter shown in FIG. 5 is approximated by the following equation.
τ _pdC = R × C (1)
_{R = (R p + R n} ) / 2 (2)
_{C = C Gp + C Gn +} C Gpo + C Gno + C Dp + C Dn (3)
here,
R _p ... On-resistance of pMOSFET R _n ... On-resistance of nMOSFET C _Gp ... Gate capacity of pMOSFET C _Gn ... Gate capacity of nMOSFET C _Gpo ... Gate overlap capacity of pMOSFET (27C)
C _Gno ... nMOSFET gate overlap capacitance (28C)
CDp... PMOSFET drain parasitic capacitance CDp... NMOSFET drain parasitic capacitance However, C _Gp , C _Gn , CDp and CDp are not shown.
On the other hand, R and C determining the intrinsic delay time τ _pdED of the ED inverter are the same as those of the nMOSFET in the equations (2) and (3), and the gate overlap capacitance (27C) of the pMOSFET. (In the circuit of FIG. 4, the depletion type MOSFET has a gate overlap capacity of only 27 between the gate and the drain).
In the MOSFET using SiC, as described in Non-Patent Document 1, the mobility of holes is much smaller than that of electrons, and therefore R _p >> R _n . Also, in SiC, the source and drain regions cannot be formed in a self-aligned manner on the gate electrode, so the influence of the gate overlap capacitance is significant. Therefore, the difference between τ _pdC and τ _pdED increases. That is, in SiC, the CMOS inverter is significantly more susceptible to these factors, so τ _pdED <τ _pdC , and the ED inverter operates at a much higher speed.

[Embodiment 2]
FIG. 6 shows an inverter (ED inverter) circuit device according to the second embodiment. In this device, in addition to the device structure shown in FIG. 1, in the enhancement type SiC MISFET 22, a p-type gate is formed on the surface portion of the source and drain regions 4E and 3E overlapping the gate electrode 7E on one main surface of the semiconductor region 2. Capacitance relaxation regions 12E and 12E are formed along the edges of the source and drain regions. Each of these regions 12E, 12E extends in the lateral direction (parallel to the main surface of the semiconductor region 2) by about 1 μm from the recess (recess) end, and has a depth of about 100 nm. The impurity concentration is about 1 × 10 ¹⁸ / cm ³ . In this case, the capacitance between the gate and source and between the gate and drain due to the overlap between the gate electrode and the source and drain regions is a combined capacitance in which the capacitance of the gate gate insulating film and the built-in capacitance of the pn junction are connected in series. Although the latter is smaller, the combined capacitance is mainly determined by the latter, and the gate electrode overlap capacitance can be reduced. The SiC MISFET having such a structure functions as a component of a high-speed logic circuit. Have.
In the depletion type SiC MISFET 21, a p-type gate capacitance relaxation region 12D is formed along the edge of the drain region in the surface portion of the drain region 3D immediately below the gate electrode. Since the gate electrode 7D and the source region 4D are directly electrically connected, it is not necessary to form a capacitance relaxation region on the surface portion of the source region 4D. The aim of providing the gate capacitance relaxation region 12D is the same as described above. This SiC MISFET is the best embodiment because it can realize a reduction in the overlapping capacity of the gate electrodes in addition to the advantages of the structure of FIG.

The effect of providing the p-type capacitance relaxation region on the surface of the n-type source and drain regions will be supplementarily described below based on numerical examples.
Capacitances C _GS (between the gate and source) and C _GD (between the gate and drain) between the gate electrode and the source or drain electrode are expressed by the following formula (1) (C _GS and C _{GD are} both the same. Mention _GS ).
Here, C _OX indicates a MOS capacitance formed between a gate electrode sandwiching a gate insulating film (oxide film) and a p-type capacitance relaxation region immediately below the gate electrode, and C _bi indicates a p-type capacitance relaxation region. A built-in capacitance formed by a pn junction between adjacent n-type source regions (including a source electrode) is shown. C _OX and C _bi in the formula (1) are represented as follows.
Calculating an example for the following numbers:
Thus, this value is found to be an extremely low value as compared with a value (= 804 nF) in the case where there is no capacity relaxation region.

  A method for manufacturing an ED inverter circuit device using the SiC MISFET shown in FIG. 6 will be described below with reference to FIGS.

First, as shown in FIG. 7, an SiC substrate in which a p-type SiC semiconductor region 2 is formed on an SiC substrate 1 is prepared. Here, the SiC substrate 1 is either p-type, n-type, or semi-insulating, and the crystal plane is a (0001) Si plane, a (000-1) C plane, or other planes. It may be an azimuth. The p-type SiC semiconductor region 2 is an active layer in which a region constituting the device is formed. For example, the p-type SiC semiconductor region 2 is an epitaxial growth layer having a thickness of 10 μm doped with an impurity concentration of about 5 × 10 ¹⁵ / cm ^3. Become.

Next, as shown in FIG. 8, n + -type source / drain regions facing and separating from each main surface of the SiC semiconductor region 2 are selectively formed in the SiC semiconductor region 2. Here, description will be made on the assumption that the drain region 3E of the enhancement type SiC MISFET and the source region 4D of the depletion type SiC MISFET are formed as a common region (there are three regions that are selectively created). As a means for selectively forming, an insulating film made of an oxide film or the like is formed on one main surface of the semiconductor region 2, and the source and drain regions 4E, 3E and 4D, 3D are formed on the regions where the source and drain regions 4E, 4D, 3D are to be formed by photolithography. A method can be used in which the insulating film is opened to form a mask (not shown), and then, for example, P (phosphorus) is ion-implanted as an n-type impurity. The impurity concentration of these regions can be about 1 × 10 ²⁰ / cm ³ and the thickness can be 250 nm.

Thereafter, as shown in FIG. 9, a p-type region 12E is selectively formed adjacent to one main surface of the semiconductor region 2 and straddling the source and drain regions 4E and 3E in the enhancement type SiC MISFET portion. In the depletion-type SiCMISFET portion, a capacitance relaxation region 12D is formed in the vicinity of the boundary between the drain region 3D and the SiC semiconductor region 2. The selective formation method is the same as that used in the step of FIG. 8, and for example, Al (aluminum) is ion-implanted as a p-type impurity. The depth of the region 17 can be about 100 nm, and the impurity concentration can be about 1 × 10 ¹⁸ / cm ³ .

Next, as shown in FIG. 10, the recesses 5D and 5E are formed by selectively removing the SiC semiconductor region 2 extending over the source and drain regions 4E and 3E, 4D and 3D from one main surface to a predetermined depth. To do. The selective removal here can be performed by dry etching using a mask (not shown) in which an opening is formed in an insulating film made of an oxide film or the like formed on one main surface of the SiC semiconductor region 2. As a result of the formation of the recess (recess), in the enhancement type SiC MISFET portion, the single p-type region 12E formed in the step of FIG. 9 is separated into regions 12E and 12E that are in contact with the source region 4E and the drain region 3E, respectively. Relaxation regions 12E and 12E are formed, and one side surface of the recess (recess) is in contact with source region 4E and p-type region 12E in contact therewith, and the other side surface is in contact with drain region 3E and p-type region 12E in contact therewith. The bottom surface of the recess (recess) is in contact with the portions 3a and 3a (see FIG. 5) of the source and drain regions in the vicinity of both end portions.
Next, for example, P (phosphorus) ions are selectively injected as n-type impurities into the bottom of the recess 5D of the depletion type SiC MISFET portion to control the threshold voltage to a predetermined value (not shown). In order to fabricate the depletion type SiC MISFET, for example, the impurity concentration of the p-type SiC semiconductor region 2 formed of an epitaxial layer is changed to 1 × 10 ¹⁵ / cm ³ instead of the usual 5 × 10 ¹⁵ / cm ^3. It may be lowered to cm ³ , thereby depleting the surface of the p-type SiC semiconductor region 2. In this case, an impurity is additionally implanted at a concentration of about 4 × 10 ¹⁵ / cm ³ into a portion (recess (12E)) where the enhancement type SiC MISFET is to be formed.
The depletion type SiC MISFET portion is the same as the enhancement type SiC MISFET portion except that the capacitance relaxation region is not formed on the surface portion of the source region 4D. Thereafter, the substrate is annealed at, for example, 1600 ° C. for 30 minutes. Thus, the implanted n-type impurity and p-type impurity are activated.

  In the process of FIG. 11, a silicon oxide film 18 is formed on the surface of the SiC semiconductor region 2. The thickness can be 13 nm.

In the process of FIG. 12, first, a polysilicon film is formed on the oxide film 18, and patterned (selective removal of the polysilicon film) with a mask (not shown) formed on the polysilicon film by photolithography technology. Then, gate electrodes 7D and 7E made of polysilicon are formed. The polysilicon film is doped with an n-type impurity at a concentration of 1 × 10 ²⁰ / cm ³ during or after the formation. Using the patterned gate electrodes 7D and 7E as a mask, the underlying oxide film 18 is selectively removed to define gate oxide films 6D and 6E.

  In the process of FIG. 13, an insulating film 8 made of a silicon oxide film is formed on the surface of the SiC semiconductor region 2, and openings are formed in portions located on the source and drain regions.

  Sources and drain electrodes 9, 10 and 11 electrically connected to the source and drain regions are formed through the openings of the oxide film 8 formed in the step of FIG. 13 to complete the device (see FIG. 6). These source and drain electrodes are also formed by patterning an electrode material layer using a mask. Al (aluminum) and Ni (nickel) can be used as the source and drain electrode materials. A low resistance contact can be made on the surface of the source and drain regions in the opening of the oxide film 8 by processing these materials at a high temperature of about 1000 ° C. after vapor deposition. The thickness of the source and drain electrodes is about 1 μm.

  In the manufacturing method of the ED inverter circuit device using the SiC MISFET shown in FIGS. 7 to 13, the case where the capacitance relaxation regions 12D, 12E, and 12E are formed has been described. For example, as shown in FIG. When the ED inverter circuit device is manufactured without providing it, the step of forming the p-type regions 12D and 12E shown in FIG. 9 may be omitted.

[Embodiment 3]
FIG. 17 shows an ED inverter circuit device using the SiC MISFET according to the third embodiment. In this device, the depth at which the bottom surfaces of the recesses (recesses) 14D and 14E are located is selected to be substantially equal to the thicknesses of the source and drain regions 4D, 3D, 4E, and 3E with reference to one main surface of the SiC semiconductor region 2. ing. Ideally, it is desirable that both depths (thicknesses) are the same, but since it is difficult to match the same in the manufacturing process, the depths of the recess bottom surfaces 14D and 14E are set to the source and drain regions 13, Control to be slightly less than 14 thickness. This is because the channel length becomes longer than the target value when the relationship is reversed.
According to this structure, the thickness of a part of the source and drain regions corresponding to 3a and 3a in FIG. 1 can be further reduced to almost zero, so that the effect of suppressing the short channel effect is further enhanced.
In this device, further, in the enhancement type SiC MISFET portion, the surface portions of the source and drain regions 4E and 3E overlapping with the gate electrode 7E on one main surface of the SiC semiconductor region 2 are arranged on the surface portion of the depletion type SiC MISFET portion. P-type regions 12E and 12D are formed along the edges of the source and drain regions, respectively, on the surface portion of the drain machine 3D overlapping 7D. Also in this case, the gate electrode overlap capacitance can be reduced as in the second embodiment.

[Embodiment 4]
14 and 15 show a NAND logic gate circuit device configured using a single channel (n channel) SiC MISFET according to the fourth embodiment. As shown in the circuit configuration diagram shown in FIG. 14, this device includes two enhancement type SIC MISFETs 22 and 22b and a depletion type SiC MISFET 21. The same type of device is connected in series to the enhancement type SiC MISFET 22 in the inverter circuit shown in FIG. The SiC MISFET 22b is connected. These SiC MISFETs 22 and 22b are called gating transistors, and output a predetermined logic output signal to the output node based on the mutual relationship of the signals input to the input nodes 23 and 23b (details of logic circuit operation of this device) Is not the subject of the present invention and will not be described).
The device structure shown in FIG. 15 has an enhancement type SiC MISFET 22b (comprised of a source region 4bE, a drain region 3bE, a recess 5bE, a gate insulating film 6bE, a gate electric station 7bE, and capacitance relaxation regions 12bE and 12bE). Except for this, it is basically the same as the ED inverter circuit device of FIG. Of course, the p-type capacitance relaxation regions 12D, 12E, and 12bE may be omitted as necessary as in the device structure shown in FIG.
Further, as shown in FIG. 17, the concave portion may be formed at the same position as the depth of the source and drain regions, and in this case, the capacitance relaxation region may be omitted.

[Embodiment 5]
FIG. 16 shows a NOR logic gate circuit configuration configured using a single channel (n channel) SiC MISFET according to the fifth embodiment. A specific device structure of this circuit configuration can be obtained in the same manner as described with reference to FIGS.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 SiC semiconductor region 4D, 4E, 4bE Source region 3a Thin region of source and drain region 3D, 3E, 3bE Drain region 5D, 5E, 5bE Recess (recess)
6D, 6E, 6bE Gate insulating film 7D, 7E, 7bE Gate electrode 8 Insulating film 9, 10, 11, 13 Source, drain electrode 12D, 12E, 12bE Capacity relaxation region

Claims (28)

  An enhancement type insulating gate field effect transistor (22) having a source, a drain, and a gate, and an n channel depletion type insulated gate field effect transistor (21) having a source, a drain, and a gate, the enhancement type insulation An input signal (23) and a first power supply potential (25) are supplied to the gate and source of the gate field effect transistor, respectively, and a second power supply potential (24 is supplied to the drain of the depletion type insulated gate field effect transistor. ) Is electrically connected, and the gate of the depletion type insulated gate field effect transistor and the source of the depletion type insulated gate field effect transistor are electrically connected, and the drain of the enhancement type insulated gate field effect transistor and the depletion type The enhancement type insulated gate field effect transistor is electrically connected to the source, and an output signal (26) is taken out from the connection point. The enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect An inverter circuit, wherein the effect transistor is formed using a silicon carbide material.   At least one of the enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect transistor includes a substrate (1) including a one-conductivity-type silicon carbide semiconductor region (2) having one main surface, and the one-conductivity type Source and drain regions (3D, 4D, 3E, 4E) of a conductivity type opposite to the one conductivity type formed in the silicon carbide semiconductor region (2) in contact with the one main surface and spaced apart from each other, and the separation Formed on one main surface side of the one conductivity type silicon carbide semiconductor region (2) sandwiched between opposing edges of the source / drain regions (3D, 4D, 3E, 4E) formed A first side surface in contact with (4D, 4E), a second side surface in contact with the drain region (3D, 3E), and the first and second side surfaces located at a predetermined depth from the one main surface. Continuously formed with the spacing The main surface where the source and drain regions (3D, 4D, 3E, 4E) are in contact with the recesses (5D, 5E) formed by the bottom surface connecting the source and drain regions (3D, 4D, 3E, 4E). Part of the insulating film (6D, 6E) formed on the first and second side surfaces and the bottom surface of the recess (5D, 5E), and on the insulating film (6D, 6E). A formed gate electrode (7D, 7E) and a source or drain electrode (9 or 10) electrically connected to at least one of the source and drain regions (3D, 4D, 3E, 4E); And a silicon carbide field effect transistor having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the bottom surface connecting the source and drain regions (3D, 4D, 3E, 4E). With features The inverter circuit of claim 1, wherein that.   In the enhancement type insulated gate field effect transistor, the one conductivity type is formed in the source and drain regions (3E, 4E) immediately below the gate electrode (7E) formed on the insulating film (6E) covering a part of the one main surface. The inverter circuit according to claim 2, wherein a capacitance relaxation region is formed.   In the depletion type insulated gate field effect transistor, the capacitance relaxation region of one conductivity type is formed in the drain region (3D) immediately below the gate electrode (7D) formed on the insulating film (6D) covering a part of the one main surface. The inverter circuit according to claim 2, wherein (12D) is formed.   2. The inverter circuit according to claim 1, wherein the inverter circuit is formed on the same substrate.   2. The inverter circuit according to claim 1, wherein the inverter circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide. A substrate (1) including one conductivity type silicon carbide semiconductor region (2) having one main surface, and in contact with the one main surface and spaced apart from each other in the one conductivity type silicon carbide semiconductor region (2). In addition, the first source / drain region (4E, 3E) having a conductivity type opposite to the one conductivity type and the opposing edges of the first source / drain regions (4E, 3E) formed apart from each other Formed on one main surface side of the sandwiched one-conductivity-type silicon carbide semiconductor region (2) and in contact with the first source region (4E) and the first drain region (3E) The second side surface in contact with the first source and drain regions (4E, 3E) located at a predetermined depth from the one main surface and connected to the first and second side surfaces and separated from each other are connected. The first recess (5E) formed of the first bottom surface is in contact with the first source / drain regions (4E, 3E). A first insulating film (6E) covering a part of the one main surface and formed on the first and second side surfaces and the first bottom surface of the first recess (5E); A first gate electrode (7E) formed on the first insulating film (6E); and a first source electrode (10) electrically connected to the first source (4E). An enhancement type insulated gate carbonization having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the first bottom surface connecting the first source / drain regions (4E, 3E). A silicon field effect transistor;
A substrate (1) including a one-conductivity-type silicon carbide semiconductor region (2) having the one main surface, and a single-conductivity-type silicon carbide semiconductor region (2) in contact with the one main surface and spaced apart from each other The second source and drain regions (4D, 3D) of the opposite conductivity type to the one conductivity type formed, and the opposing edges of the second source and drain regions (4D, 3D) formed apart from each other A third side surface that is formed on one main surface side of the one-conductivity-type silicon carbide semiconductor region (2) sandwiched between two layers and is in contact with the second source region (4D); and the second drain region (3D) A fourth side surface in contact with the second source and drain regions (4D, 3D) located at a predetermined depth from the one main surface and connected to the third and fourth side surfaces and spaced apart from each other A second recess (5D) having a second bottom surface to be in contact with the second source and drain regions (4D, 3D). A second insulating film (6D) that covers a part of the one main surface and is formed on the third and fourth side surfaces and the second bottom surface of the second recess (5D); A second gate electrode (7D) formed on the second insulating film (6D) and a second drain electrode (9) electrically connected to the second drain region (3D) A depletion type silicon carbide having a recess gate structure in which a channel forming region is formed by the silicon carbide semiconductor region portion adjacent to the second bottom surface connecting the second source / drain regions (4D, 3D) An insulated gate field effect transistor;
The first gate electrode and the first source electrode of the enhancement type silicon carbide insulated gate field effect transistor are connected to an input signal and a first power supply potential, respectively, and the second type of the depletion type silicon carbide field effect transistor is The drain electrode is connected to a second power supply potential, the second gate electrode of the depletion type silicon carbide insulated gate field effect transistor is electrically connected to the second source region, and the enhancement type silicon carbide. The first drain region of the insulated gate field effect transistor and the second source region of the depletion type silicon carbide insulated gate field effect transistor are electrically connected, and an output signal is taken out from the connection point (11). It has a recess structure characterized by being configured as follows Of silicon insulated gate field effect transistor inverter circuit.   At least one of the enhancement type silicon carbide insulated gate field effect transistor and the depletion type silicon carbide insulated gate field effect transistor has a portion in the vicinity of both ends of the first or second bottom surface of the first or second source or drain. 8. The silicon carbide insulated gate field effect transistor inverter circuit having a recess structure according to claim 7, wherein the silicon carbide insulated gate field effect transistor inverter circuit has a recess structure in contact with a thin region (3a, 3a) of the region (4E, 3E, 4D, 3D).   The first source / drain region (4E, 3E) or the second source / drain region (4D, 3D) is formed at a first predetermined depth from the one main surface, and the first or second region is formed. A bottom surface is formed to be located at a second predetermined depth from the one main surface, and at least one of the enhancement type silicon carbide field effect transistor and the depletion type silicon carbide field effect transistor is the second predetermined depth. The depth is selected to be approximately equal to or shallower than the first predetermined depth, and a channel forming region is formed by the silicon carbide semiconductor region portion adjacent over the entire length of the first or second bottom surface. 8. A silicon carbide insulated gate field effect transistor inverter circuit having a recessed structure according to claim 7.   In the enhancement type insulated gate field effect transistor, the one conductivity type is formed in the source and drain regions (3E, 4E) immediately below the gate electrode (7E) formed on the insulating film (6E) covering a part of the one main surface. 8. A silicon carbide insulated gate field effect transistor inverter circuit having a recess structure according to claim 7, wherein the capacitance relaxation region (12E, 12E) is formed.   In the depletion type insulated gate field effect transistor, the capacitance relaxation region of one conductivity type is formed in the drain region (3D) immediately below the gate electrode (7D) formed on the insulating film (6D) covering a part of the one main surface. The silicon carbide insulated gate field effect transistor inverter circuit having a recess structure according to claim 7, wherein (12D) is formed.   8. The silicon carbide insulated gate field effect transistor inverter circuit having a recess structure according to claim 7, wherein a channel formed in the enhancement type silicon carbide field effect transistor and the depletion type silicon carbide field effect transistor is n-type. .   A first n-channel enhancement type insulated gate field effect transistor (22b) having a source, drain and gate; a second n-channel enhancement type insulated gate field effect transistor (22) having a source, drain and gate; An n-channel depletion type insulated gate field effect transistor (21) having a drain and a gate, and the drain of the first enhancement type insulated gate field effect transistor and the second enhancement type insulated gate field effect transistor. The source is electrically connected, the gate of the depletion type insulated gate field effect transistor and the source of the depletion type insulated gate field effect transistor are electrically connected, and the first enhancement type insulated gate. The source of the field effect transistor is connected to a first power supply potential (25), the drain of the depletion type insulated gate field effect transistor is connected to a second power supply potential (24), and the first and second The gate of each of the enhancement type insulated gate field effect transistors is connected to the first and second input signals (23b, 23), and the drain and the depletion type insulated gate of the second enhancement type insulated gate field effect transistor. The source of the field effect transistor is electrically connected, and an output signal (26) is extracted from the connection point. The enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect transistor are carbonized. Consists of silicon materials A NAND logic gate circuit characterized.   At least one of the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor includes a substrate (1) including a one-conductivity type silicon carbide semiconductor region (2) having one main surface. And source and drain regions (4D, 3D, 4E, opposite conductivity type) formed in the one conductivity type silicon carbide semiconductor region (2) in contact with the main surface and spaced apart from each other. 3E, 4bE, 3bE) and the one-conductivity-type silicon carbide semiconductor region sandwiched between opposing edges of the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) formed separately from each other ( 2) a first side surface formed on one main surface side and in contact with the source region (4D, 4E, 4bE); a second side surface in contact with the drain region (3D, 3E, 3bE); Face A recess formed by a bottom surface connecting the source and drain regions (4D, 3D, 4E, 3E, 4bE, and 3bE) that are located at a predetermined depth and that are connected to the first and second side surfaces and are spaced apart from each other. 5D, 5E, 5bE) and a part of the one main surface where the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) are in contact, and the recesses (5D, 5E, 5bE) An insulating film formed on the first and second side surfaces and the bottom surface; a gate electrode (7D, 7E, 7bE) formed on the insulating film; and the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE) having a source or drain electrode (9 or 10) electrically connected to at least one of the source and drain regions (4D, 3D, 4E, 3E, 4bE, 3bE). Adjacent to the bottom to connect 14. The NAND logic gate circuit according to claim 13, comprising a silicon carbide field effect transistor having a recess gate structure in which a channel forming region is constituted by the silicon carbide semiconductor region portion.   In the first or second enhancement type insulated gate field effect transistor, the source and drain regions (3E, 4E,...) Just below the gate electrodes (7E, 7bE) formed on the insulating film covering a part of the one main surface. 15. The NAND logic gate circuit according to claim 14, wherein the one-conductivity type capacitance relaxation region (12E, 12E, 12bE, 12bE) is formed in 3bE, 4bE).   In the depletion type insulated gate field effect transistor, the one conductivity type capacitance relaxation region (12D) is formed in the drain region (3D) immediately below the gate electrode (7D) formed on the insulating film covering a part of the one main surface. 15. The NAND logic gate circuit according to claim 14, wherein the NAND logic gate circuit is formed.   14. The NAND logic gate circuit according to claim 13, wherein the NAND logic gate circuit is formed on the same substrate.   14. The NAND logic gate circuit according to claim 13, wherein the NAND logic gate circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide.   At least one of the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor has a portion in the vicinity of both ends of the bottom surface of the source and drain regions (3D, 4D, 3E, 4E, 15. The NAND logic gate circuit according to claim 14, wherein the NAND logic gate circuit is in contact with a thin region (3a, 3a) of 3bE, 4bE).   The first source and drain regions (3D, 4D, 3E, 4E, 3bE, 4bE) are formed from the one main surface to a first predetermined depth, and the bottom surface is formed from the one main surface to a second predetermined depth. And at least one of the first and second enhancement type silicon carbide insulated gate field effect transistors and the depletion type silicon carbide insulated gate field effect transistor has the second predetermined depth. 15. The NAND according to claim 14, wherein a channel forming region is constituted by the silicon carbide semiconductor region portion which is selected to be substantially equal to or shallower than the first predetermined depth and is adjacent to the entire length of the bottom surface. Logic gate circuit.   A first n-channel enhancement type insulated gate field effect transistor (22b) having a source, drain and gate; a second n-channel enhancement type insulated gate field effect transistor (22) having a source, drain and gate; An n-channel depletion type insulated gate field effect transistor (21) having a drain and a gate, and the source of the first enhancement type insulated gate field effect transistor and the second enhancement type insulated gate field effect transistor. The source is electrically connected, the connection point is connected to the first power supply potential (25), the drain of the first enhancement type insulated gate field effect transistor and the second enhancement type insulated gate electric field. The drain of the effect transistor Are connected to the gate and the source of the depletion type insulated gate field effect transistor, and an output signal (26) is taken out from the connection point, and the depletion The drain of the type insulated gate field effect transistor is connected to a second power supply potential (24), and the gates of the first and second enhancement type insulated gate field effect transistors are respectively connected to the first and second input signals ( 23b, 23), and the enhancement type insulated gate field effect transistor and the depletion type insulated gate field effect transistor are made of silicon carbide material.   At least one of the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor includes a substrate including a one-conductivity-type silicon carbide semiconductor region having one main surface, and the one-conductivity type A source / drain region of a conductivity type opposite to the one conductivity type formed in a silicon carbide semiconductor region in contact with the one main surface and spaced apart from each other, and a source / drain region formed opposite to each other facing each other. From the one main surface, a first side surface in contact with the source region, a second side surface in contact with the drain region, formed on one main surface side of the one conductivity type silicon carbide semiconductor region sandwiched between edges A recess that is located at a predetermined depth and that is continuous with the first and second side surfaces and is formed to be spaced apart from each other, and a bottom surface that connects the source and drain regions; An insulating film which covers a part of the one main surface with which the drain region is in contact and is formed on the first and second side surfaces and the bottom surface of the concave portion; and a gate electrode which is formed on the insulating film; And a source or drain electrode electrically connected to at least one of the source and drain regions, and a channel forming region is formed by the silicon carbide semiconductor region adjacent to the bottom surface connecting the source and drain regions 22. The NOR logic gate circuit according to claim 21, comprising a silicon carbide field effect transistor having a recessed gate structure.   In the first or second enhancement type insulated gate field effect transistor, the one-conductivity-type capacitance relaxation region is provided in a source / drain region immediately below a gate electrode formed on an insulating film covering a part of the one main surface. The NOR logic gate circuit according to claim 22, wherein the NOR logic gate circuit is formed.   In the depletion type insulated gate field effect transistor, the capacitance relaxation region of one conductivity type is formed in a drain region directly below a gate electrode formed on an insulating film covering a part of the one main surface. The NOR logic gate circuit according to claim 22.   The NOR logic gate circuit according to claim 21, wherein the NOR logic gate circuit is formed on the same substrate.   The NOR logic gate circuit according to claim 21, wherein the NOR logic gate circuit is formed on a substrate including a semiconductor region mainly composed of silicon carbide.   At least one of the first and second enhancement type insulated gate field effect transistors and the depletion type insulated gate field effect transistor has a portion in the vicinity of both ends of the bottom surface in contact with a thin region of the source and drain regions. 23. The NOR logic gate circuit according to claim 22, wherein:   The first source and drain regions are formed at a first predetermined depth from the one main surface, and the bottom surface is formed at a second predetermined depth from the one main surface. At least one of the second enhancement type silicon carbide insulated gate field effect transistor and the depletion type silicon carbide insulated gate field effect transistor has the second predetermined depth substantially equal to or more than the first predetermined depth. 23. The NOR logic gate circuit according to claim 22, wherein a channel forming region is constituted by the silicon carbide semiconductor region portion which is selected shallowly and is adjacent to the entire length of the bottom surface.