JP5098293B2 - Insulated gate type semiconductor device using wide band gap semiconductor and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulated gate semiconductor device such as a MOSFET or an IGBT, and more particularly, an insulated gate semiconductor device as a power device used in a power converter such as an inverter, a power supply device such as various industrial machines, or an automobile igniter. And a manufacturing method thereof. More specifically, the main semiconductor material is a wide band gap semiconductor of about 3 eV larger than a silicon semiconductor having a band gap of 1.08 eV, such as silicon carbide (hereinafter referred to as SiC) and gallium nitride (hereinafter referred to as GaN). The present invention relates to an insulated gate semiconductor device.

Conventionally, so-called power devices that handle large electric power have been manufactured mainly using silicon semiconductors. In order to enable a large current capacity, a power device is often configured to allow current to flow in the longitudinal direction (thickness direction) between both main surfaces of a chip. 5 and 6 are sectional views of typical vertical MOSFETs in such an insulated gate semiconductor device as a conventional power device. The vertical MOSFET shown in FIG. 5 is called a planar gate structure, and has a structure in which a gate electrode 23 and a gate insulating film 24 immediately below the gate electrode 23 are formed in parallel to the main surface. When an ON signal equal to or higher than the threshold voltage is input to the gate electrode 23, the vertical MOSFET is turned on, passes through an n channel (not shown) formed on the surface of the p-well region 25 immediately below the gate insulating film 24, and reaches the drain side. The main current flows from the n ⁺ semiconductor substrate 20 and the drift layer 22 to the source region 28. Further, this MOSFET has a structure in which the main current is cut off by turning off the input signal to the gate electrode, and the off voltage is maintained by the pn junction between the n ⁻ type drift layer 22 and the p well region 25. It can be used for switching. It should be noted that the n-type high impurity concentration buffer layer 21 can reduce the thickness of the n ⁻ -type drift layer 22 that is a high-resistance region by suppressing the extension of the depletion layer from the pn junction when a high voltage is applied. Thus, there is an effect of reducing the ON voltage. Reference numeral 20 denotes a high impurity concentration semiconductor substrate, and a drain electrode 29 is formed on the back surface of the semiconductor substrate 20 by ohmic contact. The surface side is covered with an interlayer insulating film 30 for ensuring insulation from the gate electrode 23, and is directly in contact with the surface of the n ⁺ source region 28 and highly doped with the surface of the p well region 25. A source electrode 27 in common contact is formed via the concentration p ⁺ region 26. Since the planar gate structure formed in the vertical MOSFET described above is a planar structure, there is an advantage that it is easy to manufacture.

On the other hand, the MOSFET shown in the cross-sectional view of FIG. 6 is called a trench MOSFET because it has a so-called trench gate structure in which a gate is formed inside a concave trench 35. This trench gate structure is more complicated than the planar gate structure, and the number of processes increases accordingly. However, the trench gate structure can greatly increase the integration density by miniaturizing the pattern of the device unit formed in the active part of the substrate surface, so that excellent device characteristics with low on-resistance can be easily obtained. In recent years, many have been adopted. The constituent elements described below other than the MOSFET trench gate structure have the same functions as those of the planar gate structure vertical MOSFET shown in FIG. 5, and therefore, further description thereof is omitted here. That is, the high impurity concentration n-type semiconductor substrate 20, the n-type high impurity concentration buffer layer 21, the n ⁻ -type drain region 22, the p-well region 25, the n ⁺ source region 28, the high impurity concentration p ⁺ region 26, the interlayer insulating film The detailed description of components such as 30, the gate electrode 23, the source electrode 27, and the drain electrode 29 will be omitted.

  However, in the case of silicon devices, the device unit pattern on the substrate surface, even in the case of trench MOSFETs, has been miniaturized to the limit by making full use of LSI microfabrication technology, resulting in improved device characteristics Is almost approaching the material limit. Therefore, an attempt has been made to break through this material limit with a semiconductor material having a wider band gap than silicon, such as SiC and GaN. Since these semiconductor materials have a maximum breakdown electric field that is almost an order of magnitude higher than that of silicon, it is expected that the resistance of the element will be 1/100 or less when this is used for a power device. Using a semiconductor material having a wider band gap than silicon, MOSFETs having the planar gate structure of FIG. 5 and the trench gate structure of FIG.

  In known literatures and the like, as a device using a semiconductor material having a wider band gap than silicon, for example, for manufacturing an insulated gate bipolar transistor (IGBT), a p-type and n-type gallium nitride compound semiconductor is formed on a silicon semiconductor substrate. A p-type impurity diffusion region and an n-type impurity diffusion region made of a gallium nitride compound semiconductor having a wider band gap than the n-type semiconductor layer are selectively formed on the n-type semiconductor layer. An arrangement of the same structure is known. Then, a gate electrode is formed through an insulating layer from the exposed surface of the n-type semiconductor layer of the gallium nitride compound semiconductor to the exposed surface of the p-type impurity diffusion region, and the emitter electrode and the collector electrode are respectively diffused by n-type impurity. The structure formed in the upper surface of an area | region and the lower surface of a p-type semiconductor layer is announced (patent document 1).

Furthermore, in the case of a MOSFET using a GaN semiconductor, which is a semiconductor material having a wider band gap than silicon, the mobility of electrons in the n-channel exceeds 100 cm ² / Vs, which is relatively larger than that of the SiC-MOSFET. There is also a report example (Non-patent Document 1).
JP-A-11-354786 K. Matocha, T .; P. Chow, R.W. J. et al. Gutmann, IEEE Trans. Electrton Devices, VOL. 52, no. 1, 2005, pp. 6-10

However, in the IGBT using the gallium nitride compound semiconductor disclosed in Patent Document 1, the resistance component of the channel region is said to be significantly larger than that of a normal silicon device. The reason is that the electron mobility of the inversion layer (channel layer) obtained in a normal MOS (metal-oxide film-semiconductor insulating gate) structure using silicon is about several hundred cm ² / Vs (500 cm ² / Vs). In contrast, the electron mobility of the inversion layer in the case of using a gallium nitride compound semiconductor is as low as several tens of cm ² / Vs, and the resistance component of the channel region is corresponding to this. This is because it becomes larger. On the other hand, the inversion layer in the case of using silicon carbide (SiC) as a semiconductor material is only a lower mobility level than the GaN semiconductor, which is a further problem.

In addition, as compared with silicon semiconductors, SiC and GaN as semiconductor materials have extremely large restrictions on device manufacturing. In SiC, the characteristics of the MOS interface are not as good as those of silicon or GaN. Therefore, there is a big problem that it is difficult to obtain excellent characteristics of the entire device.
In the manufacturing process, in a silicon device, impurities of a donor and an acceptor are usually introduced by ion implantation, then activated by a heat treatment at about 1000 ° C., and a diffusion layer having an appropriate depth is formed by a subsequent heat treatment. It is possible to form most pn junctions in the device structure.

  However, in SiC and GaN, even if a donor or acceptor is introduced into a semiconductor substrate by ion implantation, there is a difficulty in electrically activating it by a subsequent heat treatment. Although there are some attempts in GaN, the introduction of both n-type and p-type is extremely difficult by ion implantation, and few successful examples are known. On the other hand, SiC requires activation heat treatment at a high temperature of about 1500 ° C., but can be activated after ion implantation.

However, in SiC, as described above, interface states are generated at the MOS interface so much that the mobility of electrons in the channel becomes very low, so that the excellent characteristics of the substrate crystal can be sufficiently extracted. Making a device is not easy. In this regard, as GaN has already reported (Non-Patent Document 1), the electron mobility in the channel of the MOSFET exceeds 100 cm ² / Vs, and the MOS interface is superior to SiC. Characteristics are easy to obtain. As described above, both SiC and GaN have problems in manufacturing devices, and it is very difficult to overcome this.

  In addition, the gallium nitride compound semiconductor substrate has a thermal expansion coefficient different by about 50% and a lattice mismatch of about 15% compared to the silicon semiconductor substrate, and therefore has a larger gallium nitride layer than the silicon substrate. There is also a problem that when the film is laminated on a silicon substrate, the film is warped. Therefore, it is difficult to handle the wafer, and even in the case of a chip, it is said that soldering is difficult due to warpage. In addition, although gallium nitride semiconductor uses Mg or the like as a p-type dopant, since the activation rate of the p-type dopant is very low, it is difficult to accurately control the impurity concentration. There is also a problem that it is difficult to design such a withstand voltage structure.

  The present invention has been made in view of the above points, and the object of the present invention is to improve MOS interface characteristics even in an insulated gate semiconductor device having a silicon carbide semiconductor as a main constituent material. An object of the present invention is to provide an insulated gate semiconductor device using a wide band gap semiconductor capable of improving channel mobility and a method for manufacturing the same.

  According to the first aspect of the present invention, the surface of the one conductivity type source region and the surface of the other conductivity type region sandwiched between the surface of the one conductivity type drain region are arranged on one surface of the silicon carbide semiconductor substrate. The other conductivity type GaN semiconductor channel layer covering the other conductivity type region surface and in common contact from the one conductivity type source region surface to the one conductivity type drain region surface, and a gate covering the other conductivity type GaN semiconductor channel layer The object of the present invention is achieved by providing a wide band gap semiconductor insulated gate semiconductor device comprising an oxide film and a gate electrode covering the other-conductivity-type GaN semiconductor channel layer via the gate oxide film. .

  According to the invention of claim 2, the one-conductivity type source region and the one-conductivity type drain region each have a high impurity concentration or more that exhibits ohmic contact with one surface of the silicon carbide semiconductor substrate. 2. The wide band gap semiconductor insulated gate type semiconductor device according to claim 1, further comprising a source electrode or a drain electrode each having a region with an impurity concentration and covering the surface of the high impurity concentration region. .

  According to a third aspect of the present invention, the silicon carbide semiconductor substrate includes a one-conductivity type high impurity concentration substrate, a one-conductivity type low impurity concentration layer formed on the substrate, and the one-conductivity type low impurity concentration. Another conductivity type well region selectively formed on the surface of the layer and a one conductivity type high impurity concentration source region formed on the surface of the other conductivity type well region. The surface of the one conductivity type high impurity concentration source region is disposed so that the surface of the other conductivity type well region is sandwiched between the surface of the conductivity type high impurity concentration source region and the surface of the one conductivity type low impurity concentration layer. 2. The wide band gap semiconductor insulated gate semiconductor device according to claim 1, wherein a source electrode is coated, and a drain electrode is coated on a surface of the one conductivity type high impurity concentration substrate on the other surface side. Toss It is more preferable.

  According to a fourth aspect of the present invention, the silicon carbide semiconductor substrate is selected as a one-conductivity type high impurity concentration substrate, a one-conductivity type low impurity concentration drift layer formed on the substrate, and a surface of the drift layer. From the surface of the one conductivity type high impurity concentration source region on the one surface side of the silicon carbide semiconductor substrate, and another conductivity type well region formed on the surface of the well region. Covering the trench reaching the one conductivity type low impurity concentration drift layer through the other conductivity type well region and the surface of the other conductivity type well region exposed on the sidewall of the trench, the one conductivity type high impurity concentration source region The other-conductivity-type GaN semiconductor channel layer reaching the trench bottom from the side wall surface, and a gate insulating film formed in the trench so as to cover the other-conductivity-type GaN semiconductor channel layer A trench gate structure including a gate electrode embedded in the trench, and one surface side of the silicon carbide semiconductor substrate is in common contact with the surface of the one conductivity type high impurity concentration source region and the surface of the other conductivity type well region 2. An insulated gate semiconductor of a wide band gap semiconductor according to claim 1, further comprising a drain electrode on the surface of the one conductivity type high impurity concentration substrate on the other surface side of the silicon carbide semiconductor substrate. An apparatus is preferred.

  According to the invention of claim 5, the one conductivity type low impurity concentration drift layer, the other conductivity type well layer, and the one conductivity type high impurity concentration source layer are formed on one surface of the one conductivity type high impurity concentration silicon carbide substrate. A first step of forming a silicon carbide semiconductor substrate comprising: a second step of forming a trench reaching the one conductivity type low impurity concentration drift layer from the surface of the one conductivity type high impurity concentration source layer; and silicon carbide including the trench A third step of depositing another conductivity type GaN semiconductor channel layer on the surface of the semiconductor substrate, and removing the other conductivity type GaN semiconductor channel layer while leaving the other conductivity type GaN semiconductor channel layer on the trench side wall by anisotropic etching. Then, a fourth step of forming a gate electrode in the trench through a gate insulating film, contacting the one conductivity type high impurity concentration source layer and the other conductivity type well layer. And a fifth step of forming a drain electrode on the other surface of the one-conductivity-type high impurity concentration silicon carbide substrate. Thus, the object of the present invention can be achieved.

According to a sixth aspect of the present invention, the method for forming the one conductivity type high impurity concentration source layer or the other conductivity type well layer is SiC epitaxial growth. A method for manufacturing an insulated gate semiconductor device of a gap semiconductor is preferable.
According to a seventh aspect of the present invention, the method for forming the one conductivity type high impurity concentration source layer or the other conductivity type well layer is an ion implantation method. It is more preferable to use a method for manufacturing an insulated gate semiconductor device of a band gap semiconductor.

6. The wide band gap semiconductor insulated gate semiconductor device according to claim 5, wherein the method of forming the other conductivity type GaN semiconductor channel layer is heteroepitaxial growth. It is desirable to use this manufacturing method.
According to a ninth aspect of the present invention, the method of forming the other-conductivity-type GaN semiconductor channel layer is an ion implantation method. The wide band gap semiconductor insulated gate semiconductor according to the fifth aspect It is more desirable to use a method for manufacturing an apparatus.

  According to the present invention, even in an insulated gate semiconductor device mainly composed of a silicon carbide semiconductor, insulation using a wide band gap semiconductor that can improve MOS interface characteristics and improve channel mobility. A gate type semiconductor device can be provided.

Exemplary embodiments of an insulated gate semiconductor device using a wide bandgap semiconductor according to the present invention and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Symbols + and ⁻ such as n ⁺ and n ⁻ represent a relatively higher impurity concentration and a lower impurity concentration, respectively, in comparison with an n-type impurity concentration without these symbols. One conductivity type is described as n-type, and the other conductivity type is described as p-type. Further, the present invention is not limited only to the description of the examples described below.

  FIG. 1 is a cross-sectional view of the most fundamental MOSFET according to the present invention. FIG. 2 is an energy band diagram for explaining electron movement in the SiC / GaN heterojunction on the source side in the MOSFET of FIG. 1 according to the present invention. FIG. 3 is a cross-sectional view of a main part of the vertical MOSFET according to the present invention. FIGS. 4A to 4C are cross-sectional views of the main part of the MOSFET for each manufacturing process showing the method for manufacturing the trench MOSFET according to the present invention.

The cross-sectional view of FIG. 1 shows the structure of a basic MOSFET according to the present invention. A p-type SiC semiconductor substrate 1 and a source region 2 and a drain region 3 of high impurity concentration n-type SiC selectively formed on the surface of the p-SiC semiconductor substrate 1 are provided. The exposed surface region of the p-SiC substrate 1 and the surface of each of the n ⁺ -type SiC source region 2 and the n ⁺ -type SiC drain region 3 disposed so as to sandwich the exposed surface region are in common contact with each other. In addition, the p-type GaN semiconductor channel layer 4 is formed by heteroepitaxial growth. Since SiC semiconductors have almost the same lattice constant as GaN semiconductors, they are characterized by easy heteroepitaxial growth. Further, by stacking the gate electrode 6 so as to cover the p-type GaN channel layer 4 via the gate insulating film 5 covering the surface of the p-type GaN semiconductor channel layer 4, the threshold voltage to the gate electrode 6 is increased. Is applied, a n-type inversion layer is formed on the surface of the p-type GaN semiconductor channel layer 4 so that a current flows between the drain and the source.

This MOSFET is characterized in that a MOS structure is formed on the surface of the p-GaN semiconductor channel layer 4 deposited on the surface of the p-SiC semiconductor substrate 1 and the inversion layer to be formed on the surface of the layer 4 The n ⁺ -type SiC source region 2 and the n ⁺ -type drain region 3 that are in contact with each other so as to overlap both ends of the p-GaN semiconductor channel layer 4 are electrically connected, so that the SiC channel caused by SiC having poor interface characteristics The use of the area can be avoided. Since the lattice constants of the GaN semiconductor and the SiC semiconductor are almost the same, it is also a feature that a good heterojunction can be formed. The impurity concentration of the p-GaN semiconductor channel layer 4 is 5 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ and the thickness is about 0.2 to 1 μm. By adopting such a configuration of the MOS structure, the path through which the main current flows is from the drain SiC region 3 to the MOS inversion layer formed at the interface between the p-GaN semiconductor channel layer 4 and the gate insulating film 5. This is a low-resistance current path that is carried and further toward the SiC region 2 on the source side.

At this time, two heterojunctions of SiC / GaN exist on the source 2 side and the drain 3 side. The situation at this time will be described with reference to FIG. Although FIG. 2 is drawn assuming a GaN / SiC heterojunction portion on the source 2 side, the basic structure is the same on the drain 3 side only with different bias conditions. In the heterojunction of GaN / SiC, energy barriers Δc and Δv are generated on the conduction band side and the valence band side, respectively, as shown in FIG. In the case of GaN / 4H-SiC, Δc = 0.4 eV, Δv = 0.25 eV
Degree. When the drain 3 side is in a positive bias state, the GaN / SiC heterojunction on the drain 3 side has no barrier from the viewpoint of electrons. On the other hand, since a 0.4 eV barrier exists at the GaN / SiC junction on the source 2 side, no current flows as it is. Therefore, when a positive voltage is applied to the gate electrode 6, the surface potential of GaN on the gate insulating film 5 side is lowered as shown in (b), and the p-GaN semiconductor channel layer 4 is depleted. When a higher gate voltage is applied, the barrier becomes very thin as shown in (c), and a large amount of majority carrier electrons 10 on the source 2 side flow out to the GaN semiconductor channel layer 4 by the tunnel effect, and the gate insulating film 5 is supplied to the electron storage layer at the interface with the first electrode 5. The electrons flow along the accumulation layer to the drain side, and as a result, a current flows between the source and the drain.

In this way, in the SiC-MOSFET having the poor interface characteristics of the MOS gate structure, the excellent interface characteristics of the GaN surface can be used as the MOS gate structure to extract the excellent characteristics of GaN and SiC. It becomes possible.
FIG. 3 shows an embodiment in which the present invention is applied to a vertical MOSFET. As described above, the SiC semiconductor and the GaN semiconductor have a wider band gap than the Si semiconductor, so that it is possible to expect characteristics superior to the Si semiconductor as a power device. FIG. 3 shows the application of the present invention to the conventional planar gate MOSFET shown in FIG. Most of the semiconductor substrates are SiC, and 4H—SiC is particularly desirable because of its high electron mobility. Although the basic structure is the same as that of FIG. 5, a high resistance n ⁻ drift layer 13 formed epitaxially on the SiC−n ⁺ semiconductor substrate 12 and a p well region 14 formed on the surface of the n ⁻ drift layer 13. and ^{n +} on the surface of the SiC semiconductor substrate having a source region 15, so that the p-GaN semiconductor channel layer 16 is in contact with the common and ^{the n +} source region 15 and the SiC of the p-well region 14 and the SiC semiconductor substrate of the surface of the SiC Formed by heteroepitaxial growth. A gate oxide film 17 and a gate electrode 18 are formed so as to cover the surface of the p-GaN semiconductor channel layer 16, a source electrode 19 is formed in the SiCn ⁺ source region 15, and a back surface of the SiC-n ⁺ semiconductor substrate 12 is formed. Each drain electrode 11 is formed to constitute a vertical MOSFET. The basic operation principle is the same as that described with reference to FIG. 2, and this basic operation principle allows a large current to flow in the vertical direction through the low-resistance GaN-MOS structure with a lower resistance than the SiC-MOS structure. . In the vertical MOSFET shown in FIG. 3 as well, the gate electrode 18 formed on the surface of the p-GaN semiconductor channel layer 16 via the gate oxide film 17 is the same as in the MOSFET described in FIG. The inversion layer formed by the signal to 18 covers the surface of the p-GaN semiconductor channel layer 16 so that the SiC-n ⁺ source region 15 and the n ⁻ drift layer 13 are electrically connected with low resistance. It is necessary to form as follows. A channel is not formed in the SiCp well region 14 in FIG. 3, and it has a function of maintaining the off voltage.

  FIGS. 4-1 to 4-3 are cross-sectional views of the main part of the MOSFET showing, for each manufacturing process, a manufacturing method when the present invention is applied to a power MOSFET having a trench gate structure. The device structure of the MOSFET in the final manufacturing process is shown in the sectional view of FIG. 4-3 (g). According to the sectional view of FIG. 4C, the p-GaN semiconductor channel layer 45 is provided on the side wall surface of the trench 50, and a MOS inversion layer is formed in the p-GaN semiconductor channel layer 45. In FIGS. 4A to 4C, the manufacturing steps up to the final step MOSFET shown in FIG. 4G are shown by FIGS.

First, in FIG. 4A, an n ⁻ drift layer 42, a p well layer 43, and an n ⁺ source layer 44 made of a SiC semiconductor are formed on a high impurity concentration n ⁺ type SiC substrate 41, respectively. At this time, the p-well layer 43 and the n ⁺ source layer 44 may be formed by an SiC epitaxial growth layer containing a corresponding impurity element or by ion implantation and subsequent annealing in an SiC semiconductor epitaxial growth layer containing no impurity element. Is possible. A trench 50 reaching the n ⁻ drift layer 42 from the surface of the n ⁺ source layer 44 of the SiC laminated substrate is formed (FIG. 4B). Further, the p-GaN semiconductor channel layer 45 having an impurity concentration of 5 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ and a thickness of 0.2 μm to 1 μm is epitaxially grown on the surface of the SiC laminated substrate including the trench 50 (FIG. 4-2 (c)). The p-GaN semiconductor channel layer 45 can also be formed by a SiC epitaxial growth layer containing a corresponding impurity element or by ion implantation and subsequent annealing in a SiC semiconductor epitaxial growth layer containing no impurity element. Thereafter, when anisotropic etching of the p-GaN semiconductor channel layer 45 is performed, only the p-GaN semiconductor channel layer 45 in a portion parallel to the main surface of the multilayer substrate is removed, and the p-GaN semiconductor channel on the sidewall of the trench 50 is removed. The layer 45 can be left (FIG. 4-2 (d)). Next, an insulating film is formed on the entire surface in order to form the gate insulating film 46 on the surface of the p-GaN semiconductor channel layer 45 on the sidewall of the trench (FIG. 4-3 (e)). A gate electrode 47 made of conductive polysilicon or the like is buried in the trench 50 through this insulating film. The polysilicon film is patterned to form a gate electrode 47 (FIG. 4-3 (f)). Next, when a source electrode 49 in common contact with the p-well layer 43 and the n ⁺ source layer 44 is formed on the surface side of the multilayer substrate, and a drain electrode 48 is formed on the back surface, the trench type vertical MOSFET according to the present invention is obtained. (Fig. 4-3 (g)).

Also in this case, the inversion layer portion in which the main current flows in the MOS gate structure on the surface side is formed not in the SiC layer but in the p-GaN semiconductor channel layer 45 as in FIG. 3, and thus is generated in the SiC semiconductor layer. Compared with the inversion layer, it is possible to use a good electron mobility due to GaN, to make a current path with a low resistance, and to obtain a MOSFET with a low on-resistance.
Further, in the trench MOSFET according to the present invention, the p-GaN semiconductor channel layer 45 on the side wall of the trench reaches the bottom of the trench 50 as compared with the conventional trench MOSFET of FIG. This also has the effect of preventing breakdown voltage degradation due to electric field concentration on the gate insulating film, which is likely to be a problem.

It is sectional drawing which shows the basic structure of the wide band gap semiconductor MOSFET concerning this invention. It is an energy band figure for demonstrating the operation | movement concerning this invention. 1 is a cross-sectional structure diagram of a planar type vertical MOSFET according to the present invention. It is sectional drawing for every manufacturing process which shows the structure of the trench type vertical MOSFET concerning this invention, and its manufacturing method (the 1). It is sectional drawing for every manufacturing process which shows the structure of the trench type vertical MOSFET concerning this invention, and its manufacturing method (the 2). It is sectional drawing for every manufacturing process which shows the structure of the trench type vertical MOSFET concerning this invention, and its manufacturing method (the 3). It is principal part sectional drawing of the conventional planar gate vertical MOSFET. It is principal part sectional drawing of the conventional trench vertical MOSFET.

Explanation of symbols

1 p-SiC substrate 2, 15, 44 n ⁺ source region 3 n ⁺ drain region 4, 16, 45 p-GaN semiconductor channel layer 5, 17, 46 Gate insulating film 6, 18, 47 Gate electrode 7, 19, 49 Source electrode 8, 11, 48 Drain electrode 12, 41 High impurity concentration n ⁺ SiC semiconductor substrate 13, 42 n ⁻ drift layer 14, 43 p well layer 50 trench.

Claims (9)

A surface of one conductivity type source region and a surface of another conductivity type region sandwiched between surfaces of the one conductivity type drain region are disposed on one surface of the silicon carbide semiconductor substrate, covering the surface of the other conductivity type region, and Other-conductivity-type GaN semiconductor channel layer in common contact from the source region surface of the mold to the surface of the one-conductivity-type drain region, a gate oxide film covering the other-conductivity-type GaN semiconductor channel layer, and the other conductivity A wide bandgap semiconductor insulated gate semiconductor device comprising: a gate electrode covering the type GaN semiconductor channel layer. The one conductivity type source region and the one conductivity type drain region each include a region having a high impurity concentration equal to or higher than an impurity concentration exhibiting ohmic contact on one surface of the silicon carbide semiconductor substrate, and the high impurity concentration region 2. The wide band gap semiconductor insulated gate semiconductor device according to claim 1, further comprising a source electrode or a drain electrode covering the surface. The silicon carbide semiconductor substrate is a one conductivity type high impurity concentration substrate, a one conductivity type low impurity concentration layer formed on the substrate, and another conductivity type well region selectively formed on the surface of the one conductivity type low impurity concentration layer. And one conductivity type high impurity concentration source region formed on the surface of the other conductivity type well region, and on one surface of the silicon carbide semiconductor substrate, the surface of the one conductivity type high impurity concentration source region and the one conductivity type The surface of the other conductivity type well region is disposed between the surface of the low impurity concentration layer and the surface of the one conductivity type high impurity concentration source region is covered with a source electrode, 2. The wide band gap semiconductor insulated gate semiconductor device according to claim 1, wherein the surface of the conductive high impurity concentration substrate is covered with a drain electrode. The silicon carbide semiconductor substrate is a one conductivity type high impurity concentration substrate, a one conductivity type low impurity concentration drift layer formed on the substrate, another conductivity type well region selectively formed on the surface of the drift layer, and the well region One conductivity type high impurity concentration source region formed on the surface, and penetrates the other conductivity type well region from the surface of the one conductivity type high impurity concentration source region on the one surface side of the silicon carbide semiconductor substrate. A trench reaching the low impurity concentration drift layer and the other conductivity type GaN semiconductor channel layer covering the surface of the other conductivity type well region exposed on the side wall of the trench and reaching the bottom of the trench from the side wall surface of the one conductivity type high impurity concentration source region And a gate electrode embedded in the trench through a gate insulating film formed in the trench so as to cover the other conductivity type GaN semiconductor channel layer And having a source electrode in common contact with the surface of the one conductivity type high impurity concentration source region and the surface of the other conductivity type well region on one surface side of the silicon carbide semiconductor substrate, 2. The wide band gap semiconductor insulated gate semiconductor device according to claim 1, wherein a drain electrode is provided on the surface of the one conductivity type high impurity concentration substrate on the other side of the silicon semiconductor substrate. A first step of forming, in this order, a silicon carbide semiconductor substrate comprising a one conductivity type low impurity concentration drift layer, another conductivity type well layer, and a one conductivity type high impurity concentration source layer on one surface of a one conductivity type high impurity concentration silicon carbide substrate. A second step of forming a trench reaching the one conductivity type low impurity concentration drift layer from the surface of the one conductivity type high impurity concentration source layer, and depositing another conductivity type GaN semiconductor channel layer on the surface of the silicon carbide semiconductor substrate including the trench A third step, anisotropic etching, removes the other conductivity type GaN semiconductor channel layer while leaving the other conductivity type GaN semiconductor channel layer on the side wall of the trench, and then passes through the gate insulating film in the trench. A fourth step of forming a gate electrode; a fifth step of forming a source electrode in contact with the one conductivity type high impurity concentration source layer and the other conductivity type well layer; Method for producing a wide band gap semiconductor insulated gate semiconductor device, characterized in that it comprises a sixth step of forming a drain electrode on the conductive type high impurity concentration silicon carbide on the other surface of the substrate. 6. The method of manufacturing an insulated gate semiconductor device of a wide band gap semiconductor according to claim 5, wherein the formation method of the one conductivity type high impurity concentration source layer or the other conductivity type well layer is SiC epitaxial growth. 6. The method of manufacturing an insulated gate semiconductor device of a wide band gap semiconductor according to claim 5, wherein the formation method of the one conductivity type high impurity concentration source layer or the other conductivity type well layer is an ion implantation method. 6. The method of manufacturing an insulated gate semiconductor device of wide band gap semiconductor according to claim 5, wherein the formation method of the other conductivity type GaN semiconductor channel layer is heteroepitaxial growth. 6. The method of manufacturing an insulated gate semiconductor device of a wide band gap semiconductor according to claim 5, wherein the formation method of the other conductivity type GaN semiconductor channel layer is an ion implantation method.

Images