JP3573149B2 - Silicon carbide semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device.
[0002]
[Prior art]
[Patent Document] JP-A-10-233503 (page 5-6, FIG. 1)
[Non-patent literature] V. Afanasev, M .; Bassler, G .; Pensl and M.S. Schulz, Phys. Stat. Sol. (A) 162 (1997) 321. .
[0003]
Silicon carbide (hereinafter referred to as SiC) has a wide band gap, and the maximum breakdown electric field is one digit larger than that of silicon (hereinafter referred to as Si). Further, the natural oxide of SiC is SiO ₂ Thus, a thermal oxide film can be easily formed on the surface of SiC by the same method as Si. For this reason, SiC is expected to be a very excellent material when used as a high-speed / high-withstand-voltage switching element of an electric vehicle, particularly a high-power uni / bipolar element.
[0004]
A conventional SiC power MOSFET structure is disclosed, for example, in the above-mentioned patent document. In this conventional SiC power MOSFET, the high concentration N ⁺ N on the SiC substrate ⁻ A type SiC epitaxial region is formed. In a predetermined region in the surface layer portion of the epitaxial region, P ⁻ Mold base region, and N ⁺ A mold source region is formed. Also, N ⁻ A gate electrode is arranged on the type SiC epitaxial region via a gate insulating film, and the gate electrode is covered with an interlayer insulating film. P ⁻ Mold base region and N ⁺ A source electrode is formed in contact with the mold source region, and N ⁺ A drain electrode is formed on the back surface of the type SiC substrate.
[0005]
The operation of this SiC power MOSFET is such that when a positive voltage is applied to the gate electrode while a voltage is applied between the drain electrode and the source electrode, the P ⁻ An inversion type channel region is formed in the surface layer of the mold base region, and current can flow from the drain electrode to the source electrode. In addition, by removing the voltage applied to the gate electrode, the drain electrode and the source electrode are electrically insulated, and exhibit a switching function.
[0006]
[Problems to be solved by the invention]
However, the SiC power MOSFET disclosed in the above patent document has the following problems. That is, an incomplete crystal structure, that is, a large amount of interface states exists at the interface between the gate insulating film and the inversion type channel region (see the above-mentioned non-patent document). For this reason, there is a problem that the mobility of carriers passing through the inversion type channel in the surface layer of the channel region formed by applying a voltage to the gate electrode is very small, and the channel resistance is large. If the channel length can be made shorter, the channel resistance itself becomes smaller. However, if the channel region is too short, punch-through may occur in the channel region when a high voltage is applied to the drain electrode with the gate electrode and the source electrode grounded, so that the actual channel length is formed to 1 μm or less. This is difficult, and as a result, there is a problem that the on-resistance of the SiC power MOSFET increases.
[0007]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the related art, and has as its object to provide a silicon carbide semiconductor device that is a high withstand voltage field effect transistor having low on-resistance.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a first conductivity type drain region in a silicon carbide semiconductor substrate, a first conductivity type drift region connected to the drain region, and formed on the drift region, A second conductivity type hetero semiconductor region that is heterojunction with the silicon carbide semiconductor; a first conductivity type hetero semiconductor region connected to the second conductivity type hetero semiconductor region and not connected to the drift region; A gate insulating film formed on the surface of the hetero-type semiconductor region of the type and extending to the drift region and the hetero-type semiconductor region of the first conductivity type; a gate electrode formed on the gate insulating film; A drain electrode in contact therewith; and a source electrode in contact with the first conductivity type hetero semiconductor region.
[0009]
【The invention's effect】
According to the present invention, it is possible to provide a silicon carbide semiconductor device which is a high withstand voltage field effect transistor having low on-resistance.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0011]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The polytype of silicon carbide (SiC) used in the present embodiment is typically 4H, but other polytypes such as 6H and 3C may be used. In addition, although an example in which polycrystalline silicon is used for the hetero semiconductor region has been described, the material for forming the hetero semiconductor region is not limited to this (details will be described later). Further, in this embodiment, the silicon carbide semiconductor device has a structure in which the drain electrode is formed on the back surface of the semiconductor substrate and the source electrode is arranged on the surface of the substrate and current flows vertically in the element. The present invention can also be applied to a silicon carbide semiconductor device having a structure in which a current flows in the lateral direction by arranging on the substrate surface in the same manner as the source electrode. In the present embodiment, for example, the configuration in which the drain region 10 is N-type has been described. However, the configuration may be such that the drain region 10 is P-type.
[0012]
Needless to say, the present invention includes modifications without departing from the gist of the present invention.
[0013]
Embodiment 1
FIG. 1 shows a first embodiment of a silicon carbide semiconductor device according to the present invention. N to be the drain region ⁺ N on the SiC substrate 10 ⁻ The type epitaxial region 20 is stacked. A predetermined region on the epitaxial region 20 has P ⁻ Form polycrystalline silicon layer 60 is formed. P ⁻ The type polycrystalline silicon layer 60 and the epitaxial region 20 have a hetero junction, and an energy barrier 140 exists at the junction interface as shown in the energy band diagram of FIG. Also, N ⁻ In a predetermined region on the p-type epitaxial region 20, P ⁻ N connected to the polycrystalline silicon layer 60 ⁺ Form polycrystalline silicon layer 50 is formed. Furthermore, P ⁻ Gate insulating film 30 is formed on the surface of type polycrystalline silicon layer 60. The gate insulating film 30 has at least the drift region 20 and N ⁺ It extends to the mold polycrystalline silicon layer 50. A gate electrode 40 is formed on the gate insulating film 30. N ⁺ Type polycrystalline silicon layer 50 is connected to source electrode 80. N ⁺ A drain electrode 90 is formed on the back surface of the type SiC substrate 10.
[0014]
This silicon carbide semiconductor device is used by grounding source electrode 80 and applying positive voltage Vd to drain electrode 90. At this time, if the gate electrode 40 is grounded, the characteristics of the element become P ⁻ Bias characteristics of the heterojunction diode between the polysilicon layer 60 and the SiC epitaxial region 20.
[0015]
That is, a depletion layer extends toward the epitaxial region 20 according to the drain voltage Vd. On the other hand, P ⁻ In the polycrystalline silicon layer 60, electrons as minority carriers cannot accumulate at the energy barrier 140 and accumulate at the junction interface. FIG. 14 shows this state. The lines of electric force corresponding to the depletion layer extending to the epitaxial region 20 end at the electron accumulation layer, and P ⁻ The electric field is shielded on the type polycrystalline silicon layer 60 side. Therefore, P first ⁻ The type polycrystalline silicon layer 60 does not cause a breakdown, and a current starts to flow from the drain electrode 90 to the source electrode 80 only when the drain voltage Vd reaches the predetermined voltage Vb.
[0016]
In the reverse bias characteristics of the heterojunction diode as described above, P ⁻ Experiments have confirmed that a withstand voltage of 300 V or more can be ensured even when the thickness of the polycrystalline silicon layer 60 is reduced to, for example, about 200 °. Therefore, in the silicon carbide semiconductor device using the structure of the present invention, even if the thickness of hetero semiconductor region 60 is reduced, the above P ⁻ On the side of the type polycrystalline silicon layer 60, there is no possibility of punch-through due to the effect of shielding the electric field, and the channel length can be reduced to at least the thickness of the hetero semiconductor region 60, for example, about 200 °. It is possible to do.
[0017]
On the other hand, when a positive voltage is applied to the gate electrode 40, P ⁻ Type polycrystalline silicon layer 60 is in a strong inversion state and N ⁺ A mold layer is formed. Furthermore, P ⁻ An electric field acts on the heterojunction interface between the polycrystalline silicon layer 60 and the SiC epitaxial region 20, and the concentration of the electric field reduces the thickness of the energy barrier formed by the heterojunction surface. FIG. 15 shows this state. The energy level shown by the dotted line is before the gate voltage is applied, and that of the solid line is after the gate voltage is applied. As a result, even if the drain voltage Vd is equal to or lower than the predetermined voltage Vb, a tunnel phenomenon occurs and current starts to flow.
[0018]
That is, the silicon carbide semiconductor device according to the present invention controls the current between drain electrode 90 and source electrode 80 by maintaining drain voltage Vd at Vb or lower and applying a positive voltage to gate electrode 40 in this state. Is what you do.
[0019]
That is, the silicon carbide semiconductor device of the first embodiment includes a first conductivity type drain region 10 in a silicon carbide semiconductor substrate, a first conductivity type drift region 20 formed to be connected to drain region 10, A second conductivity type hetero semiconductor region 60 formed in a predetermined region on the drift region 20 and heterojunction with the silicon carbide semiconductor, and formed to be connected to the second conductivity type hetero semiconductor region 60. Is formed on the surface of the first conductivity type hetero semiconductor region 50 and the second conductivity type hetero semiconductor region 60 which are not connected, and is formed at least to the drift region 20 and the first conductivity type hetero semiconductor region 50. A film 30, a gate electrode 40 formed on the gate insulating film 30, a drain electrode 90 in contact with the drain region 10, and a first conductive type hetero-half. Characterized in that a source electrode 80 in contact with the body region 50.
[0020]
Next, an example of a method for manufacturing the silicon carbide semiconductor device of the first embodiment will be described with reference to the cross-sectional views of FIGS.
[0021]
First, in the step of FIG. ⁺ For example, when the impurity concentration is 10 ¹⁴ -10 ¹⁸ cm ^-3 , N having a thickness of 1 to 100 μm ⁻ Type SiC epitaxial region 20 is formed.
[0022]
In the step of FIG. 10B, sacrificial oxidation is performed on the epitaxial region 20, and after removing the sacrificial oxide film, a CVD oxide film of, for example, about 0.01 to 10 μm is deposited and patterned to form an insulating film. 70 is formed.
[0023]
In the step of FIG. 10C, a polycrystalline silicon layer is deposited using a low pressure CVD method to a thickness of, for example, about 0.1 to 10 μm. Then, a desired impurity is introduced into this polycrystalline silicon layer, and P ⁻ Type polycrystalline silicon layer 60, N ⁺ Form polycrystalline silicon layers 50 are formed. In this method, a highly doped depo film is deposited further on the deposited polycrystalline silicon layer, and impurities in the depo film are thermally diffused into the polycrystalline silicon layer by a heat treatment at about 600 to 1000 ° C. Alternatively, the impurity may be directly introduced into the polycrystalline silicon layer by ion implantation. In addition, in order to improve the mobility of carriers in the polycrystalline silicon layer, for example, the polycrystalline silicon layer may be annealed to increase the size of single-crystal or polycrystalline grains. Further, the polycrystalline silicon layer may be crystallized by irradiating the polycrystalline silicon layer with laser light.
[0024]
In the step of FIG. 10D, for example, a CVD oxide film is deposited to form a gate insulating film 30, and a polycrystalline silicon layer is again formed on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10 μm by low pressure CVD. It is deposited using a method. Thereafter, desired impurities are introduced into the polycrystalline silicon layer 40, and patterning is performed to form the gate electrode 40.
[0025]
In the step of FIG. ⁺ A source electrode 80 is formed so as to be in contact with the mold polycrystalline silicon layer 50, a metal film is deposited as a drain electrode 90 on the back surface of the SiC substrate 10, and heat-treated at, for example, about 600 to 1300 ° C. to form an ohmic electrode.
[0026]
Thus, the silicon carbide semiconductor device shown in FIG. 1 is completed.
[0027]
In this silicon carbide semiconductor device, a high-speed / high-withstand-voltage switching element can be manufactured with a simple configuration by using a heterojunction between SiC and a hetero semiconductor. The junction interface between the hetero semiconductor region 60 where the channel is formed and the gate insulating film 30 has few levels, and carriers can pass through the channel without being affected by the interface level. Furthermore, even if the thickness of the hetero semiconductor region 60 serving as a channel is reduced, punch-through does not occur, and the channel length (from the drift region 20 to the hetero semiconductor region 50 of the first conductivity type, the second conductivity type hetero semiconductor region 50). Since the length of the semiconductor region 60 can be reduced to, for example, 200 °, the channel resistance can be significantly reduced.
[0028]
Further, in the present semiconductor device, introduction of impurities by high-energy ion implantation is not required in manufacturing a basic element structure. As a result, the impurity activation annealing at 1500 ° C. or higher, which also serves as the recovery of the crystallinity, is unnecessary, and the load on the manufacturing process can be reduced, and the deterioration of the surface morphology caused by the high-temperature annealing can be avoided.
[0029]
In the prior art of the above-mentioned patent document, P ⁻ N for mold base area ⁻ In order to form a deep diffusion region in the SiC epitaxial region, it is necessary to form a deep diffusion region. For that purpose, it is indispensable to introduce impurities by high-energy ion implantation. When high-energy ion implantation is performed, defects are generated in the SiC epitaxial region, which is likely to cause an increase in leak current. In addition, high-temperature annealing of, for example, 1500 ° C. or more is required to activate impurities that also serves to recover crystallinity, but there is a problem that surface morphology deteriorates after high-temperature annealing. According to the present invention, it is possible to solve such a problem and to provide a normally-off voltage-driven silicon carbide semiconductor device with a simple manufacturing process.
[0030]
Further, an insulating electric field relaxation layer 70 is formed on a part of the surface of the drift region 20 of the first conductivity type facing the gate electrode 40 via the gate insulating film 30. With such a structure, the electric field applied to the heterojunction between the hetero semiconductor region 60 and the drift region 20 (or the high-concentration semiconductor region 100) is reduced by the insulating electric field relaxation layer 70. In addition, the leakage current can be reduced.
[0031]
Further, the electric field applied to the gate insulating film 30 is reduced by the depletion layer extending from the junction interface between the insulating electric field alleviating layer 70 and the drift region 20 to the drift region 20, so that the reliability of the gate insulating film is improved.
[0032]
Furthermore, in this example, it is not necessary to introduce impurities by high-energy ion implantation, which is indispensable for forming the second conductivity type electric field relaxation region 110. As a result, it is not necessary to perform the impurity activation annealing at 1500 ° C. or higher that also serves to recover the crystallinity, so that the load on the manufacturing process can be reduced and the deterioration of the surface morphology caused by the high-temperature annealing can be avoided.
[0033]
Note that as a condition for forming a heterojunction with silicon carbide to function as a switching element, the band gap of the hetero semiconductor region needs to be smaller than the band gap of silicon carbide. Conversely, when the band gap of the hetero semiconductor region is larger than the band gap of silicon carbide, the two form a heterojunction but do not function as a switching element. Therefore, hetero semiconductor regions 60 and 50 that are heterojunction with the silicon carbide semiconductor are made of a semiconductor material having a smaller band gap than silicon carbide, and are made of, for example, at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon. And That is, these materials have a smaller band gap than silicon carbide and form a heterojunction with silicon carbide. Therefore, in the silicon carbide semiconductor device according to the present invention, when these materials are used for the hetero semiconductor region, the above-described effects are easily obtained. In the case of single crystal silicon, amorphous silicon, or polycrystalline silicon, deposition on a silicon carbide substrate, or oxidation, patterning, selective etching, selective conductivity control, or the like is easy.
[0034]
Embodiment 2
FIG. 2 shows a second embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. ⁻ The region where the polycrystalline silicon layer 60 is adjacent to the gate insulating film 30 is ⁺ The high-concentration SiC region 100 is used.
[0035]
P ⁻ N-type polycrystalline silicon layer ⁺ Heterojunction with the SiC region 100 ⁺ In addition to a large amount of carriers in the SiC region 100, ⁺ The extension of the depletion layer to the type SiC region 100 is reduced, and the thickness of the energy barrier is reduced. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0036]
That is, in the silicon carbide semiconductor device of the second embodiment, in addition to the effect described in the first embodiment, an effect that the controllability of the element main current by the gate voltage is improved. At this time, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Although the breakdown voltage with the type SiC region 100 is low, N ⁻ Since a depletion layer extends in the p-type epitaxial region 20, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in drain withstand voltage can be prevented. As described above, in the second embodiment, a portion of the first conductive type drift region 20 facing the gate electrode 40 via the gate insulating film 30 has the first conductive type having at least an impurity concentration higher than that of the drift region 20. A high-concentration semiconductor region 100 of the first conductivity type is formed, and the high-concentration semiconductor region 100 of the first conductivity type is in contact with the hetero semiconductor region 60 of the second conductivity type. As described above, by forming the first conductive type high-concentration semiconductor region 100 so as to be in contact with the hetero semiconductor region 60, the high-concentration semiconductor region 100 has a large amount of carriers, The extension of the depletion layer to the region 100 is reduced, and the thickness of the energy barrier is reduced. As a result, in addition to the above effects, a tunnel current of the barrier can be made to flow at a low gate voltage, and control of the main current by the gate voltage becomes easy.
[0037]
Embodiment 3
FIG. 3 shows a third embodiment of the silicon carbide semiconductor device according to the present invention. The difference in configuration from FIG. ⁺ In the portion of the SiC epitaxial region 20 below the p-type polysilicon layer 50, the P ⁺ That is, the SiC electric field relaxation region 110 is disposed.
[0038]
In this example, compared with the electric field shield by the field plate effect shown in the second embodiment, P ⁺ Type SiC electric field relaxation region 110 to N ⁻ The depletion layer can be further extended to the type epitaxial region 20. For this reason, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in drain withstand voltage can be prevented.
[0039]
Further, since the electric field applied to the gate insulating film 30 is reduced, the reliability of the gate insulating film is improved.
[0040]
As described above, in the third embodiment, the second conductivity type electric field relaxation region 110 is formed on a part of the surface of the first conductivity type drift region 20 facing the gate electrode 40 via the gate insulating film 30. It is characterized by having been done. The second conductive type electric field relaxation region 110 can be designed so that the breakdown voltage of the element is determined by the reverse breakdown voltage of this region and the drift region 20 in the diode, so that a high breakdown voltage element is obtained.
[0041]
Also, the electric field applied to the gate insulating film 30 is reduced by the depletion layer extending from the junction interface between the electric field relaxation region 110 of the second conductivity type and the drift region 20 to the drift region 20, so that the reliability of the gate insulating film 30 is reduced. improves.
[0042]
In this example, P ⁺ Although the example in which the SiC electric field relaxation region 110 is connected to the source electrode 80 has been described, the connection may not be necessary.
[0043]
Embodiment 4
FIG. 4 shows a fourth embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. ⁺ The point is that the insulating film 70 is formed in the groove 120 formed in the portion of the SiC epitaxial region 20 below the type polycrystalline silicon layer 50. By applying this example, N ⁺ The depletion layer can be extended from a deeper position with respect to the ⁻ Type polycrystalline silicon layer 60 and N ⁺ The electric field applied to the junction with the type SiC region 100 is easily shielded. As a result, a decrease in drain withstand voltage can be effectively prevented. Further, since the electric field applied to the gate insulating film 30 is reduced, the reliability of the gate insulating film 30 is improved.
[0044]
In the fabrication of this example, unlike Embodiment 3, it is not necessary to introduce impurities by high-energy ion implantation. As a result, the impurity activation annealing at 1500 ° C. or higher, which also serves as the recovery of the crystallinity, is not required, and the load on the manufacturing process can be reduced, and the deterioration of the surface morphology caused by the high-temperature annealing can be avoided.
[0045]
Embodiment 5
FIG. 5 shows a fifth embodiment of the silicon carbide semiconductor device according to the present invention. N to be the drain region ⁺ N on the type SiC substrate 10 ⁻ The type epitaxial region 20 is stacked. A groove 120 having a predetermined depth is formed in a predetermined region of the surface portion of the epitaxial region 20. Then, along the groove 120, P ⁻ Form polycrystalline silicon layer 60 is formed. P ⁻ The type polycrystalline silicon layer 60 and the SiC epitaxial region 20 have a heterojunction, and an energy barrier 140 exists at the junction interface as shown in the energy band diagram of FIG. Also, along the groove 120, N ⁺ Type polycrystalline silicon layer 50 is P ⁻ It is stacked on the mold polycrystalline silicon layer 60.
[0046]
The gate electrode 40 is formed in the groove 120 with the gate insulating film 30 interposed therebetween. N ⁺ Type polycrystalline silicon layer 50 is connected to source electrode 80. N ⁺ A drain electrode 90 is formed on the back surface of the type SiC substrate 10.
[0047]
As described above, in the fifth embodiment, the first conductivity type drain region 10 in the silicon carbide semiconductor substrate, the first conductivity type drift region 20 formed to be connected to drain region 10, and drift region 20 A trench 120 formed in a predetermined region of the surface layer portion and having a predetermined depth, and a second conductivity type hetero semiconductor formed in a predetermined region on drift region 20 along trench 120 and heterojunction with the silicon carbide semiconductor A region 60, a first conductivity type hetero semiconductor region 50, which is also formed on the second conductivity type hetero semiconductor region 60 along the trench 120, and a gate insulating film 30 in the trench 120. The semiconductor device is provided with a gate electrode 40 to be filled, a drain electrode 90 in contact with the drain region 10, and a source electrode 80 in contact with the first conductivity type hetero semiconductor region 50.
[0048]
Therefore, in addition to the effects described in the first embodiment, the area efficiency of the device can be increased by the trench gate structure, and the on-resistance can be reduced and the device can be miniaturized. Further, since the second conductivity type hetero semiconductor region 60 and the first conductivity type hetero semiconductor region 50 can be stacked, the thickness of the second conductivity type hetero semiconductor region 60 can be easily reduced, and the channel length can be increased. This is an effective structure to shorten the length.
[0049]
Furthermore, by making the gate insulating film 30 orthogonal to the heterojunction interface direction, the length of the electric force lines from the gate electrode 40 to the heterojunction interface can be shortened. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode 40 can be further improved. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0050]
The operation of the silicon carbide semiconductor device is basically the same as that of the first embodiment shown in FIG. That is, the source electrode 80 is grounded, and a positive voltage Vd is applied to the drain electrode 90 for use. At this time, if the gate electrode 40 is grounded, the characteristics of the device become P ⁻ Bias characteristics of the heterojunction diode between the polysilicon layer 60 and the SiC epitaxial region 20.
[0051]
On the other hand, when a positive voltage is applied to the gate electrode 40, P ⁻ Type polycrystalline silicon layer 60 is in a strong inversion state, and N ⁺ A mold layer is formed. Furthermore, P ⁻ An electric field acts on the heterojunction interface between the polycrystalline silicon layer 60 and the SiC epitaxial region 20, and the concentration of the electric field reduces the thickness of the energy barrier formed by the heterojunction surface. As a result, even if the drain voltage Vd is equal to or lower than the predetermined voltage Vb, a tunnel phenomenon occurs and current starts to flow.
[0052]
There are two structural differences between the first embodiment shown in FIG. 1 and the fifth embodiment shown in FIG. The first is P ⁻ Type polycrystalline silicon layer 60 and N ⁺ The point is that they are formed by laminating the type polycrystalline silicon layer 50. The second is P ⁻ Type polycrystalline silicon layer 60 and N ⁺ The point is that a trench 120 penetrating the mold polycrystalline silicon layer 50 in the depth direction is formed, and a trench gate structure for forming the gate electrode 40 in the trench 120 is formed.
[0053]
By applying the trench gate structure in this example, the area efficiency of the device can be increased, the on-resistance can be reduced, and the device can be miniaturized. Also, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the polycrystalline silicon layer 50 can be stacked, P ⁻ It is easy to make the thickness of the polycrystalline silicon layer 60 thin, and this is an effective structure for shortening the channel length.
[0054]
Furthermore, by making the gate insulating film perpendicular to the heterojunction interface direction, the length of the line of electric force from the gate electrode to the heterojunction interface can be shortened. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode can be further improved. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0055]
Next, an example of a method for manufacturing the silicon carbide semiconductor device of the fifth embodiment will be described with reference to the cross-sectional views of FIGS.
[0056]
First, in the step of FIG. ⁺ For example, when the impurity concentration is 10 ¹⁴ -10 ¹⁸ cm ^-3 , N having a thickness of 1 to 100 μm ⁻ Type SiC epitaxial region 20 is formed.
[0057]
In the step of FIG. 11B, sacrificial oxidation is performed on the epitaxial region 20, and after removing the sacrificial oxide film, the polycrystalline silicon layer is formed to a thickness of, for example, about 0.1 to 10 μm using a low pressure CVD method. accumulate. Then, a desired impurity is introduced into this polycrystalline silicon layer, and P ⁻ The type polycrystalline silicon layer 60 is used. Next, the polycrystalline silicon layer is again formed to a thickness of about 0.1 to ⁻ It is laminated on the mold polycrystalline silicon layer 60. At this time, desired impurities are introduced into the deposited polysilicon layer to ⁺ A type polycrystalline silicon layer 50 is formed.
[0058]
As a method for introducing a desired impurity into the polycrystalline silicon layer, a highly doped depot film is deposited on the deposited polycrystalline silicon layer, and the deposited film is heat-treated at about 600 to 1000 ° C. The impurities therein may be thermally diffused into the polycrystalline silicon layer, or the impurities may be directly introduced into the polycrystalline silicon layer by ion implantation. In addition, in order to improve the mobility of carriers in the polycrystalline silicon layer, for example, the polycrystalline silicon layer may be annealed to increase the size of single-crystal or polycrystalline grains. Further, the polycrystalline silicon layer may be crystallized by irradiating the polycrystalline silicon layer with laser light.
[0059]
In the step of FIG. ⁺ Type polycrystalline silicon layer 50 and P ⁻ N through the polycrystalline silicon layer 60 in the depth direction. ⁻ A groove 120 reaching the epitaxial region 20 and having a depth of, for example, 0.1 to 10 μm is formed.
[0060]
In the step of FIG. 11D, for example, a CVD oxide film is deposited to form a gate insulating film 30, and a polycrystalline silicon layer is again formed on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10 μm by low pressure CVD. It is deposited using a method. Thereafter, desired impurities are introduced into this polycrystalline silicon layer. Next, the gate electrode 40 is formed in the groove 120 by patterning the polycrystalline silicon layer.
[0061]
In the step of FIG. ⁺ A source electrode 80 is formed so as to be in contact with the mold polycrystalline silicon layer 50, a metal film is deposited as a drain electrode 90 on the back surface of the SiC substrate 10, and heat-treated at, for example, about 600 to 1300 ° C. to form an ohmic electrode.
[0062]
Thus, the silicon carbide semiconductor device shown in FIG. 5 is completed.
[0063]
Embodiment 6
FIG. 6 shows a sixth embodiment of the silicon carbide semiconductor device according to the present invention. The difference in configuration from FIG. ⁻ N in the portion of the SiC epitaxial region 20 under the type polycrystalline silicon layer 60 ⁺ That is, the type SiC region 100 is arranged.
[0064]
P ⁻ N-type polycrystalline silicon layer ⁺ Heterojunction with the SiC region 100 ⁺ In addition to a large amount of carriers in the SiC region 100, ⁺ The extension of the depletion layer to the type SiC region 100 is reduced, and the thickness of the energy barrier is reduced. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0065]
That is, in the silicon carbide semiconductor device of the sixth embodiment, in addition to the effect described in the fifth embodiment, an effect that the controllability of the element main current by the gate voltage is improved.
[0066]
At this time, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Although the breakdown voltage with the type SiC region 100 is low, N ⁻ Since a depletion layer extends in the p-type epitaxial region 20, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in drain withstand voltage can be prevented.
[0067]
Embodiment 7
FIG. 7 shows a seventh embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration in FIG. ⁺ That is, the SiC electric field relaxation region 110 is disposed.
[0068]
In this example, compared with the electric field shield by the field plate effect shown in the sixth embodiment, P ⁺ Type SiC electric field relaxation region 110 to N ⁻ The depletion layer can be further extended to the type epitaxial region 20. For this reason, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in drain withstand voltage can be prevented.
[0069]
Further, the electric field applied to the gate insulating film 30 at the bottom of the trench 120 is reduced, so that the reliability of the gate insulating film is improved.
[0070]
In this example, P ⁺ Type SiC electric field relaxation region 110 may be connected to source electrode 80 in a depth direction (not shown).
[0071]
Embodiment 8
FIG. 8 shows an eighth embodiment of the silicon carbide semiconductor device according to the present invention. N to be the drain region ⁺ N on the type SiC substrate 10 ⁻ The type epitaxial region 20 is stacked. A groove 120 having a predetermined depth is formed in a predetermined region on the epitaxial region 20. ⁻ Form polycrystalline silicon layer 60 is formed. P ⁻ The type polycrystalline silicon layer 60 and the SiC epitaxial region 20 have a heterojunction, and an energy barrier 140 exists at the junction interface as shown in the energy band diagram of FIG. In addition, this P ⁻ N through the polycrystalline silicon layer 60 ⁺ Form polycrystalline silicon layer 60 is formed. Furthermore, P ⁻ Gate insulating film 30 is formed on the surface of type polycrystalline silicon layer 60. The gate insulating film 30 has at least the drift region 20 and N ⁺ It extends to the mold polycrystalline silicon layer 50. A gate electrode 40 is formed on the gate insulating film 30. N ⁺ Type polycrystalline silicon layer 50 is connected to source electrode 80. N ⁺ A drain electrode 90 is formed on the back surface of the type SiC substrate 10.
[0072]
That is, in the eighth embodiment, first conductivity type drain region 10 in the silicon carbide semiconductor substrate, first conductivity type drift region 20 formed to be connected to drain region 10, and surface layer of drift region 20. A trench 120 formed in a predetermined region of the portion and having a predetermined depth, a second conductivity type hetero semiconductor region 60 formed in trench 120 and heterojunction with the silicon carbide semiconductor, and a second conductivity type in trench 120 The first conductivity type hetero semiconductor region 50 formed via the hetero semiconductor region 60 and the second conductivity type hetero semiconductor region 60 are formed on the surface of at least the drift region 20 and the first conductivity type hetero semiconductor region. A gate insulating film 30 extending up to 50; a gate electrode 40 formed on the gate insulating film 30; a drain electrode 90 contacting the drain region 10; Characterized in that a source electrode 80 in contact with the hetero semiconductor region 50 to.
[0073]
Therefore, in addition to the effects described in the first embodiment, the electric field applied to the gate insulating film 30 is reduced by the hetero semiconductor region 60 in the trench 120, so that the reliability of the gate insulating film 30 is improved. In addition, by making the gate insulating film 30 perpendicular to the heterojunction interface direction, the length of the line of electric force from the gate electrode 40 to the heterojunction interface can be shortened. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode 40 can be further improved. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0074]
The operation of the silicon carbide semiconductor device is basically the same as that of the first embodiment shown in FIG. That is, the source electrode 80 is grounded, and a positive voltage Vd is applied to the drain electrode 90 for use. At this time, if the gate electrode 40 is grounded, the characteristics of the device become P ⁻ Bias characteristics of the heterojunction diode between the polysilicon layer 60 and the SiC epitaxial region 20.
[0075]
On the other hand, when a positive voltage is applied to the gate electrode 40, P ⁻ Type polycrystalline silicon layer 60 is in a strong inversion state, and N ⁺ A mold layer is formed. Furthermore, P ⁻ An electric field acts on the heterojunction interface between the polycrystalline silicon layer 60 and the SiC epitaxial region 20, and the concentration of the electric field reduces the thickness of the energy barrier formed by the heterojunction surface. As a result, even if the drain voltage Vd is equal to or lower than the predetermined voltage Vb, a tunnel phenomenon occurs and current starts to flow.
[0076]
The structural difference between the first embodiment shown in FIG. 1 and the fifth embodiment shown in FIG. 5 is that a groove 120 is formed and P ⁻ The point is that the mold polycrystalline silicon layer 60 is formed.
[0077]
By applying the structure in this example, the electric field applied to the gate insulating film 30 is reduced by the hetero semiconductor region 60 in the trench 120, so that the reliability of the gate insulating film 30 is improved. In addition, by making the gate insulating film 30 perpendicular to the heterojunction interface direction, the length of the line of electric force from the gate electrode 40 to the heterojunction interface can be shortened. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode 40 can be further improved. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0078]
Next, an example of a method for manufacturing the silicon carbide semiconductor device of the eighth embodiment will be described with reference to the cross-sectional views of FIGS.
[0079]
First, in the step of FIG. ⁺ For example, when the impurity concentration is 10 ¹⁴ -10 ¹⁸ cm ^-3 , N having a thickness of 1 to 100 μm ⁻ Type SiC epitaxial region 20 is formed.
[0080]
In the step of FIG. 12B, a groove 120 having a depth of, for example, 0.1 to 10 μm is formed.
[0081]
In the step shown in FIG. 12C, sacrificial oxidation is performed on the epitaxial region 20, and after removing the sacrificial oxide film, the polycrystalline silicon layer 60 is formed to a thickness of, for example, about 0.1 to 10 μm using a low pressure CVD method. Deposit. Then, a desired impurity is introduced into this polycrystalline silicon layer, and P ⁻ Type polycrystalline silicon layer. In this method, a highly doped depo film is deposited further on the deposited polycrystalline silicon layer, and a heat treatment at about 600 to 1000 ° C. is performed to remove impurities in the depo film into the polycrystalline silicon layer. The impurity may be diffused or introduced directly into the polycrystalline silicon layer by ion implantation. In addition, in order to improve the mobility of carriers in the polycrystalline silicon layer, for example, the polycrystalline silicon layer may be annealed to increase the size of single-crystal or polycrystalline grains. Further, the polycrystalline silicon layer may be crystallized by irradiating the polycrystalline silicon layer with laser light.
[0082]
In the step of FIG. 12D, the polycrystalline silicon layer 60 is subjected to mechanical chemical polishing using, for example, a CMP method, and the polycrystalline silicon layer 60 is left inside the groove 120. Next, P in the groove 120 ⁻ A predetermined impurity is introduced into a predetermined region of the polycrystalline silicon layer 60 to a predetermined depth, and N ⁺ A type polycrystalline silicon layer 50 is formed.
[0083]
In the step of FIG. 12E, for example, a CVD oxide film is deposited to form a gate insulating film 30, and a polycrystalline silicon layer is again formed on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10. It is deposited using a method. After that, desired impurities are introduced into the polycrystalline silicon layer 40. Next, the gate electrode 40 is formed by patterning the polycrystalline silicon layer 40.
[0084]
In the step of FIG. ⁺ A source electrode 80 is formed so as to be in contact with the mold polycrystalline silicon layer 50, a metal film is deposited as a drain electrode 90 on the back surface of the SiC substrate 10, and heat-treated at, for example, about 600 to 1300 ° C. to form an ohmic electrode.
[0085]
Thus, the silicon carbide semiconductor device shown in FIG. 8 is completed.
[0086]
Embodiment 9
FIG. 9 shows a ninth embodiment of a silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. 8 is that the SiC epitaxial region 20 under the gate insulating film has N ⁺ That is, the high-concentration SiC region 100 is disposed.
[0087]
P ⁻ N-type polycrystalline silicon ⁺ Heterojunction with the SiC region 100 ⁺ In addition to a large amount of carriers in the SiC region 100, ⁺ The extension of the depletion layer to the type SiC region 100 is reduced, and the thickness of the energy barrier is reduced. As a result, the tunnel current of the barrier can flow at a low gate voltage, and the control of the main current by the gate voltage becomes easy.
[0088]
That is, in the silicon carbide semiconductor device of the ninth embodiment, in addition to the effect described in the eighth embodiment, an effect that the controllability of the element main current by the gate voltage is improved is obtained. At this time, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Pressure resistance with the SiC region 100 is low, ⁻ Type polycrystalline silicon layer 60 and N ⁻ N from the junction interface of the epitaxial region 20 ⁻ Since a depletion layer extends in the p-type epitaxial region 20, P ⁻ Type polycrystalline silicon layer 60 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in drain withstand voltage can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing Embodiment 1 of the present invention.
FIG. 2 is a sectional view showing Embodiment 2 of the present invention.
FIG. 3 is a sectional view showing Embodiment 3 of the present invention.
FIG. 4 is a sectional view showing a fourth embodiment of the present invention.
FIG. 5 is a sectional view showing a fifth embodiment of the present invention.
FIG. 6 is a sectional view showing a sixth embodiment of the present invention.
FIG. 7 is a sectional view showing a seventh embodiment of the present invention.
FIG. 8 is a sectional view showing Embodiment 8 of the present invention.
FIG. 9 is a sectional view showing a ninth embodiment of the present invention.
FIG. 10 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.
FIG. 11 is a sectional view showing a manufacturing process according to a fifth embodiment of the present invention.
FIG. 12 is a sectional view showing a manufacturing process according to an eighth embodiment of the present invention.
FIG. 13 is an energy band diagram of Si and 4H—SiC.
FIG. 14 is an energy band diagram of Si and 4H-SiC (when a drain voltage is applied and a gate voltage is off).
FIG. 15 is an energy band diagram of Si and 4H-SiC (when a drain voltage is applied and a gate voltage is on).
[Explanation of symbols]
10 ... N ⁺ Type SiC substrate
20 ... N ⁻ Type SiC epitaxial region (drift region)
30 ... Gate insulating film
40 ・ ・ ・ Gate electrode
50 ... N ⁺ Type polycrystalline silicon
60 ... P ⁻ Type polycrystalline silicon
70 ... insulating film
80 Source electrode
90 ・ ・ ・ Drain electrode
100 ... N ⁺ Type SiC region
110 ... P ⁺ Type SiC region
120 ... groove
130 ... interlayer film
140 ... heterojunction barrier
150 ... P ⁻ Type SiC region
160 ... N ⁺ Type SiC region (source region)
170 ・ ・ ・ Channel region

Claims (9)

A first conductivity type drain region in the silicon carbide semiconductor substrate, a first conductivity type drift region connected to the drain region, and a predetermined region on the drift region; A second conductivity type hetero semiconductor region to be joined; a first conductivity type hetero semiconductor region formed so as to be connected to the second conductivity type hetero semiconductor region and not connected to the drift region; A gate insulating film formed on the surface of the hetero semiconductor region of the type, extending at least to the drift region and the hetero semiconductor region of the first conductivity type; a gate electrode formed on the gate insulating film; A silicon carbide semiconductor device comprising: a drain electrode in contact with a drain region; and a source electrode in contact with the first conductivity type hetero semiconductor region. A first conductivity type drain region in the silicon carbide semiconductor substrate, a first conductivity type drift region connected to the drain region, and a predetermined depth formed in a predetermined region of a surface portion of the drift region; A second conductive type hetero semiconductor region formed along the groove in a predetermined region on the drift region and heterojunction with a silicon carbide semiconductor; and the second conductive A first conductivity type hetero semiconductor region formed by being stacked on the type hetero semiconductor region, a gate electrode filled in the trench via a gate insulating film, and a drain electrode contacting the drain region, A silicon carbide semiconductor device, comprising: a source electrode in contact with the first conductivity type hetero semiconductor region. A first conductivity type drain region in the silicon carbide semiconductor substrate, a first conductivity type drift region connected to the drain region, and a predetermined depth formed in a predetermined region of a surface portion of the drift region; A second conductive type hetero semiconductor region formed in the groove and heterojunction with the silicon carbide semiconductor; and a first conductive type hetero semiconductor region formed in the groove via the second conductive type hetero semiconductor region. A conductive type hetero semiconductor region, a gate insulating film formed on the surface of the second conductive type hetero semiconductor region, and extending at least to the drift region and the first conductive type hetero semiconductor region; A gate electrode formed on the film, a drain electrode in contact with the drain region, and a source electrode in contact with the first conductivity type hetero semiconductor region ,
A silicon carbide semiconductor device , wherein a hetero junction between the hetero semiconductor region and the drift region of the first conductivity type has a reverse bias characteristic of a hetero junction diode . A part of the drift region of the first conductivity type facing the gate electrode via a gate insulating film, a high-concentration semiconductor region of the first conductivity type having an impurity concentration higher than at least the drift region is formed, 3. The silicon carbide semiconductor device according to claim 1, wherein the first conductive type high-concentration semiconductor region is in contact with the second conductive type hetero semiconductor region. 4. The first electrode facing the gate electrode via a gate insulating film; One At least part of the drift region of the conductivity type has an impurity concentration higher than that of the drift region. One A conductive high-concentration semiconductor region is formed, One The conductive type high concentration semiconductor region is Two 4. The silicon carbide semiconductor device according to claim 3, wherein said silicon carbide semiconductor device is in contact with a conductive type hetero semiconductor region. According to claim 1, wherein said part of said first conductivity type in a surface of the drift region through the gate insulating film for the gate electrode, the electric field relaxation region of the second conductivity type is formed 5. The silicon carbide semiconductor device according to any one of 4 . Some of the first conductivity type in a surface of the drift region through the gate insulating film on the gate electrode, any of claim 1, 2, 4, wherein an insulating electric field relaxation layer is formed Or a silicon carbide semiconductor device according to any one of the preceding claims. The hetero semiconductor region to the silicon carbide semiconductor and heterojunctions, the silicon carbide semiconductor device according to any one of claims 1 to 7, characterized by comprising a semiconductor material having a band gap smaller than the silicon carbide. 9. The silicon carbide semiconductor device according to claim 8, wherein the semiconductor material having a band gap smaller than that of silicon carbide is at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon.

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