JP5593673B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, research has been conducted on GaN-based transistors in which an AlGaN layer and a GaN layer are formed by crystal growth above a substrate. The band gap of GaN is 3.4 eV, which is larger than the band gap of Si (1.2 eV) and the band gap of GaAs (1.4 eV). For this reason, the withstand voltage of GaN-based transistors is high, and it is promising as a high withstand voltage power device for automobiles.

  The structure of the GaN-based transistor includes a horizontal structure in which the source and drain are arranged in parallel to the surface of the substrate, and a vertical structure in which the source and drain are arranged perpendicular to the surface of the substrate.

  In the vertical structure, the current path is three-dimensional, so that the amount of current per chip can be increased as compared with the horizontal structure. In addition, since the drain electrode and the source electrode are located above and below the substrate, it is easy to reduce the chip area even if these areas are increased. Therefore, even if the area of the drain electrode and the source electrode is increased in order to pass a large current, the area of the chip is hardly increased. Furthermore, since the ratio of the metal per chip | tip becomes large, a thermal radiation characteristic improves.

  As a conventional GaN-based vertical transistor structure, a structure in which an n-type GaN layer is formed on a p-type GaN layer and Mg ions are introduced as a p-type impurity in the p-type GaN layer is known.

  However, in general, Mg ions are difficult to activate, and when an n-type GaN layer is formed on a p-type GaN layer, this difficulty in activation becomes significant. Furthermore, Mg ions are likely to migrate during transistor operation. For this reason, it is difficult to control a GaN-based vertical transistor including a p-type GaN layer into which Mg ions are introduced, and it is very difficult to put it into practical use.

Applied Physics Express 1 (2008) 011105 Applied Physics Express 1 (2008) 021104

  An object of the present invention is to provide a semiconductor device capable of easily controlling a vertical transistor and a manufacturing method thereof.

In one embodiment of the semiconductor device, a first semiconductor layer and a second semiconductor layer heterojunction with the first semiconductor layer are provided. Furthermore, a gate electrode for controlling the potential of the heterojunction surface between the first semiconductor layer and the second semiconductor layer, a drain electrode connected to the first semiconductor layer, and the second semiconductor A source electrode connected to the layer. The first semiconductor layer includes a region in which the band gap decreases continuously or stepwise as the distance from the heterojunction surface increases.
In another embodiment of the semiconductor device, a first semiconductor layer and a second semiconductor layer heterojunction with the first semiconductor layer are provided. Furthermore, a gate electrode for controlling the potential of the heterojunction surface between the first semiconductor layer and the second semiconductor layer, a drain electrode connected to the first semiconductor layer, and the second semiconductor A source electrode connected to the layer. The second semiconductor layer includes a first region that is in contact with the heterojunction surface and has a band gap that increases as the distance from the heterojunction surface increases, and a second region that is heterojunction with the first region. Including. The gate electrode also controls the potential of the heterojunction surface between the first region and the second region.

  According to the above semiconductor device or the like, a vertical transistor can be configured without using a p-type GaN layer. For this reason, control can be performed easily.

1 is a diagram illustrating a semiconductor device according to a first embodiment. It is a figure which shows the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the layout of a gate electrode and a source electrode. It is a figure which shows an example of the usage method of a semiconductor device. It is sectional drawing which shows the manufacturing method of the GaN-type vertical transistor which concerns on 2nd Embodiment in process order. FIG. 5B is a cross-sectional view illustrating the manufacturing method of the GaN-based vertical transistor in the order of steps following FIG. 5A. FIG. 5B is a cross-sectional view illustrating the manufacturing method of the GaN-based vertical transistor in the order of steps, following FIG. 5B. It is a figure which shows the structure of a MOCVD apparatus. It is a figure which shows the modification of 2nd Embodiment. It is a figure which shows the result of the simulation and experiment which were performed about 2nd Embodiment. It is a figure which shows the result of the other experiment conducted about 2nd Embodiment. It is a figure which shows the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the result of the simulation and experiment which were performed about 3rd Embodiment. It is a figure which shows the result of the other experiment conducted about 3rd Embodiment. It is a figure which shows the semiconductor device which concerns on 4th Embodiment. It is a figure which shows the result of the simulation and experiment which were performed about 4th Embodiment. It is a figure which shows the result of the other experiment conducted about 4th Embodiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a diagram illustrating the semiconductor device according to the first embodiment.

  In the first embodiment, the semiconductor layer 2 is formed on the semiconductor layer 1 as shown in FIG. The band gap of the semiconductor layer 1 is larger than that of the semiconductor layer 2, and the semiconductor layers 1 and 2 are heterojunction with each other. A drain electrode 10 d is connected to the semiconductor layer 1, and a source electrode 10 s is connected to the semiconductor layer 2. In addition, an opening 9 that penetrates the semiconductor layer 2 and reaches the inside of the semiconductor layer 1 is provided. A gate insulating film 3 is formed along the inner surface of the opening 9, and a gate electrode 10 g is formed thereon. Is formed.

  In the first embodiment configured as described above, the levels of the conduction bands of the semiconductor layers 1 and 2 when no voltage is applied to the gate electrode 10g (when off) are as shown in FIG. It will be something. For this reason, at the time of off, the density of electrons in the semiconductor layer 1 is significantly lower than that in the semiconductor layer 2, and the change in carrier density at the heterojunction surface between the semiconductor layers 1 and 2 is extremely large. For this reason, no current flows between the source electrode 10s and the drain electrode 10d. On the other hand, when a positive voltage is applied to the gate electrode 10g (when turned on), electrons are attracted to the electric field generated by the gate electrode 10g, and the density of electrons in the semiconductor layer 1 is significantly increased. As a result, a current flows between the source electrode 10s and the drain electrode 10d.

  Therefore, the first embodiment functions as a transistor capable of a normally-off operation. Further, it is not necessary to use a p-type GaN layer into which Mg ions are introduced, which is required for a conventional transistor.

  In addition, the heterojunction surface between the semiconductor layers 1 and 2 may prevent the movement of electrons from the semiconductor layer 2 to the semiconductor layer 1 as described above, but prevents the movement of electrons from the semiconductor layer 1 to the semiconductor layer 2. There is no hindrance. That is, the semiconductor layers 1 and 2 include parasitic diodes. Therefore, even when a reverse voltage is applied between the drain electrode 10d and the source electrode 10s, the parasitic diode can return the state to normal.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 2 is a diagram illustrating a semiconductor device according to the second embodiment.

In the second embodiment, as shown in FIG. 2, an AlN layer 18, an n-type AlGaN layer 11, an n-type GaN layer 12, and an n ⁺ GaN layer 14 are formed in this order on a conductive SiC substrate 17. Has been. The AlN layer 18 has a thickness of about 1 nm to 10 μm and functions as a buffer layer. The thickness of the AlGaN layer 11 is about 0.1 μm to 10 μm. The composition of the AlGaN layer 11 is represented by, for example, Al _0.2 Ga _0.8 N. The GaN layer 12 is doped with Si in an amount of about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , and the thickness is preferably about 1 nm to 1 μm. This is because if the thickness is less than 1 nm, a sufficient breakdown voltage cannot be obtained, and if it is greater than 1 μm, the on-state current density decreases due to an increase in on-resistance. The n ⁺ GaN layer 14 is doped with Si at a higher concentration than the AlGaN layer 11 and the GaN layer 12. That is, the n ⁺ GaN layer 14 is doped with Si in an amount of about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The thickness of the n ⁺ GaN layer 14 is about 0.1 to 100 nm.

In addition, an opening 19 that penetrates the n ⁺ GaN layer 14 and the GaN layer 12 and reaches the inside of the AlGaN layer 11 is provided, and a gate insulating film 13 is formed along the inner surface of the opening 19. A gate electrode 20g is formed thereon. The width of the opening 19 is, for example, about 100 nm to 1 μm. As the gate insulating film 13, for example, a silicon nitride film having a thickness of about 1 nm to 1 μm is formed.

Insulating film 16 covering the gate electrode 20g is formed on the n ⁺ GaN layer 14, an opening portion 16x for the source electrode on the n ⁺ GaN layer 14 is formed. A source electrode 20s is formed on the n ⁺ GaN layer 14 in the opening 16x, and a source wiring 15 covering the insulating film 16 is formed on the source electrode 20s. Further, a drain electrode 20 d is formed on the back surface of the SiC substrate 17.

  In this way, one GaN-based vertical transistor is configured. In addition, as shown in FIG. 3A, such GaN-based vertical transistors are provided so as to be arranged in, for example, two directions orthogonal to each other. The planar shape of the source electrode 20s may be other polygons such as an octagon shown in FIG. 3B in addition to the rectangle shown in FIG. 3A, and may include a curve such as a circle. It may be. The source wiring 15 is formed with an opening that exposes a part of the gate electrode 20g (or a gate pad connected to the gate electrode 20g), and the side surface of the opening is insulated.

  In the second embodiment, the AlGaN layer 11 functions in the same manner as the semiconductor layer 1 in the first embodiment, and the GaN layer 12 functions in the same manner as the semiconductor layer 2. Therefore, as in the first embodiment, the transistor functions as a transistor capable of a normally-off operation.

  The semiconductor device according to the second embodiment is mounted on a mounting board 28, for example, as shown in FIG. The gate terminal G provided on the mounting substrate 28 and a part of the gate electrode 20g (or a gate pad connected to the gate electrode 20g) are connected by the gate wire 26, and the source terminal S and the source wiring 15 are connected. The drain electrode 20 d is connected to the drain terminal D through the source wire 27.

  Next, a method for manufacturing the GaN-based vertical transistor as described above will be described. 5A to 5C are cross-sectional views illustrating a method of manufacturing a GaN-based vertical transistor according to the second embodiment in the order of steps.

  First, as shown in FIG. 5A (a), an AlN layer 18 is formed on a SiC substrate 17 by a metal organic chemical vapor deposition (MOCVD) method.

Here, the MOCVD apparatus will be described. FIG. 6 is a diagram showing the configuration of the MOCVD apparatus. A high frequency coil 141 is disposed around the quartz reaction tube 140, and a carbon susceptor 142 for placing the substrate 120 is disposed inside the reaction tube 140. Two gas introduction pipes 144 and 145 are connected to the upstream end of the reaction tube 140 (the left end in FIG. 6), and a compound source gas is supplied. For example, NH ₃ gas is introduced from the gas introduction pipe 144 as an N source gas, and organic group III compound raw materials such as trimethylaluminum (TMA) and trimethylgallium (TMG) are introduced from the gas introduction pipe 145 as a group III element source gas. Is done. Crystal growth is performed on the substrate 120, and excess gas is discharged from the gas discharge pipe 146 to the detoxification tower. When crystal growth by MOCVD is performed in a reduced pressure atmosphere, the gas exhaust pipe 146 is connected to a vacuum pump, and the exhaust port of the vacuum pump is connected to a detoxification tower. The MOCVD apparatus is used not only for forming the AlN layer 18 but also for forming an AlGaN layer 11, a GaN layer 12 and an n ⁺ GaN layer 14 described later.

Conditions for forming the AlN layer 18 are set as follows, for example.
Trimethylaluminum (TMA) flow rate: 0-30 sccm,
Trimethylgallium (TMG) flow rate: 0-30 sccm,
Ammonia (NH ₃ ) flow rate: 5 slm,
n-type impurity: silane (SiH ₄ ),
Pressure: 90 Torr,
Temperature: 1000 ° C

  After the AlN layer 18 is formed, the n-type AlGaN layer 11 is formed on the AlN layer 18 by MOCVD.

The conditions for forming the AlGaN layer 11 are set as follows, for example.
Trimethylaluminum (TMA) flow rate: 0-30 sccm,
Ammonia (NH ₃ ) flow rate: 5 slm,
n-type impurity: silane (SiH ₄ ),
Pressure: 100 Torr,
Temperature: 1100 ° C

  After the AlGaN layer 11 is formed, an n-type GaN layer 12 is formed on the AlGaN layer 11 by MOCVD.

The conditions for forming the GaN layer 12 are set as follows, for example.
Trimethylgallium (TMG) flow rate: 0-50 sccm,
Ammonia (NH ₃ ) flow rate: 20 slm,
n-type impurity: silane (SiH ₄ ),
Pressure: 100 Torr,
Temperature: 1100 ° C

After the GaN layer 12 is formed, an n ⁺ GaN layer 14 is formed on the GaN layer 12 by MOCVD.

The conditions for forming the n ⁺ GaN layer 14 are set as follows, for example.
Trimethylgallium (TMG) flow rate: 0-50 sccm,
Ammonia (NH ₃ ) flow rate: 20 slm,
n-type impurity: silane (SiH ₄ )

After the n ⁺ GaN layer 14 is formed, as shown in FIG. 5A (b), the source electrode 20s is formed on the n ⁺ GaN layer 14 by, for example, a lift-off method. In forming the source electrode 20s, for example, a Ta film is formed, and an Al film is formed thereon.

Next, as shown in FIG. 5A (c), an opening 19 for a gate is formed in the n ⁺ GaN layer 14, the GaN layer 12 and the AlGaN layer 11. In forming the opening 19, for example, a resist pattern that exposes a region where the opening 19 is to be formed is formed, and the n ⁺ GaN layer 14, the GaN layer 12, and the AlGaN layer 11 are used in a predetermined amount by using this resist pattern as a mask. What is necessary is just to etch. Thereafter, the resist pattern is removed.

  Thereafter, as shown in FIG. 5B (d), an insulating film 13a is formed on the entire surface by plasma CVD. For example, a silicon nitride film is formed as the insulating film 13a.

  Subsequently, as shown in FIG. 5B (e), a gate electrode 20g is formed on the insulating film 13a in the opening 19 by, for example, a lift-off method. When forming the gate electrode 20g, for example, an Ni film is formed, and an Au film is formed thereon.

The source electrode 20s may be formed after the insulating film 13a and the gate electrode 20g are formed. In this case, an opening for the source electrode 20s is formed in the insulating film 13a. At the time of selective etching of the insulating film 13a, for example, SF ₆ gas is used as an etching gas.

  Next, as shown in FIG. 5B (f), an insulating film 16a is formed on the entire surface by plasma CVD. For example, a silicon nitride film is formed as the insulating film 16a.

After that, as shown in FIG. 5C (g), the insulating films 13a and 16a are selectively etched to expose the source electrode 20s while maintaining the state where the gate electrode 20g is covered with the insulating films 13a and 16a. At the time of selective etching of the insulating films 13a and 16a, for example, SF ₆ gas is used as an etching gas. The portion connected to the gate wire 26 of the gate electrode 20g is also exposed.

  Subsequently, as shown in FIG. 5C (h), the source wiring 15 in contact with each source electrode 20s is formed on almost the entire surface side except the portion connected to the gate wire 26 of the gate electrode 20g. When the source wiring 15 is formed, for example, an Au film is formed by a plating method.

  Next, the SiC substrate 17 is thinned to a predetermined thickness. At this time, for example, a back surface is polished after a surface protective film is formed on the front surface side of the SiC substrate 17. Thereafter, drain electrode 20 d is formed on the entire back surface of SiC substrate 17. Thereafter, the surface protective film is removed.

  In this way, the semiconductor device can be completed.

A portion of the insulating film 13a below the surface of the n ⁺ GaN layer 14 corresponds to the gate insulating film 13, and a portion of the insulating film 13a above the surface of the n ⁺ GaN layer 14 and the insulating film 16a are the insulating film. It corresponds to 16.

  As shown in FIG. 7, a conductive GaN substrate 37 may be used in place of the SiC substrate 17. In this case, since the AlGaN layer 11 can be directly epitaxially grown on the GaN substrate 37, the AlN layer 18 functioning as a buffer layer becomes unnecessary.

  Here, simulations and experiments performed on the second embodiment will be described. 8A and 8B show the results of various simulations and experiments performed on the second embodiment. This simulation and experiment were performed based on the structure shown in FIG. FIG. 8A (a) shows the result of simulation, and FIG. 8A (b), FIG. 8B (c) and FIG. 8B (d) show the result of actual measurement.

  FIG. 8A (a) shows the relationship between the distance from the lower surface of the AlGaN layer 11 and the electron density. In this simulation, a voltage of 10 V was applied to the drain electrode 20d with reference to the source electrode 20s. The voltage applied to the gate electrode 20g was 0V (off) or 5V (on), and the electron density was calculated. As shown in FIG. 8A (a), when off, the density of electrons in the GaN layer 12 is significantly higher than that in the AlGaN layer 11, and the change in carrier density at the heterojunction surface between them is extremely large. For this reason, no current flows between the source electrode 20s and the drain electrode 20d. On the other hand, when a voltage of 5 V is applied to the gate electrode 20g (when turned on), electrons are attracted to the electric field generated by the gate electrode 20g, and the density of electrons in the AlGaN layer 11 is significantly increased. For this reason, a current flows between the source electrode 20s and the drain electrode 20d.

  FIG. 8A (b) shows the relationship between the voltage applied to the gate electrode 20g (gate voltage Vg) and the density of the current flowing between the source electrode 20s and the drain electrode 20d (source-drain current density Ids). Show. As shown in FIG. 8A (b), a normally-off operation was confirmed. FIG. 8B (c) shows the relationship between the voltage (drain voltage Vd) applied to the drain electrode 20d and the current density Ids when the gate voltage Vg is changed from 0V to 5V. As shown in FIG. 8B (c), current flowed at an appropriate density during the on-operation. FIG. 8B (d) shows the relationship between the drain voltage Vd and the current density Ids when the gate voltage Vg is 0V. As shown in FIG. 8B (d), good diode characteristics were obtained.

(Third embodiment)
Next, a third embodiment will be described. FIG. 9 is a diagram illustrating a semiconductor device according to the third embodiment.

In the third embodiment, as shown in FIG. 9A, an n-type Al _X Ga _{1-X in which} the ratio of Al and Ga changes in the thickness direction between the AlGaN layer 11 and the GaN layer 12. An N layer 21 is provided. As shown in FIG. 9B, in the Al _x Ga _1-x N layer 21, the proportion of Al at the interface with the GaN layer 12 is 20 atomic% (X = 0.2). Then, the closer to the AlGaN layer 11, the lower the Al ratio in a curve, and the Al ratio at the interface with the AlGaN layer 11 is 0 atomic%. Other configurations are the same as those of the second embodiment.

In such a third embodiment, the AlGaN layer 11 and the Al _x Ga _1-x N layer 21 are heterojunction, and the Al _x Ga _1-x N layer 21 and the GaN layer 12 are heterojunction. Therefore, the AlGaN layer 11 functions in the same manner as the semiconductor layer 1 of the first embodiment, and the Al _x Ga _1-x N layer 21 and the GaN layer 12 function in the same manner as the semiconductor layer 2. Further, the Al _x Ga ₁ -xN layer 21 functions in the same manner as the semiconductor layer 1, and the GaN layer 12 functions in the same manner as the semiconductor layer 2. For this reason, it can be said that the structure of the third embodiment is equivalent to a structure in which the energy difference of the conduction band at the heterojunction is larger than that of the second embodiment. Therefore, it is possible to more surely prevent the off-state current than in the second embodiment. That is, it is possible to further reduce the occurrence of power loss due to leakage.

As indicated by broken lines in FIG. 9 (b), the ratio of Al and Ga in the Al _X Ga _1-X N layer 21 may be changed linearly.

The Al _x Ga _1-x N layer 21 can be formed, for example, by changing the amount of TMA and TMG supplied into the reaction tube 140 continuously or stepwise.

  Further, as in the second embodiment, the GaN substrate 37 may be used and the AlN layer 18 may be omitted.

  Here, simulations and experiments performed on the third embodiment will be described. FIG. 10A and FIG. 10B show the results of various simulations and experiments performed on the third embodiment. Similar to the structure shown in FIG. 7, the simulation and experiment were performed based on a structure in which the GaN substrate 37 was used and the AlN layer 18 was omitted. FIG. 10A (a) shows the result of simulation, and FIG. 10A (b), FIG. 10B (c) and FIG. 10B (d) show the result of actual measurement.

FIG. 10A (a) shows the relationship between the distance from the lower surface of the AlGaN layer 11 and the electron density. In this simulation, a voltage of 10 V was applied to the drain electrode 20d with reference to the source electrode 20s. The voltage applied to the gate electrode 20g was 0V (off) or 5V (on), and the electron density was calculated. As shown in FIG. 10A (a), at the time of off, the density of electrons in the GaN layer 12 is significantly higher than that of the Al _X Ga _1-X N layer 21, also, Al _X Ga _1-X N layer 21 The density of electrons in the inside is remarkably higher than that in the AlGaN layer 11, and the change in carrier density at the heterojunction surface between them is extremely large. For this reason, no current flows between the source electrode 20s and the drain electrode 20d. On the other hand, when a voltage of 5 V is applied to the gate electrode 20g (when turned on), electrons are attracted to the electric field generated by the gate electrode 20g, and the density of electrons in the AlGaN layer 11 and the Al _x Ga _1-x N layer 21 is reduced. Remarkably high. For this reason, a current flows between the source electrode 20s and the drain electrode 20d.

  FIG. 10A (b) shows the relationship between the gate voltage Vg and the current density Ids. As shown in FIG. 10A (b), a normally-off operation was confirmed. FIG. 10B (c) shows the relationship between the drain voltage Vd and the current density Ids when the gate voltage Vg is changed from 0V to 5V. As shown in FIG. 10B (c), current flowed at an appropriate density during the on-operation. FIG. 10B (d) shows the relationship between the drain voltage Vd and the current density Ids when the gate voltage Vg is 0V. As shown in FIG. 10B (d), good diode characteristics were obtained.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 11 is a diagram illustrating a semiconductor device according to the fourth embodiment.

In the fourth embodiment, as shown in FIG. 11A, an n-type Al _Y Ga _1-Y N layer 22 in which the ratio of Al and Ga changes in the thickness direction is provided instead of the AlGaN layer 11. It has been. As shown in FIG. 11B, in the Al _Y Ga _1-Y N layer 22, the proportion of Al at the interface with the GaN layer 12 is 20 atomic% (X = 0.2). Then, the closer to the AlN layer 18, the lower the Al ratio, and the Al ratio at the interface with the AlN layer 18 is 0 atomic%. Other configurations are the same as those of the second embodiment.

In such a fourth embodiment, the composition of the lower part of the Al _Y Ga _1-Y N layer 22 is very close to that of GaN, so the on-resistance is lower than in the second embodiment. Therefore, the forward current of the diode increases, and a switching operation with higher speed and less noise becomes possible. Similarly to the second embodiment, a GaN substrate 37 can be used. When the GaN substrate 37 is used, a lattice between the GaN substrate 37 and the Al _Y Ga _1-Y N layer 22 is used. The alignment is very good. For this reason, the crystal orientation is also very good, and higher yield and reliability can be obtained.

Note that, as indicated by a broken line in FIG. 11B, the ratio of Al and Ga in the Al _Y Ga _1-Y N layer 22 may change linearly.

The Al _Y Ga _1-Y N layer 22 can be formed, for example, by changing the amount of TMA and TMG supplied into the reaction tube 140 continuously or stepwise.

  Here, simulations and experiments performed on the fourth embodiment will be described. 12A and 12B show the results of various simulations and experiments performed on the fourth embodiment. Similar to the structure shown in FIG. 7, the simulation and experiment were performed based on a structure in which the GaN substrate 37 was used and the AlN layer 18 was omitted. FIG. 12A (a) shows the result of simulation, and FIG. 12A (b), FIG. 12B (c) and FIG. 12B (d) show the result of actual measurement.

FIG. 12A (a) shows the relationship between the distance from the lower surface of the Al _Y Ga _1-Y N layer 22 and the electron density. In this simulation, a voltage of 10 V was applied to the drain electrode 20d with reference to the source electrode 20s. The voltage applied to the gate electrode 20g was 0V (off) or 5V (on), and the electron density was calculated. As shown in FIG. 12A (a), when off, the density of electrons in the GaN layer 12 is significantly higher than that in the Al _Y Ga _1-Y N layer 22, and the carrier density at the heterojunction surface between them. The change is extremely large. For this reason, no current flows between the source electrode 20s and the drain electrode 20d. On the other hand, when a voltage of 5 V is applied to the gate electrode 20g (when turned on), electrons are attracted to the electric field generated by the gate electrode 20g, and the density of electrons in the Al _Y Ga _1-Y N layer 22 is significantly increased. For this reason, a current flows between the source electrode 20s and the drain electrode 20d.

  FIG. 12A (b) shows the relationship between the gate voltage Vg and the current density Ids. As shown in FIG. 12A (b), a normally-off operation was confirmed. FIG. 12B (c) shows the relationship between the drain voltage Vd and the current density Ids when the gate voltage Vg is changed from 0V to 5V. As shown in FIG. 12B (c), current flowed at an appropriate density during the on-operation. FIG. 12B (d) shows the relationship between the drain voltage Vd and the current density Ids when the gate voltage Vg is 0V. As shown in FIG. 12B (d), good diode characteristics were obtained.

  In any of the embodiments, instead of the GaN layer 12, an AlGaN layer in which the proportion of Al (the proportion of Al atoms relative to the total amount of Al atoms and Ga atoms) is lower than that of the AlGaN layer 11 may be used. Further, instead of the AlGaN layer 11 and the GaN layer 12, an AlInGaN layer may be used. Also in this case, the Al ratio of the AlInGaN layer used instead of the GaN layer 12 is set lower than the Al ratio of the AlInGaN layer used instead of the AlGaN layer 11.

For example, the composition at the heterojunction surface of the semiconductor constituting the first semiconductor layer 1 is expressed as Al _a In _b Ga _1-ab N, and the composition at the heterojunction surface of the semiconductor constituting the second semiconductor layer 2 is It is expressed by Al _c In _d Ga _1-cd N, and it is sufficient that 0 ≦ c <a ≦ 1, 0 ≦ b <1 and 0 ≦ d <1 are satisfied.

Further, an n-type AlGaN layer may be formed as a buffer layer between the AlN layer 18 and the AlGaN layer 11, and an n-type AlGaN layer may be formed as a buffer layer instead of the AlN layer 18. . Furthermore, the semiconductor layer 1, AlGaN layer _{11, Al X Ga 1-X} N layer 21, and Al _Y Ga _1-Y N layer conductivity type, such as 22 may be a p-type semiconductor layer 1, AlGaN layer 11, Al _X Impurities need not be introduced into the Ga _1-X N layer 21, the Al _Y Ga _1-Y N layer 22, and the like.

  In any of the embodiments, the material, thickness, impurity concentration, and the like of the substrate and each layer are not particularly limited. For example, a conductive silicon substrate or the like may be used as the substrate in addition to the conductive SiC substrate and the GaN substrate. In addition, when using a conductive GaN substrate, it is preferable to use a surface having a nonpolar surface. This is to suppress generation of useless two-dimensional electron gas.

  The application of these semiconductor devices is not particularly limited, and can be used as a power source for servers and personal computers, and as parts for automobiles and the like.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A first semiconductor layer;
A second semiconductor layer heterojunction with the first semiconductor layer;
A gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer;
A drain electrode connected to the first semiconductor layer;
A source electrode connected to the second semiconductor layer;
A semiconductor device comprising:

(Appendix 2)
The composition of the semiconductor constituting the first semiconductor layer at the heterojunction surface is represented by Al _a In _b Ga _1-ab N,
The composition of the semiconductor constituting the second semiconductor layer at the heterojunction surface is represented by Al _c In _d Ga _{1 -cd} N,
2. The semiconductor device according to appendix 1, wherein relationships of 0 ≦ c <a ≦ 1, 0 ≦ b <1, and 0 ≦ d <1 are satisfied.

(Appendix 3)
The band gap at the heterojunction surface of the semiconductor constituting the first semiconductor layer is larger than the band gap at the heterojunction surface of the semiconductor constituting the second semiconductor layer. A semiconductor device according to 1.

(Appendix 4)
The second semiconductor layer includes
A first region in contact with the heterojunction surface and having a band gap that increases with distance from the heterojunction surface;
A second region heterojunction with the first region;
Have
The semiconductor device according to appendix 3, wherein the gate electrode also controls a potential of a heterojunction surface between the first region and the second region.

(Appendix 5)
The semiconductor device according to appendix 3 or 4, wherein the first semiconductor layer has a region that is in contact with the heterojunction surface and decreases as the distance from the heterojunction surface increases.

(Appendix 6)
An opening reaching at least the second semiconductor layer to the heterojunction surface is formed,
The semiconductor device according to any one of appendices 1 to 5, wherein the gate electrode is provided in the opening.

(Appendix 7)
The semiconductor device according to appendix 6, further comprising a gate insulating film provided between the gate electrode and the heterojunction surface.

(Appendix 8)
The semiconductor device according to appendix 7, wherein the gate insulating film includes silicon nitride.

(Appendix 9)
Forming a first semiconductor layer and a second semiconductor layer that are heterojunction with each other;
Forming a gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer;
Forming a drain electrode connected to the first semiconductor layer and a source electrode connected to the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising:

(Appendix 10)
The composition of the semiconductor constituting the first semiconductor layer at the heterojunction surface is represented by Al _a In _b Ga _1-ab N,
The composition of the semiconductor constituting the second semiconductor layer at the heterojunction surface is represented by Al _c In _d Ga _{1 -cd} N,
The method for manufacturing a semiconductor device according to appendix 9, wherein the relationships 0 ≦ c <a ≦ 1, 0 ≦ b <1, and 0 ≦ d <1 are satisfied.

1,2: Semiconductor layer 3: a gate insulating film 10 g: gate electrode 10s: Source electrode 10d: drain electrode 11: AlGaN layer 12: GaN layer 13: Gate insulating film 14: n ⁺ GaN layer 21: Al _X Ga _1-X N layer 22: Al _Y Ga _1-Y N layer 37: GaN substrate

Claims (6)

A first semiconductor layer;
A second semiconductor layer heterojunction with the first semiconductor layer;
A gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer;
A drain electrode connected to the first semiconductor layer;
A source electrode connected to the second semiconductor layer;
I have a,
The semiconductor device according to claim 1, wherein the first semiconductor layer includes a region where the band gap decreases continuously or stepwise as the distance from the heterojunction surface increases . A first semiconductor layer;
A second semiconductor layer heterojunction with the first semiconductor layer;
A gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer;
A drain electrode connected to the first semiconductor layer;
A source electrode connected to the second semiconductor layer;
Have
The second semiconductor layer includes
A first region in contact with the heterojunction surface and having a band gap that increases with distance from the heterojunction surface;
A second region heterojunction with the first region;
Including
The gate electrode, the semi-conductor device you characterized by also controlling the potential of the heterojunction surface between the first region and the second region. The composition of the semiconductor constituting the first semiconductor layer at the heterojunction surface is represented by Al _a In _b Ga _1-ab N,
The composition of the semiconductor constituting the second semiconductor layer at the heterojunction surface is represented by Al _c In _d Ga _{1 -cd} N,
3. The semiconductor device according to claim 1, wherein relationships of 0 ≦ c <a ≦ 1, 0 ≦ b <1, and 0 ≦ d <1 are satisfied. The band gap in the heterojunction surface of the semiconductor forming the first semiconductor layer, to claim 1, wherein the larger than the band gap of the semiconductor of the heterojunction surface constituting the second semiconductor layer 4. The semiconductor device according to any one of 3 . Forming a first semiconductor layer and a second semiconductor layer that are heterojunction with each other;
Forming a gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer;
Forming a drain electrode connected to the first semiconductor layer and a source electrode connected to the second semiconductor layer;
Forming a region in the first semiconductor layer in which the band gap decreases continuously or stepwise as the distance from the heterojunction surface increases.
A method for manufacturing a semiconductor device, comprising: Forming a first semiconductor layer and a second semiconductor layer that are heterojunction with each other;
Forming a drain electrode connected to the first semiconductor layer and a source electrode connected to the second semiconductor layer;
A first region in which a band gap increases as the distance from the heterojunction surface between the first semiconductor layer and the second semiconductor layer increases; and a second region heterojunction with the first region Forming on the second semiconductor layer;
A gate electrode for controlling a potential of a heterojunction surface between the first semiconductor layer and the second semiconductor layer and a potential of a heterojunction surface between the first region and the second region Forming a step;
A method for manufacturing a semiconductor device, comprising:

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