JP2006210693A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high breakdown voltage, and to provide a manufacturing method for the semiconductor device. <P>SOLUTION: The semiconductor device has a semiconductor base 100, consisting of a 1st first conductivity-type semiconductor material of, an anode electrode 7 formed to come into contact with a first major surface of the semiconductor base, and a cathode electrode 6 formed to come into contact with an opposite major surface facing the first major surface. The semiconductor device has a heterojunction, formed of the first semiconductor material and a second semiconductor material which is different from the first semiconductor material in the band gap, and a field-relaxing region 5, formed of an impurity introducing region 4 formed in the first semiconductor material in contact with the heterojunction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high breakdown voltage semiconductor device and a method for manufacturing the semiconductor device.

One of the junctions to obtain a high voltage diode using conventional silicon carbide is “Power Device / Power IC Handbook Electrical Society of Japan High Performance and High Performance Power Device / Power IC Research Special Committee, Corona, Inc. p.12 ～ There is a Schottky junction described in 21 ″ (non-patent document). In this non-patent document, the junction for obtaining the above high breakdown voltage diode is described on the basis of silicon, and is widely applied to silicon carbide.
"Power Device / Power IC Handbook Electrical Society of Japan High Performance and High Performance Power Device / Power IC Research Committee, Corona, Inc. p.12-21"

  In order to apply a Schottky junction to silicon carbide and realize a high breakdown voltage diode, a diffusion layer is formed as an electric field relaxation region at the Schottky electrode end to alleviate electric field concentration at the Schottky electrode end. There is a need. When forming this diffusion layer, ion implantation is used. In the case of silicon carbide, the activation heat treatment after the implantation requires a high temperature of 1500 ° C. or more, so that the surface of the silicon carbide substrate deteriorates during the heat treatment. There is a problem that a good Schottky junction cannot be formed on the deteriorated silicon carbide substrate surface and it is difficult to realize a high breakdown voltage diode.

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a semiconductor device having a high breakdown voltage and a method for manufacturing the semiconductor device.

  To achieve the above object, the present invention provides a heterojunction formed by a first semiconductor material and a second semiconductor material having a band gap different from that of the first semiconductor material, and in contact with the heteroconnection. A semiconductor device including an electric field relaxation region including an impurity introduction region formed in a first semiconductor material and a method for manufacturing the semiconductor device are provided.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the electric field relaxation region can be formed without performing high-temperature heat treatment, and a high voltage diode or switch element can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
A first embodiment of the present invention will be described based on FIG. 1, FIG. 2, FIG. 3, and FIG. FIG. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the first embodiment of the present invention.

In FIG. 1, an N ⁻ type silicon carbide epitaxial layer 2 is formed on an N ⁺ type silicon carbide substrate 1 to form an N type silicon carbide semiconductor substrate 100 which is a first conductivity type. That is, silicon carbide semiconductor substrate 100 in which the first semiconductor material is silicon carbide includes silicon carbide substrate 1 and silicon carbide epitaxial layer 2.

The first main surface side of the silicon carbide semiconductor substrate 100, i.e., the silicon carbide epitaxial layer 2 side, as the second semiconductor materials having different band gap silicon carbide, N ^- consists -type polycrystalline silicon N ^- type Polycrystalline silicon layer 3A is formed, and a heterojunction is formed between silicon carbide epitaxial layer 2 and N ⁻ type polycrystalline silicon layer 3A.

Further, an electric field relaxation region 5 is formed on the first main surface side of silicon carbide semiconductor substrate 100, that is, on silicon carbide epitaxial layer 2 side, so that impurity introduction region 4 into which impurities are introduced is in contact with the heterojunction. Yes. On the back surface of silicon carbide substrate 1, cathode electrode 6 is formed of a conductive material such as metal. Further, the N ⁻ type polycrystalline silicon layer 3 A formed so as to be in contact with the silicon carbide epitaxial layer 2 also serves as the anode electrode 7.

That is, the silicon carbide semiconductor device shown in FIG. 1 has a diode structure having anode electrode 7 and cathode electrode 6 made of N ⁻ type polycrystalline silicon layer 3A.

  Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIG.

First, as shown in FIG. 2A, an N type silicon carbide semiconductor substrate 100 in which an N ⁻ type silicon carbide epitaxial layer 2 is formed on an N ⁺ type silicon carbide substrate 1 is prepared. The concentration and thickness of silicon carbide epitaxial layer 2 are, for example, 1 × 10 ¹⁶ cm ⁻³ and 10 μm.

  Next, as shown in FIG. 2B, after depositing, for example, 1000Å of polycrystalline silicon by LP-CVD method to form a polycrystalline silicon layer 3, phosphorus 8 is deposited by polycrystalline silicon layer 3 by ion implantation. Impurities are introduced into the polycrystalline silicon.

The ion implantation conditions at this time are, for example, an acceleration voltage of 70 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² . Under this condition, the range of phosphorus 8 to be implanted becomes larger than the thickness of the polycrystalline silicon layer 3, so that phosphorus 8 is also implanted into the silicon carbide epitaxial layer 2 side through the polycrystalline silicon layer 3 and the impurity introduction region. 4 is formed. That is, the heterojunction between the silicon carbide epitaxial layer 2 and the polycrystalline silicon layer 3 and the electric field relaxation region 5 including the impurity introduction region 4 are formed.

Next, as shown in FIG. 2C, heat treatment is performed at 950 ° C. for 20 minutes in a nitrogen atmosphere to activate phosphorus 8 implanted into the polycrystalline silicon layer 3, and then by photolithography and etching. The polycrystalline silicon layer 3 is patterned to form an N ⁻ type polycrystalline silicon layer 3A.

Next, as shown in FIG. 2 (D), Ti (titanium) and Ni (nickel) are deposited in this order on the back surface of the N ⁺ type silicon carbide substrate 1 by sputtering, and 1000 ° C. for 1 minute in a nitrogen atmosphere. RTA (Rapid Thermal Anneal) is performed to form the cathode electrode 6 to complete the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG.

  According to the method for manufacturing a silicon carbide semiconductor device according to the first embodiment, the polycrystalline silicon layer 3 as the second semiconductor material is deposited on the silicon carbide substrate 100 as the first semiconductor material, thereby forming a heterojunction. Can be formed. Moreover, since ion implantation is used for introducing impurities into the polycrystalline silicon layer 3, impurities can be introduced with high accuracy.

Further, since the thickness of polycrystalline silicon layer 3 is formed to be thinner than the range of phosphorus 8 at the time of impurity introduction, N ⁻ -type silicon carbide epitaxial layer simultaneously with the introduction of impurities into polycrystalline silicon layer 3 by ion implantation. Impurities are also introduced into 2 to form the impurity introduction region 4, and as a result, the electric field relaxation region 5 can be formed in a self-aligned manner.

  A specific operation of the silicon carbide semiconductor device according to the first embodiment manufactured as described above will be described using an energy band structure from point a to point b in FIG.

FIG. 3A shows an energy band structure in a thermal equilibrium state, that is, in a state where both the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7) and the cathode electrode 6 are grounded.

Due to the difference in electron affinity χSiC, χPoly between silicon carbide and N ⁻ -type polycrystalline silicon, an accumulation layer is formed on the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7) side at the heterojunction interface under the thermal equilibrium state, A barrier φh50 is formed at the heterojunction interface.

For this reason, when an appropriate voltage is applied to the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7) of this element and the cathode electrode 6 is grounded, electrons are transferred from the cathode electrode 6 to the silicon carbide substrate 1 and the silicon carbide epitaxial layer. It flows through the layer 2 and the impurity introduction region 4 to the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7). That is, it shows the forward characteristic of the diode.

Next, the operation of the device when the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7) is grounded and a high voltage is applied to the cathode electrode 6, that is, when a reverse voltage is applied will be described.

  In this element, when the electric field relaxation region 5 composed of the impurity introduction region 4 and the heterojunction does not exist, a high electric field is applied to the heterojunction interface when the reverse voltage is applied, and the energy band structure is as shown in FIG. The electrons 51 are blocked by the barrier φh50 generated at the heterojunction interface, and the blocked state is maintained.

At this time, a part of the electrons 51 accumulated on the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7) side at the heterojunction interface tunnels through the barrier φh50 by applying a high electric field, or the barrier φh50. As the electric field relaxation region 5 exists, the heterojunction interface is reached by the electric field relaxation region 5 when trying to move from the N ⁻ type polycrystalline silicon layer 3A to the silicon carbide epitaxial layer 2. Since the electric field is relaxed, the reverse leakage current from the heterojunction can be reduced.

  FIG. 4 shows the reverse characteristics of the diode obtained from the results of the inventors producing and experimenting with the silicon carbide semiconductor device according to the first embodiment of the present invention. The diode having the electric field relaxation region 5 has very little reverse leakage current as compared with the case where the electric field relaxation region 5 is not provided, and exhibits a good reverse characteristic. As understood from the experimental results, this element has a high reverse breakdown voltage even in the case of only the heterojunction, but it becomes possible to further reduce the leakage current by providing the electric field relaxation region 5. Thus, it is possible to realize a diode having a higher blocking property.

  Moreover, since the silicon carbide semiconductor device in 1st Embodiment can be formed without using high temperature activation annealing unlike the conventional edge termination area | region etc., the surface of the silicon carbide epitaxial layer 2 deteriorates. There is no. In addition, since the electric field relaxation region 5 can be formed in a self-aligning manner when impurities are introduced into the polycrystalline silicon layer 3, the process can be simplified.

  In addition, by using silicon carbide as the first semiconductor material, a semiconductor device with higher withstand voltage can be provided.

  Furthermore, by using polycrystalline silicon as the second semiconductor material, processes such as etching and conductivity control during device manufacturing can be simplified.

<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a cross-sectional view of a silicon carbide semiconductor device according to the second embodiment of the present invention.

The silicon carbide semiconductor device according to the second embodiment of the present invention has substantially the same structure as that of the silicon carbide semiconductor device according to the first embodiment, but is N ⁻ formed so as to be in contact with silicon carbide epitaxial layer 2. The difference from the silicon carbide semiconductor device in the first embodiment is that electric field relaxation region 5 is formed only on the outer peripheral portion of type polycrystalline silicon layer 3A (anode electrode 7).

  Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention shown in FIG. 5 will be described with reference to FIG. In addition, the figure in the process similar to the manufacturing method of the silicon carbide semiconductor device by the 1st Embodiment of this invention is abbreviate | omitted.

First, an N type silicon carbide semiconductor substrate 100 in which an N ⁻ type silicon carbide epitaxial layer 2 is formed on an N ⁺ type silicon carbide substrate 1 is prepared. The concentration and thickness of silicon carbide epitaxial layer 2 are, for example, 1 × 10 ¹⁶ cm ⁻³ and 10 μm.

Next, as shown in FIG. 6A, polycrystalline silicon is deposited by LP-CVD to form a polycrystalline silicon layer 3. At this time, the thickness of the polycrystalline silicon layer 3 is made larger than the range of ions for ion implantation at the time of impurity introduction. For example, when the condition of ion implantation is that phosphorus is implanted at an acceleration voltage of 70 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² , the thickness of the polycrystalline silicon layer 3 is, for example, 5000 mm.

  Next, by photolithography and etching, the outer peripheral portion of the polycrystalline silicon layer 3 is made to have a thickness that is smaller than the range of ions for ion implantation at the time of impurity introduction. For example, when the ion implantation conditions are the above-described conditions, the thickness of the polycrystalline silicon layer 3 that is smaller than the range is, for example, 1000 mm. That is, a region where the thickness of the polycrystalline silicon layer 3 is different, specifically, a region larger or smaller than the range of ions for ion implantation at the time of introducing the impurity is formed.

Next, as shown in FIG. 6B, phosphorus 8 is introduced into the polycrystalline silicon layer 3 by ion implantation. As described above, the ion implantation conditions are, for example, an acceleration voltage of 70 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² . At this time, phosphorus 8 is implanted also into the silicon carbide epitaxial layer 2 side immediately below the region where the thickness of the polycrystalline silicon layer 3 is smaller than the range of the phosphorus 8 to form the impurity introduction region 4.

  That is, an electric field relaxation region 5 including a heterojunction of silicon carbide epitaxial layer 2 and polycrystalline silicon layer 3 and impurity introduction region 4 is formed.

Next, heat treatment is performed in a nitrogen atmosphere at 950 ° C. for 20 minutes to activate the phosphorus 8 implanted into the polycrystalline silicon layer 3, and then the polycrystalline silicon layer 3 is patterned by photolithography and etching, and N ^A -type polycrystalline silicon layer 3A is formed. At this time, the N ⁻ type polycrystalline silicon layer 3A is patterned so that the outermost peripheral portion is on the impurity introduction region 4.

Thereafter, Ti (titanium) and Ni (nickel) are sequentially deposited on the back surface of the N ⁺ -type silicon carbide substrate 1 by sputtering, and RTA (Rapid Thermal Anneal) is performed at 1000 ° C. for 1 minute in a nitrogen atmosphere. Electrode 6 is formed to complete the silicon carbide semiconductor device shown in FIG.

In addition to the effects shown in the first embodiment, the silicon carbide semiconductor device in the second embodiment manufactured in this way has an N ⁻ type polycrystalline silicon layer 3A (where the electric field is most concentrated when a reverse voltage is applied) Since the electric field relaxation region 5 is disposed on the outer peripheral portion of the anode electrode 7), compared with the case where the electric field relaxation region 5 is not provided, the N ^- type polycrystalline silicon layer 3A (the anode electrode 7) is separated from the outer peripheral portion. Leakage current is reduced, resulting in a higher breakdown voltage.

Furthermore, in the silicon carbide semiconductor device according to the second embodiment, the electric field relaxation region 5 is disposed only on the outer peripheral portion of the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7). 5 has the same characteristics as those in the case where 5 does not exist, a high reverse breakdown voltage can be obtained, and a low on-resistance can be realized.

The silicon carbide semiconductor device according to the second embodiment has a structure in which the electric field relaxation region 5 is disposed on the outer periphery of the N ⁻ -type polycrystalline silicon layer 3A (anode electrode 7). As shown in FIG. 7A, when the polycrystalline silicon layer 3 is patterned, the polycrystalline silicon layer 3 has a region in which the thickness of the polycrystalline silicon layer 3 is larger or smaller than the range of ions during ion implantation when impurities are introduced. Are patterned so as to be alternately arranged at predetermined intervals, or as shown in FIG. 7B, the thickness of the polycrystalline silicon layer 3 becomes smaller than the range of ions for ion implantation at the time of impurity introduction. If the mask material 52 made of an oxide film or the like is patterned after being formed with a thickness, the impurity introduction region is selectively introduced into the silicon carbide epitaxial layer 2 together with the introduction of impurities into the polycrystalline silicon layer 3. The region 4 is formed, and the electric field relaxation region 5 as shown in FIGS. 7C and 7D is formed at a predetermined interval, thereby further improving the blocking property when a reverse voltage is applied. it can.

  In the first and second embodiments, the case where the polycrystalline silicon layer 3A functions as the anode electrode 7 has been described. However, the same applies to the case where the anode electrode 7 as shown in FIGS. An effect can be obtained.

  In the first and second embodiments of the present invention, the diode has been described as an example, but the electric field relaxation region in the present invention can be used as simple edge termination as described above. Therefore, the present invention can be applied not only to a diode but also to a switch element or the like.

<Third Embodiment>
A third embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a cross-sectional view of a silicon carbide semiconductor device according to the third embodiment of the present invention. As shown in the figure, this silicon carbide semiconductor device shows a cross-sectional structure at the outer periphery of a large number of unit cells arranged, and shows a structure in which three unit cells are continuous.

In FIG. 10, an N ⁻ type silicon carbide epitaxial layer 2 is formed on an N ⁺ type silicon carbide substrate 1 to form an N type silicon carbide semiconductor substrate 100 which is the first conductivity type. That is, silicon carbide semiconductor substrate 100 in which the first semiconductor material is silicon carbide includes silicon carbide substrate 1 and silicon carbide epitaxial layer 2.

  Trenches (grooves) 13 are formed at predetermined intervals on the first main surface side on silicon carbide semiconductor substrate 100, that is, on silicon carbide epitaxial layer 2 side. A source region 9 made of N-type polycrystalline silicon, which is a semiconductor material having a band gap different from that of silicon carbide semiconductor substrate 100, is formed at a predetermined position on the first main surface side of silicon carbide epitaxial layer 2, and silicon carbide epitaxial layer A heterojunction is formed between 2 and the source region 9.

  A gate electrode 10 is formed adjacent to silicon carbide epitaxial layer 2 and source region 9 on the side wall of trench 13 via gate insulating film 14. Source electrode 11 is formed in source region 9, and drain electrode 12 is formed on the second main surface side of silicon carbide substrate 1. An electric field relaxation region formed such that an impurity introduction region 4 into which an impurity is introduced is in contact with the heterojunction on the silicon carbide epitaxial layer 2 side in a predetermined region between the trenches 13 and the outer peripheral portion of a large number of unit cells arranged 5 is formed. The gate electrode 10 and the source electrode 11 are electrically insulated by an interlayer insulating film 15.

  Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention shown in FIG. 10 will be described with reference to FIGS.

First, as shown in FIG. 11A, an N type silicon carbide semiconductor substrate 100 in which an N ⁻ type silicon carbide epitaxial layer 2 is formed on an N ⁺ type silicon carbide substrate 1 is prepared. The concentration and thickness of silicon carbide epitaxial layer 2 are, for example, 1 × 10 ¹⁶ cm ⁻³ and 10 μm.

  Next, as shown in FIG. 11B, polycrystalline silicon is deposited on the silicon carbide epitaxial layer 2 side of the silicon carbide semiconductor substrate 100 by LP-CVD to form a polycrystalline silicon layer 3. At this time, the thickness of the polycrystalline silicon layer 3 is, for example, 5000 mm.

Next, as shown in FIG. 11C, boron 30 is ion-implanted into the predetermined region of silicon carbide epitaxial layer 2 through polycrystalline silicon using mask material 52. At this time, the acceleration voltage of the boron 30 is set so that the implantation range of the boron 30 is larger than the thickness of the polycrystalline silicon layer 3. In the case of this embodiment, for example, the acceleration voltage is 200 keV, and the dose amount is 5 × 10 ¹³ cm ⁻² .

  By performing ion implantation under such conditions, boron 30 is implanted into part of the polycrystalline silicon layer 3 and the silicon carbide epitaxial layer 2 side immediately below the polycrystalline silicon layer 3 to form the impurity introduction region 4.

Next, as shown in FIG. 11 (D), after the phosphorus 8 is ion-implanted into the entire surface of the polycrystalline silicon layer 3, 950 ° C. in a nitrogen atmosphere, heat treatment is performed for 20 minutes, N ⁺ -type polycrystalline A silicon layer 3B is formed. The phosphorus 8 implantation conditions in this embodiment are, for example, an acceleration voltage of 50 keV and a dose of 1 × 10 ¹⁶ cm ⁻² .

Here, in the process of FIG. 11C described above, boron is implanted into a part of the polycrystalline silicon layer. The concentration of phosphorus implanted in the process of FIG. 11D is the same as that of the implanted boron. Since it is higher than the concentration by about two orders of magnitude or more, after the heat treatment at 950 ° C. for 20 minutes in the nitrogen atmosphere, all the polycrystalline silicon layers become N ⁺ type. By performing the steps shown in FIGS. 11C and 11D in this way, the electric field relaxation comprising the heterojunction of the silicon carbide epitaxial layer 2 and the N ⁺ -type polycrystalline silicon layer 3B and the impurity introduction region 4 is achieved. Region 5 is formed. Thereafter, the outer peripheral portion of the N ⁺ type polycrystalline silicon layer 3B is etched by photolithography and etching.

Next, as shown in FIG. 12 (E), predetermined regions of the N ⁺ -type polycrystalline silicon layer 3B and the silicon carbide epitaxial layer 2 are etched by reactive ion etching using the mask material 52, and the source region 9 Then, the trench 13 is formed. Thereafter, the mask material 52 is removed.

  Then, as shown in FIG. 12F, after forming the gate insulating film 14 so as to be adjacent to the silicon carbide epitaxial layer 2 on the side wall of the source region 9 and the trench 13, the gate insulating film 14 is inserted into the trench through the gate insulating film 14. A gate electrode 10 is formed.

  Next, after depositing an interlayer insulating film 15 as shown in FIG. 12G, a contact hole is opened, a source electrode 11 is formed so as to be in contact with the source region 9, and the silicon carbide substrate 1 is formed on the back surface. Drain electrode 12 is formed to complete the silicon carbide semiconductor device of FIG.

  A specific operation of the silicon carbide semiconductor device according to the third embodiment manufactured as described above will be described. This element is used by grounding the source electrode 11 and applying a positive drain voltage to the drain electrode 12.

  At this time, if gate electrode 10 is grounded, the characteristics of the element exhibit the same characteristics as the reverse characteristics of the silicon carbide semiconductor device in the first embodiment. In other words, no current flows between the source electrode 11 and the drain electrode 12, so that the state is cut off.

  Next, when an appropriate positive voltage is applied to the gate electrode 10, electrons are accumulated in the source region 9 made of polycrystalline silicon adjacent to the gate insulating film 14 and the silicon carbide epitaxial layer 2, and as a result, a predetermined drain voltage is obtained. Thus, a current flows between the source electrode 11 and the drain electrode 12. That is, it becomes a conductive state.

  Further, when the positive voltage applied to the gate electrode 10 is removed, the source region 9 adjacent to the gate insulating film 14 and the silicon carbide epitaxial layer 2 have no electron accumulation layer, and the barrier φh50 at the heterojunction interface (FIG. 3 (A)), the electrons are blocked, and a blocking state is obtained.

  This element is formed so that the impurity introduction region 4 is in contact with the heterojunction in a predetermined region between the outer peripheral portion of the arrayed unit cells and the trenches 13 where the electric field tends to concentrate when a drain voltage is applied. Since the electric field relaxation region 5 is provided, the electric field in the outer peripheral portion when the drain voltage is applied can be relaxed, and the drain breakdown voltage is high.

  Further, when this element is turned on in the reverse direction, the electric field relaxation region 5 functions as a unipolar free-wheeling diode, so there is no need to provide a free-wheeling diode inside the switch element, and the area per unit cell can be reduced. That is, the on-resistance can be further reduced. Further, since the electric field relaxation region 5 functioning as a reflux diode is a unipolar element, minority carrier injection does not occur. Therefore, it is possible to reduce power loss during the switching operation.

  In this embodiment, the impurity introduced into the impurity introduction region is described as boron, and the impurity introduced into the polycrystalline silicon layer as the second semiconductor material is described as phosphorus. , And combinations are not limited to these. For example, as impurities introduced into the impurity introduction region, argon, phosphorus, arsenic, aluminum, vanadium, sulfur, or the like can be used in addition to boron. In addition to phosphorus, arsenic, antimony, boron, aluminum, gallium, or the like can be used as an impurity to be introduced into the polycrystalline silicon layer.

<Fourth Embodiment>
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a cross-sectional view of a silicon carbide semiconductor device according to the fourth embodiment of the present invention. As shown in the figure, this silicon carbide semiconductor device shows a cross-sectional structure at the outer periphery of a large number of unit cells arranged, and shows a structure in which three unit cells are continuous.

In Figure 13, N on the N ⁺ -type silicon carbide substrate 1 ^- the type of N-type silicon carbide semiconductor substrate 100 is a first conductivity type by forming a silicon carbide epitaxial layer 2 is formed. That is, silicon carbide semiconductor substrate 100 in which the first semiconductor material is silicon carbide includes silicon carbide substrate 1 and silicon carbide epitaxial layer 2. On this silicon carbide semiconductor substrate 100, trenches (grooves) 13 are formed at predetermined intervals on the first main surface side, that is, on the silicon carbide epitaxial layer 2 side.

A source region 9 made of N ⁻ -type polycrystalline silicon, which is a semiconductor material having a band gap different from that of silicon carbide semiconductor substrate 100, is formed at a predetermined position on the first main surface side of silicon carbide epitaxial layer 2. A heterojunction is formed between the layer 2 and the source region 9. A source contact region 16 made of N ⁺ type polycrystalline silicon is formed at a predetermined position on the first main surface side of the source region 9 so as to be in contact with the source region 9.

  Gate electrode 10 is formed adjacent to silicon carbide epitaxial layer 2, source region 9, and source contact region 16 on the side wall portion of trench 13 through gate insulating film 14. Source electrode 11 is formed in source contact region 16, and drain electrode 12 is formed on the second main surface side of silicon carbide substrate 1.

  An electric field relaxation region formed such that an impurity introduction region 4 into which an impurity is introduced is in contact with the heterojunction on the silicon carbide epitaxial layer 2 side in a predetermined region between the trenches 13 and the outer peripheral portion of a large number of unit cells arranged 5 is formed. The gate electrode 10 and the source electrode 11 are electrically insulated by an interlayer insulating film 15.

  Next, a method for manufacturing the silicon carbide semiconductor device according to the fourth embodiment of the present invention shown in FIG. 13 will be described with reference to FIGS.

First, as shown in FIG. 14A, an N-type silicon carbide semiconductor substrate 100 in which an N ⁻ -type silicon carbide epitaxial layer 2 is formed on an N ⁺ -type silicon carbide substrate 1 is prepared. The concentration and thickness of silicon carbide epitaxial layer 2 are, for example, 1 × 10 ¹⁶ cm ⁻³ and 10 μm.

Next, as shown in FIG. 14B, polycrystalline silicon is deposited on the silicon carbide epitaxial layer 2 side of the silicon carbide semiconductor substrate 100 by LP-CVD to form a polycrystalline silicon layer 3. At this time, the thickness of the polycrystalline silicon layer 3 is set to be larger than the range of ions for ion implantation at the time of impurity introduction. For example, when the condition of ion implantation is that phosphorus is implanted at an acceleration voltage of 70 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² , the thickness of the polycrystalline silicon layer 3 is, for example, 5000 mm.

Next, as shown in FIG. 14C, a region where the thickness of the polycrystalline silicon layer 3 is different by photolithography and etching, specifically, a region larger than the ion implantation range at the time of impurity introduction, or After forming a small region, phosphorus 8 is introduced into the polycrystalline silicon layer 3 by ion implantation. As described above, the ion implantation conditions are, for example, an acceleration voltage of 70 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² .

At this time, phosphorus 8 is implanted also into the silicon carbide epitaxial layer 2 side immediately below the region where the thickness of the polycrystalline silicon layer 3 is smaller than the range of the phosphorus 8 to form the impurity introduction region 4. That is, an electric field relaxation region 5 including a heterojunction of silicon carbide epitaxial layer 2 and polycrystalline silicon layer 3 and impurity introduction region 4 is formed. Thereafter, heat treatment is performed at 950 ° C. for 20 minutes in the nitrogen atmosphere as activation annealing of the implanted phosphorus 8 to form the N ⁻ -type polycrystalline silicon layer 3A.

Next, as shown in FIG. 14 (D), N ^- type on the upper surface of the polycrystalline silicon layer 3A is formed an N ⁺ -type polycrystalline silicon layer 3B, N by photolithography and etching ^- -type polycrystalline silicon layer 3A The N ⁺ type polycrystalline silicon layer 3B is patterned. After the patterning, an oxide film is deposited, and the mask film 52 is formed by patterning the oxide film by photolithography and etching.

Next, as shown in FIG. 15E, the N ⁻ type polycrystalline silicon layer 3A, the N ⁺ type polycrystalline silicon layer 3B, and the silicon carbide epitaxial layer are formed by reactive ion etching using the formed mask material 52 as a mask. 2 is etched to form a source region 9, a source contact region 16, and a trench 13. Thereafter, the mask material 52 is removed.

  Then, as shown in FIG. 15F, after forming the gate insulating film 14 so as to be adjacent to the silicon carbide epitaxial layer 2 on the side wall of the source region 9, the source contact region 16, and the trench 13, the gate insulating film 14 is interposed therebetween. Then, the gate electrode 10 is formed inside the trench.

  Next, as shown in 15 (G), after depositing interlayer insulating film 15, a contact hole is opened, source electrode 9 is formed so as to be in contact with source contact region 16, and a drain is formed on the back surface of silicon carbide substrate 1. Electrode 12 is formed to complete the silicon carbide semiconductor device of FIG.

  The silicon carbide semiconductor device according to the fourth embodiment manufactured in this way exhibits the same operation as the semiconductor device according to the third embodiment.

The source region 9 in the fourth embodiment the N ^- showed MOSFET of configured storage type at -type polycrystalline silicon as an example, the source region 9 N ^- -type inversion type constituted by polycrystalline silicon MOFET may be used. In this case, boron or the like can be used for ion implantation into the source region 9.

  As described above, in the third and fourth embodiments, the vertical MOSFET is described as an example of the switch element. However, any switch element having an active region including a source region, a drain region, and a drive region may be used.

  For example, the same effect can be obtained in any switching element such as a unipolar device such as a MOSFET or JFET, a bipolar device typified by an IGBT, or a lateral switching element such as a MOSFET having a RESURF structure.

  In any of the embodiments of the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type. However, the first conductivity type is defined as P type and the second conductivity type is defined as N type. Can achieve the same effect.

  Furthermore, in any embodiment of the present invention, the first semiconductor material is described as silicon carbide, and the second semiconductor material is described as polycrystalline silicon. .

  For example, a wide gap semiconductor typified by gallium nitride, diamond, zinc oxide, and the like can of course obtain the same effect in any semiconductor material such as germanium, gallium arsenide, and indium nitride.

  Moreover, it cannot be overemphasized that the deformation | transformation in the range which does not deviate from the main point of this invention is included.

  This is extremely useful in manufacturing a semiconductor device with a high breakdown voltage.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on the 1st Embodiment of this invention. It is explanatory drawing which shows the manufacturing process of the silicon carbide semiconductor device which concerns on 1st Embodiment. It is explanatory drawing which shows the energy band structure in the silicon carbide semiconductor device which concerns on 1st Embodiment. It is explanatory drawing which shows the reverse direction characteristic of the silicon carbide semiconductor device which concerns on 1st Embodiment obtained from the experimental result. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows the manufacturing process of the silicon carbide semiconductor device which concerns on 2nd Embodiment. It is explanatory drawing which shows the application example of the silicon carbide semiconductor device which concerns on 2nd Embodiment. In the 2nd Embodiment of this invention, it is explanatory drawing which shows sectional drawing of the silicon carbide semiconductor device in case an anode electrode consists of metals. In the 2nd Embodiment of this invention, it is explanatory drawing which shows sectional drawing of the silicon carbide semiconductor device in case an anode electrode consists of metals. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 12 is a first partial view of an explanatory view showing a manufacturing process of a silicon carbide semiconductor device according to a third embodiment. FIG. 12 is a second partial view of the explanatory view showing the manufacturing process of the silicon carbide semiconductor device according to the third embodiment. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on the 4th Embodiment of this invention. FIG. 10 is a first partial view of an explanatory view showing a manufacturing process of a silicon carbide semiconductor device according to a fourth embodiment. It is a 2nd partial view of the explanatory view showing the manufacturing process of the silicon carbide semiconductor device concerning a 4th embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate 2 Silicon carbide substrate epitaxial layer 3 Polycrystalline silicon layer 3A N ^- type polycrystalline silicon layer 3B N ⁺ type polycrystalline silicon layer 4 Impurity introduction region 5 Electric field relaxation region 6 Cathode electrode 7 Anode electrode 8 Phosphorus 9 Source region 10 gate electrode 11 source electrode 12 drain electrode 13 trench 14 gate insulating film 15 interlayer insulating film 16 source contact region 30 boron 50 barrier φh
51 Electronic 52 Mask material

Claims (18)

  A heterojunction formed by a first semiconductor material and a second semiconductor material having a different band gap between the first semiconductor material and an impurity formed in the first semiconductor material so as to be in contact with the heteroconnection A semiconductor device comprising: an introduction region; and an electric field relaxation region. A semiconductor substrate made of a first semiconductor material of a first conductivity type, an anode electrode formed to contact the first main surface of the semiconductor substrate, and a main surface opposite to the first main surface In a semiconductor device having a cathode electrode formed,
Between the anode electrode and the semiconductor substrate, the first semiconductor material and the first semiconductor material are in contact with the heterojunction formed by a second semiconductor material having a different band gap. Thus, a semiconductor device comprising an electric field relaxation region comprising an impurity introduction region formed in the first semiconductor material.   The semiconductor device according to claim 2, wherein the electric field relaxation region is annularly arranged on an outer peripheral portion of the anode electrode.   The semiconductor device according to claim 2, wherein the electric field relaxation regions are arranged at a predetermined interval. In a semiconductor device for forming a switch element having an active region composed of at least three regions of a source region, a drain region, and a drive region formed in a predetermined position of a semiconductor substrate made of a first semiconductor material,
The first semiconductor material and the first semiconductor material are formed on the first semiconductor material so as to be in contact with the heterojunction formed by the second semiconductor material having a different band gap. A semiconductor device comprising an electric field relaxation region comprising an impurity introduction region.   The semiconductor device according to claim 5, wherein the electric field relaxation region is annularly arranged on an outer peripheral portion of the active region.   The semiconductor device according to claim 5, wherein the electric field relaxation region is disposed in at least one place inside the active region.   The switch element includes a drain region formed of the semiconductor substrate, a source region formed of a second semiconductor material having a band gap different from that of the first semiconductor material, and an insulating film adjacent to the semiconductor substrate and the source region. And a drain electrode formed in contact with the drain region, and a gate electrode disposed in contact with the source region, and a drain electrode formed in contact with the drain region. The semiconductor device according to claim 7.   9. The semiconductor device according to claim 8, wherein a groove is formed at a predetermined position on the first main surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the first semiconductor material is silicon carbide.   11. The semiconductor device according to claim 1, wherein the second semiconductor material is at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon. A semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of claims 1 to 11,
Forming a heterojunction of the first semiconductor material and the second semiconductor material having a band gap different from that of the first semiconductor material;
Introducing impurities into the second semiconductor material;
Forming the impurity introduction region;
A method for manufacturing a semiconductor device, comprising:   13. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the impurity introduction region is performed by introducing an impurity into the first semiconductor material through the second semiconductor material. Method. The step of forming the impurity introduction region comprises:
The method of manufacturing a semiconductor device according to claim 12, wherein the method is performed simultaneously with the step of introducing an impurity into the second semiconductor material.   The method for manufacturing a semiconductor device according to claim 12, wherein the step of introducing the impurity is performed by ion implantation.   A step of forming the second semiconductor material such that the entire surface or a part of the thickness of the second semiconductor material is thinner than the range of impurities introduced by the ion implantation. The method for manufacturing a semiconductor device according to any one of claims 12 to 15.   The method of manufacturing a semiconductor device according to any one of claims 12 to 16, wherein the first semiconductor material is silicon carbide. 18. The method of manufacturing a semiconductor device according to claim 12, wherein the second semiconductor material is at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon. Method.

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