CN112951905A - SiC reverse conducting type insulated gate bipolar transistor device and manufacturing method thereof - Google Patents
SiC reverse conducting type insulated gate bipolar transistor device and manufacturing method thereof Download PDFInfo
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- 230000002441 reversible effect Effects 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000011049 filling Methods 0.000 claims abstract description 10
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 230000008020 evaporation Effects 0.000 claims description 12
- 238000001704 evaporation Methods 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000002829 reductive effect Effects 0.000 abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 26
- 229910010271 silicon carbide Inorganic materials 0.000 description 25
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention discloses a SiC reverse conducting type insulated gate bipolar transistor device and a manufacturing method thereof, wherein the transistor device comprises a metal collector electrode, and a first conducting type substrate, a first conducting type buffer layer, a second conducting type collector electrode and a first conducting type drift region are sequentially arranged from the metal collector electrode; a plurality of grooves are formed in the first conduction type substrate and the first conduction type buffer layer, the grooves penetrate through the first conduction type substrate layer and the first conduction type buffer layer, and the filling collector in the grooves is connected with the second conduction type collector after penetrating through the first conduction type substrate and the first conduction type buffer; the second conductive type collectors are in an array structure separated from each other, and each of the second conductive type collectors corresponds to the trench. According to the transistor device, the freewheeling diode is integrated into the SiC IGBT, so that the parasitic parameters of the circuit are reduced, and the area utilization rate of a chip is improved.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a SiC reverse conducting type insulated gate bipolar transistor device and a manufacturing method thereof.
Background
Silicon carbide (SiC) is taken as a third-generation wide bandgap material, has the advantages of large forbidden band width, high critical breakdown electric field, high thermal conductivity, high carrier saturation velocity and the like, and is favored in the field of power devices.
The silicon carbide insulated gate bipolar transistor (SiC IGBT) not only has the characteristics of high resistance-to-breakdown voltage, high working junction temperature, strong radiation resistance, high working frequency and the like of a SiC material, but also has the advantages of easiness in driving, simplicity in control, reduction in conducting voltage, large on-state current and small loss of the IGBT, is one of ideal switching devices applied to high-voltage (more than or equal to 10 kV) high-power fields such as a solid-state transformer, a high-voltage pulse power supply, a high-voltage inverter, a flexible alternating current/direct current transmission system, a high-voltage direct current transmission system, a static reactive compensator and the like, and has wide development prospect.
Generally, the use of the IGBT requires an antiparallel freewheeling diode, and the IGBT with an integrated antiparallel diode on a silicon device is known as an RC-IGBT. However, the SiC substrate is thicker than 350 μm, the impurity diffusion coefficient is low, and the separated collector region is difficult to realize, so that the realization mode of the RC-IGBT becomes a problem which needs to be considered by practitioners.
In the prior art, a P-type SiC substrate is generally adopted to form an N-channel IGBT, even if the thickness of the thinned substrate is as high as-150 μm, the implantation is difficult due to the large thickness of the substrate, and the high-energy implantation of a large amount of impurities can cause unrecoverable damage to SiC crystal lattices, so that the reverse-conducting type SiC IGBT is difficult to prepare by expecting to reversely dope the substrate with a large amount of N-type impurities. Therefore, when the SiC IGBT is used, a freewheeling diode with the same voltage level needs to be connected in an anti-parallel mode, so that high extra cost is brought, and circuit parasitic parameters are increased.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the SiC reverse conducting type insulated gate bipolar transistor structure and the manufacturing method thereof are provided, parasitic parameters of a circuit are reduced, and the area utilization rate of a chip is improved.
The technical scheme adopted by the invention is as follows:
a SiC reverse conducting type insulated gate bipolar transistor device comprises a metal collector arranged on the back side, and a first conducting type substrate, a first conducting type buffer layer, a second conducting type collector and a first conducting type drift region are sequentially arranged from the metal collector;
a plurality of grooves are formed in the first conduction type substrate and the first conduction type buffer layer, the grooves penetrate through the first conduction type substrate layer and the first conduction type buffer layer, and the filling collector in the grooves is connected with the second conduction type collector after penetrating through the first conduction type substrate and the first conduction type buffer;
the second conductive type collectors are in an array structure separated from each other, and each of the second conductive type collectors corresponds to the trench.
A manufacturing method of a SiC reverse conducting type insulated gate bipolar transistor device comprises the following steps:
1) selecting a first conductive type substrate;
2) growing an epitaxial layer on a first conduction type substrate to form a first conduction type buffer region and a part of a first conduction type-drift region, and forming a separated second conduction type collector region by selectively injecting second conduction type impurities;
3) continuing to grow a first conduction type-drift region on the formed second conduction type collector region;
4) blocking through a graphic mask, and forming a second conductive type well region through selective ion implantation;
5) forming a side wall on the side wall of the pattern mask in a self-alignment mode;
6) forming a first conductive type emitter region by ion implantation;
7) blocking the selective ion implantation through a graphic mask to form a heavily doped second conductive type region;
8) removing the surface mask, coating carbon film for protection, and then performing high-temperature annealing;
9) removing the carbon film and performing sacrificial oxidation treatment on the surface, and forming a gate insulating layer in a thermal oxygen growth or deposition mode;
10) depositing doped polysilicon, and forming a gate electrode by photoetching;
11) depositing silicon dioxide or/and silicon nitride, and forming an insulating medium layer through photoetching;
12) forming an ohmic contact metal layer by means of evaporation or sputtering;
13) forming a trench penetrating through the first conductive type substrate and the first conductive type buffer layer on the back surface;
14) filling a conductive material in the groove to form a filled collector, and leading out the second conductive type collector;
15) forming a metal emitter on the front surface in an evaporation or sputtering mode;
16) forming an ohmic contact metal layer on the back surface in an evaporation or sputtering mode, and forming ohmic contact with the first conductive type substrate through laser annealing;
17) and forming a back metal emitter by means of evaporation or sputtering.
The invention achieves the following beneficial effects:
according to the SiC reverse conducting insulated gate bipolar transistor device, the connection of the collector metal and the second conducting type collector is realized through the back deep groove structure, the reverse parallel integration of the SiC diode and the SiC IGBT is realized, the reverse conducting type SiC IGBT device is formed, the utilization rate of the area of a chip is effectively improved, and the application cost of the device is greatly reduced.
Drawings
Fig. 1 is a schematic structural view of an SiC reverse conducting type insulated gate bipolar transistor device example 1 according to the present invention;
fig. 2 is a schematic structural view of an SiC reverse conducting type insulated gate bipolar transistor device example 2 according to the present invention;
FIG. 3 is a top view of a first trench structure on the backside of a transistor device in accordance with the present invention:
fig. 4 is a top view of a second trench structure on the backside of the transistor device of the present invention;
fig. 5 is a top view of a third backside trench structure of a transistor device of the present invention;
fig. 6 is a top view of a trench structure on the backside of a transistor device according to a fourth embodiment of the present invention.
The reference numbers in the figures are: 1-a first conductivity type substrate, 2-a first conductivity type buffer layer, 3-a second conductivity type collector, 4-a first conductivity type drift region, 5-a second conductivity type well region, 6-a first conductivity type emitter region, 7-a heavily doped second conductivity type region, 8-a gate insulating layer, 9-a gate electrode, 10-an insulating dielectric layer, 11-a metal emitter, 12-a filled collector, 13-a metal collector.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and should not be taken as limiting the scope of the present invention.
Example 1
As shown in fig. 1, the SiC reverse conducting type insulated gate bipolar transistor device of the present invention includes a metal collector 13 disposed on a back surface, and a first conducting type substrate 1, a first conducting type buffer layer 2, a second conducting type collector 3, and a first conducting type drift region 4 are sequentially disposed from the metal collector 13;
a plurality of grooves are formed in the first conduction type substrate and the first conduction type buffer layer, the grooves penetrate through the first conduction type substrate layer and the first conduction type buffer layer, and the filling collector 12 in the grooves penetrates through the first conduction type substrate 1 and the first conduction type buffer2 and then is connected with the second conduction type collector 3;
a second conductive type well region, a first conductive type emitter region and a heavily doped second conductive type region are arranged at the position, close to the front surface, of the first conductive type drift region;
the gate electrode 9 is isolated from the SiC material by a gate insulating layer 8 and from a metal emitter 11 located on the front side by an insulating dielectric layer 10; the SiC material comprises a well region, an emission region and a drift region;
the metal emitter 11 forms an ohmic contact connection with the first conductive type emitter region 6 and the heavily doped second conductive type region 7 at the same time.
The front structure of the first conduction type drift region is a planar gate structure.
As shown in fig. 3 to 6, the number of trenches in the first conductivity type substrate 1 and the first conductivity type buffer2 is one or more.
The shapes of the grooves in first conductivity type substrate 1 and first conductivity type buffer2 are stripe, square, polygon, circle, or the like, and may be a combination of a plurality of shapes.
The sizes of the plurality of trenches in first conductivity type substrate 1 and first conductivity type buffer2 are variable, such as being composed of two or more different sized trenches.
The material for filling the plurality of trenches in the first conductivity type substrate 1 and the first conductivity type buffer2 is one or a mixture of Cu, silver paste, alloy powder or polysilicon.
All of the above top views only cover a part of the top view of the backside trench of the present invention, and the top view of the backside trench according to the claimed invention is within the protection scope of the present invention.
The plurality of gate electrodes 9 are connected by a planar polysilicon arrangement.
If the first conductive type mentioned in the invention is N type, the second conductive type is P type; and vice versa.
The invention discloses a method for manufacturing a SiC reverse conducting type insulated gate bipolar transistor device, which comprises the following steps of:
1) selecting an N-type substrate; the thickness range of the N-type substrate is 150-350 μm, and the resistivity range is 0.01-0.02 ohm-cm;
2) growing an epitaxial layer on an N-type substrate to form an N-type buffer region and a part of N-drift region, and selectively injecting P-type impurities to form a separated P-type collector region; wherein the concentration range of the N type buffer zone is 1E18cm-3-2e18cm-3The thickness range is 0.3-3 μm; the concentration range of the P type collector region is 1E18cm-3-1E19 cm-3The thickness range is 1-10 mu m; the concentration and thickness of the N-drift region depend on the voltage class of the target device, and the concentration range is 8E14 cm-3-1E16 cm-3The thickness range is 10-100 μm; optionally, the P-type collector region may be inverted by selectively implanting ions into the N-type impurity after extending the P-type region to form a separated P-type collector region;
3) continuing to grow an N-drift region on the formed P-type collector region;
4) by means of a patterned maskBlocking, and selectively injecting ions to form a P-type well region; the concentration range of the well region is 1E18cm-3-1E19 cm-3The depth range is 1-10 μm;
5) forming a side wall on the side wall of the pattern mask in a self-alignment mode, and selecting silicon dioxide or silicon nitride to form a spacer side wall, wherein the effective width of the side wall is generally 0.4-2 mu m;
6) forming an N-type emitter region by ion implantation; the concentration range of the emission region is 5E19 cm-3-1E21 cm-3The depth range is 0.3-3 μm;
7) blocking the selective ion implantation through a graphic mask to form a heavily doped P-type region; the concentration range of the heavily doped P-type region is 1E19 cm-3-1E20 cm-3The depth is close to the depth of the P-type well region, and the depth range is 1-10 mu m;
8) removing the surface mask, coating carbon film for protection, and then performing high-temperature annealing; the high-temperature annealing temperature range is 1600-1800 ℃, and the annealing time is 15-60 min;
9) removing the carbon film and performing sacrificial oxidation treatment on the surface, and forming a gate insulating layer in a thermal oxygen growth or deposition mode; the thickness range of the oxide layer is 50nm-200nm, and the mobility of the channel is improved through nitrogen oxide annealing;
10) depositing doped polysilicon, and forming a gate electrode by photoetching, wherein the thickness range of the gate electrode is 1-4 μm, the sheet resistance range is 6 omega/□ -30 omega/□, and □ represents a square;
11) depositing silicon dioxide or/and silicon nitride, and forming an insulating medium layer through photoetching; the total thickness of the insulating medium layer is 1-4 μm;
12) forming an ohmic contact metal layer by evaporation or sputtering, wherein typical materials such as Ti, Ni and the like have the thickness range of 800-1000 angstroms (1 angstrom is 0.1 nm), and forming an ohmic contact layer of a metal emission set and a SiC material by a high-temperature process of 800-1000 ℃;
further comprising the steps of:
13) grinding the back of the front protection film of the workpiece formed in the step 11) by using a grinding wheel, and thinning the N-type substrate, or stripping and thinning the N-type substrate by using laser; selecting grinding wheels of 2000 meshes and 8000 meshes as coarse thinning and fine thinning; the thinning time is related to the thinning thickness, the thinned thickness range is 20-150 mu m, and partial stress of the chip is released by using a CMP polishing mode;
14) forming a groove penetrating through the N-type substrate and the N-type buffer layer on the back surface; the implementation mode comprises laser hole opening and chemical etching or the combination of the two implementation modes; notching SiC N-type substrate layer in selected region with laser wavelength of 300-600 nm or forming mask opening on back surface by photoetching mask, and grooving by chemical reaction with chlorine-based gas, fluorine-based gas and Cl2、CCl4、SF6、CF4、CH3F, etc.;
15) filling a conductive material in the groove to form a filled collector, and leading out the P-type collector; the conductive material is Cu, silver paste, alloy powder or polysilicon, and the like, and is annealed to form good filling and good contact between the metal collector and the P-shaped collector, wherein the annealing temperature is 300-1000 ℃, and the annealing time is 15-120 min;
16) forming a metal emitter on the front surface in an evaporation or sputtering mode; the structure is Al and/or Au and/or Ag, and Al can be doped with a small amount of other metals, and the thickness ranges from 2 mu m to 6 mu m;
17) forming an ohmic contact metal layer on the back surface in an evaporation or sputtering mode, wherein the thickness of the ohmic contact metal layer is 800-1000 angstroms and is made of materials such as Ti, Ni and the like, and forming back ohmic contact through laser annealing;
18) the back metal emitter is formed by evaporation or sputtering, the metal layer is Ti/Ni/Ag or Ti/Ni/Au, the thickness of Ti is generally in the range of 0.1-0.4 μm, the thickness of Ni is generally in the range of 0.2-0.6 μm, the thickness of Ag is generally in the range of 1-2 μm, and the thickness of Au is generally in the range of 0.01-0.1 μm.
Example 2
As shown in fig. 2, the front surface structure of the first conductivity type drift region is a trench gate structure and a trench gate structure with a dummy trench gate. By the design of the front trench, the transverse conductive channel in embodiment 1 is optimized to be longitudinal, which is beneficial to the fine design of the device and reduces the conduction voltage drop and the GC capacitance of the device.
Other technical features are the same as those of embodiment 1.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be noted that the above description is only a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be considered as the protection scope of the present invention.
Claims (10)
1. The utility model provides a SiC reverse conducting type insulated gate bipolar transistor device, is including setting up the metal collector electrode at the back, its characterized in that: a first conductive type substrate, a first conductive type buffer layer, a second conductive type collector and a first conductive type drift region are sequentially arranged from the metal collector;
a plurality of grooves are formed in the first conduction type substrate and the first conduction type buffer layer, the grooves penetrate through the first conduction type substrate layer and the first conduction type buffer layer, and the filling collector in the grooves is connected with the second conduction type collector after penetrating through the first conduction type substrate and the first conduction type buffer;
the second conductive type collectors are in an array structure separated from each other, and each of the second conductive type collectors corresponds to the trench.
2. The SiC reverse conducting insulated gate bipolar transistor device of claim 1, wherein: the gate electrode is isolated from the SiC material through a gate insulating layer and is isolated from the metal emitter positioned on the front side through an insulating medium layer; the SiC material includes a well region, an emitter region, and a drift region.
3. The SiC reverse conducting insulated gate bipolar transistor device of claim 2, wherein: the metal emitter forms ohmic contact connection with the first conduction type emitter region and the heavily doped second conduction type region at the same time.
4. The SiC reverse-conducting insulated gate bipolar transistor device according to any one of claims 1 to 3, wherein: the front structure of the first conduction type drift region is a planar gate structure or a trench gate structure.
5. The SiC reverse-conducting insulated gate bipolar transistor device according to any one of claims 1 to 3, wherein: the number of the trenches in the first conductive type substrate and the first conductive type buffer is one or more.
6. The SiC reverse-conducting insulated gate bipolar transistor device according to any one of claims 1 to 3, wherein: the plurality of trenches in the first conductivity type substrate and the first conductivity type buffer are shaped as stripes, squares, polygons, or circles, or a combination thereof.
7. The SiC reverse-conducting insulated gate bipolar transistor device according to any one of claims 1 to 3, wherein: the material for filling the plurality of grooves in the first conductive type substrate and the first conductive type buffer is one or a mixture of Cu, silver paste, alloy powder or polycrystalline silicon.
8. The SiC reverse-conducting insulated gate bipolar transistor device according to any one of claims 1 to 3, wherein: the plurality of gate electrodes are connected by a planar polysilicon arrangement.
9. A manufacturing method of a SiC reverse conducting type insulated gate bipolar transistor device is characterized by comprising the following steps:
1) selecting a first conductive type substrate;
2) growing an epitaxial layer on a first conduction type substrate to form a first conduction type buffer region and a part of a first conduction type-drift region, and forming a separated second conduction type collector region by selectively injecting second conduction type impurities;
3) continuing to grow a first conduction type-drift region on the formed second conduction type collector region;
4) blocking through a graphic mask, and forming a second conductive type well region through selective ion implantation;
5) forming a side wall on the side wall of the pattern mask in a self-alignment mode;
6) forming a first conductive type emitter region by ion implantation;
7) blocking the selective ion implantation through a graphic mask to form a heavily doped second conductive type region;
8) removing the surface mask, coating carbon film for protection, and then performing high-temperature annealing;
9) removing the carbon film and performing sacrificial oxidation treatment on the surface, and forming a gate insulating layer in a thermal oxygen growth or deposition mode;
10) depositing doped polysilicon, and forming a gate electrode by photoetching;
11) depositing silicon dioxide or/and silicon nitride, and forming an insulating medium layer through photoetching;
12) forming an ohmic contact metal layer by means of evaporation or sputtering;
13) forming a trench penetrating through the first conductive type substrate and the first conductive type buffer layer on the back surface;
14) filling a conductive material in the groove to form a filled collector, and leading out the second conductive type collector;
15) forming a metal emitter on the front surface in an evaporation or sputtering mode;
16) forming an ohmic contact metal layer on the back surface in an evaporation or sputtering mode, and forming ohmic contact with the first conductive type substrate through laser annealing;
17) and forming a back metal emitter by means of evaporation or sputtering.
10. The method of manufacturing a SiC reverse conducting insulated gate bipolar transistor device according to claim 9, wherein: after the step 11), the following steps are also included;
grinding the back of the part formed in the step 12) by using a grinding wheel to thin the first conductive type substrate, or peeling and thinning the first conductive type substrate by using laser.
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| CN116153992A (en) * | 2023-04-21 | 2023-05-23 | 上海陆芯电子科技有限公司 | Reverse-conduction insulated gate bipolar transistor |
| CN117613076A (en) * | 2023-12-08 | 2024-02-27 | 无锡用芯微电子科技有限公司 | Partitioned dual-mode conductive insulated gate bipolar transistor |
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