CN108122971B - RC-IGBT device and preparation method thereof - Google Patents
RC-IGBT device and preparation method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention discloses an RC-IGBT device and a preparation method thereof, belonging to the technical field of semiconductor power devices. According to the invention, semiconductor materials with different forbidden band widths are adopted in the traditional RC-IGBT device to form the collector short-circuit area, and the forbidden band width of the collector short-circuit area material is larger than that of the semiconductor material in contact with the collector short-circuit area material, so that a heterojunction structure with rectification characteristic is formed, and thus, the Voltage folding phenomenon (Voltage Snapback) in the forward conduction process of the traditional RC-IGBT can be eliminated by realizing a single cell structure, the current distribution and the heat distribution in a drift area are optimized, the reliability problem caused by current concentration and heat concentration is avoided, and the reverse recovery capability of the device is improved. And further adopting semiconductor materials with different forbidden band widths to form an emitting area, wherein the forbidden band width of the emitting area is larger than that of the semiconductor material in contact with the emitting area, so that the latch-up resistance of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a reverse conducting insulated gate bipolar transistor (RC-IGBTs) device and a preparation method thereof.
Background
With the continuous expansion of the depth and the breadth of the human industrial revolution, people can enjoy the convenience brought by the industrial result and simultaneously do not face various crises. Sustainable use of energy resources has been receiving attention from countries around the world as industrial "blood". And the increasing consumption of energy resources also makes people feel the energy crisis. While seeking a new source of energy as a replacement for fossil energy, people are also thinking about maximizing the utilization of energy. Electric energy is a main energy source directly utilized by human beings, and an electric power system managing the electric energy is a key way for improving the utilization rate of the electric energy. As the core of the power system, the semiconductor power device controls at least more than 70% of the world's power energy, so the power conversion capability and efficiency are high and low, which is significant for improving the utilization rate of energy resources.
Semiconductor power devices are mainly silicon-based power devices, mainly include power bipolar junction devices (BJTs), Schottky Barrier Diodes (SBDs), thyristors (SCRs), power PIN devices, power MOSFETs, insulated gate field effect transistors (IGBTs), and the like, and are widely used in the full power range. As shown in fig. 1, the conventional Trench-FSIGBT structure is one of the most widely used semiconductor power devices, and an Insulated Gate Bipolar Transistor (IGBT) combines the characteristics of a power MOSFET and a Bipolar Junction Transistor (BJT), and has the characteristics of high input impedance of the MOSFET, good temperature stability, and large current handling capability of the bipolar junction transistor, so that a good compromise characteristic can be obtained between a fast operating speed and a high power density. However, compared with the MOSFET, because the IGBT does not have a body diode of the MOSFET, the IGBT is equivalent to a PNP transistor with an open base region during reverse operation, and has no free-wheeling capability; moreover, since the IGBT does not have reverse conduction capability, in inverter circuits or other circuit applications, technicians often add an anti-parallel diode in the circuit to freewheel. With the progress of research, in order to reduce cost and improve power density and reliability of a chip, as shown in fig. 2, researchers technically integrate an anti-parallel diode and an IGBT on one chip. However, this method also brings problems such as voltage foldback (voltagessnapback) in forward application of the IGBT, increased on-state voltage drop, non-uniform current distribution in the drift region, non-uniform heat distribution, and poor reverse recovery capability of the diode, which become obstacles for the wide application of the RC-IGBT device, while reducing the manufacturing cost of the chip and increasing the power density of the chip. Wherein: the voltage folding phenomenon is generated at the initial stage of the RC-IGBT conduction, the device is in unipolar conduction, and the device is equivalently operated in a VDMOS mode. For an N-channel device, in this operation mode, electrons flow from the channel into the drift region, almost vertically flow into the N-type buffer layer or the N-type field resistance layer, and then flow out of the device after being gathered in the N-type collector short-circuit region. The movement of electrons above the P + collector region is approximately a lateral flow, so that the potential difference from the P + collector region near one side of the N-type collector short-circuit region to the P + collector region and the N-type field-stop layer on the opposite side thereof is continuously increased, and the magnitude of the potential difference determines whether the collector junction is opened or not. And with the increase of current density, the potential difference continuously rises, and the collector junction is finally opened, so that the device enters an IGBT working mode, and due to the conductance modulation effect, the conduction voltage drop is reduced, and the voltage folding phenomenon is generated. The voltage foldback phenomenon has a great negative effect on the reliability of the parallel application of the devices, and in order to solve the voltage foldback phenomenon, researchers have proposed a parallel-type conventional RC-IGBT as shown in fig. 3, in which a plurality of IGBT cells are connected in parallel to increase the lateral parasitic resistance, and the plurality of IGBT cells share one anti-parallel freewheeling diode, thereby forming one larger "cell". The traditional parallel RC-IGBT solves the problem of voltage retracing to a certain extent, but the problems of uneven current distribution, uneven heat distribution, poor reverse recovery capability and the like of a drift region can be more prominent when the IGBT and a diode work mode are both in an on-state voltage drop mode, and the compromise characteristics of forward on-state voltage drop and turn-off loss of the IGBT are poor.
Disclosure of Invention
In view of the above, the present invention provides an RC-IGBT device with a heterojunction structure and a method for manufacturing the same, which solve the problems of Voltage foldback (Voltage Snapback), increased conduction Voltage drop, non-uniform current distribution and thermal distribution in a drift region, and poor reverse recovery capability of a diode in the conventional silicon-based RC-IGBT, and the like.
The technical scheme provided by the invention is as follows:
in one aspect, the present invention provides an RC-IGBT device, the cell structure of which includes: the semiconductor drift region of the first conduction type, emitter structure and grid structure located on the upper layer of the semiconductor drift region of the first conduction type, collector structure located on the lower layer of the semiconductor drift region of the first conduction type; the emitter structure comprises a metal emitter, a first conduction type semiconductor emitter region, a second conduction type semiconductor contact region and a second conduction type semiconductor base region, the second conduction type semiconductor base region is positioned at the top of the first conduction type semiconductor drift region, the first conduction type semiconductor emitter regions are positioned on two sides of the top of the second conduction type semiconductor base region, the second conduction type semiconductor contact region is positioned between the first conduction type semiconductor emitter regions and connected with the first conduction type semiconductor emitter regions, and the metal emitter is positioned on the upper surfaces of the first conduction type semiconductor emitter regions and the second conduction type semiconductor contact region; the grid structure comprises a metal grid electrode, polycrystalline silicon and a grid medium, wherein the polycrystalline silicon is positioned in the grid medium, the metal grid electrode is positioned on the upper surface of the polycrystalline silicon, and the grid medium is positioned in the first conduction type semiconductor drift regions on two sides of the emitter structure; the collector structure comprises a second conductive type semiconductor collector region, a first conductive type semiconductor collector short-circuit region and a metal collector, the second conductive type semiconductor collector region and the first conductive type semiconductor collector short-circuit region are arranged at the bottom of the first conductive type semiconductor drift region in parallel, and the metal collector is arranged on the lower surfaces of the second conductive type semiconductor collector region and the first conductive type semiconductor collector short-circuit region; the method is characterized in that: the material of the first conduction type semiconductor drift region, the material of the second conduction type semiconductor collector region, the material of the second conduction type semiconductor contact region and the material of the second conduction type semiconductor base region are first semiconductor materials, the material of the first conduction type semiconductor collector short-circuit region is second semiconductor materials, the material of the first conduction type semiconductor emitter region is first semiconductor materials or second semiconductor materials, and the forbidden bandwidth of the second semiconductor materials is larger than that of the first semiconductor materials; a heterojunction is formed between the first conductivity type semiconductor collector short-circuiting region and the first semiconductor in contact therewith.
Further, in the present invention, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
Further, in the present invention, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor.
Further, in the present invention, the first semiconductor material is silicon, and the second semiconductor material is silicon carbide.
Furthermore, the RC-IGBT device structure can be a trench gate structure or a planar gate structure.
Further, the RC-IGBT device structure of the present invention may be an FS structure, and when the device structure is an FS structure, a first conductivity type semiconductor field stop layer is further provided between the second conductivity type semiconductor collector region and the first conductivity type semiconductor drift region.
Further, the RC-IGBT device structure in the invention may be an RC-CSTBT structure, and when the device structure is an RC-CSTBT structure, a carrier storage layer is further provided between the second conductivity type semiconductor base region and the first conductivity type semiconductor drift region.
Furthermore, a first conductivity type semiconductor region is further arranged between the first conductivity type semiconductor collector short-circuit region and the metal collector, the first conductivity type semiconductor region is made of a third semiconductor material, the forbidden bandwidth of the third semiconductor material is larger than that of the second semiconductor material, and the first conductivity type semiconductor collector short-circuit region and the first conductivity type semiconductor region form a homotype heterojunction.
Furthermore, the number of the second conductive type semiconductor collector regions and the number of the first conductive type semiconductor collector short-circuit regions are at least two, and the plurality of first conductive type semiconductor collector short-circuit regions and the plurality of second conductive type semiconductor collector regions are arranged at intervals.
Furthermore, the collector short-circuit region of the first conductivity type semiconductor in the invention is formed by at least two sections which are sequentially stacked from top to bottom.
Furthermore, the first conductive type semiconductor collector short-circuit region is uniformly doped or gradually doped.
Specifically, when the first conductivity type semiconductor collector short-circuit region is doped in a gradual manner, the doping concentration of the first conductivity type semiconductor collector short-circuit region is gradually reduced from top to bottom.
On the other hand, the invention also provides a preparation method of the RC-IGBT device, which is characterized by comprising the following steps:
manufacturing a first conductive type semiconductor drift region by adopting a first semiconductor material, and manufacturing a front structure of the RC-IGBT (resistor-capacitor-insulated gate bipolar translator) on the front surface of the first conductive type semiconductor drift region by multiple photoetching, oxidation, ion implantation, annealing and deposition processes, wherein the front structure comprises an emitter structure and a grid structure; turning over a silicon wafer, thinning the back of the silicon wafer, forming a second conductive type semiconductor collector region on the back of a first semiconductor material through photoetching and ion implantation processes, and growing a first conductive type semiconductor collector short-circuit region formed by different semiconductor materials in a preset region on the back of a first conductive type semiconductor drift region, wherein the forbidden bandwidth of the material of the first conductive type semiconductor collector short-circuit region is greater than that of the first semiconductor material; and depositing metal on the back surface to form a metal collector.
The invention is based on the traditional silicon-based RC-IGBT device structure, the semiconductor material of the collector short-circuit area is replaced by different semiconductor materials, and the forbidden bandwidth of the materials is larger than that of the semiconductor material used by the device, so that the contact interface of the collector short-circuit area and the semiconductor material above the collector short-circuit area forms homotype heterojunction. When the device is in forward conduction, the homotypic heterojunction is in a blocking mode, the current carrier injected into the drift region by the surface MOS channel cannot flow out of the heterojunction, and the current carrier reaching the collector through the heterojunction can be further prevented by changing the doping level of the collector short-circuit region, so that the device is prevented from entering an MOSFET working mode, and a path for forming a voltage folding phenomenon is cut off from the source; meanwhile, the existence of homotype heterojunction enables current carriers to form accumulation near the heterojunction, the conductivity modulation effect of a drift region is enhanced, the forward conduction characteristic of the IGBT of the RC-IGBT device is obviously improved, and the voltage folding phenomenon is inhibited; just because the suppression of the voltage folding phenomenon can be realized by a single IGBT unit cell, compared with the traditional parallel RC-IGBT, the current distribution and the heat distribution of the drift region are optimized, the reliability problem caused by current concentration and heat concentration is avoided, the reliability of parallel application of the device is improved, the compromise performance of the conduction voltage drop and the turn-off loss of the device is improved, and the power consumption is reduced. When the device is in a reverse diode, the homotype heterojunction is in a forward conduction mode, the conduction voltage drop of the diode is low, and the voltage folding phenomenon can be inhibited just because of a single IGBT unit cell, so that the reverse recovery of the diode is facilitated, the reverse recovery charge and the reverse recovery time of the diode are reduced, and the loss of a chip is reduced compared with the parallel traditional RC-IGBT. In addition, the semiconductor material of the emitter region is replaced by different semiconductor materials, and the forbidden bandwidth of the semiconductor material of the emitter region is larger than that of the semiconductor material used by the whole device, so that the forward conduction voltage drop of the special-shaped heterojunction formed by the emitter region and the base region is improved, the latch-up effect can be effectively avoided, and the reliability of the device is improved.
Compared with the prior art, the invention has the beneficial effects that:
firstly, the voltage foldback phenomenon (VoltageSnapback) in the forward conduction process of the traditional RC-IGBT can be eliminated by a single cell structure while the current-continuing capability is achieved, and the reliability of the RC-IGBT in parallel connection use is improved; the conductivity modulation effect of the drift region is enhanced, the forward conduction characteristic of the device is optimized, the compromise performance of the conduction voltage drop and the turn-off loss of the device is improved, and the power consumption is reduced.
Compared with the traditional parallel RC-IGBT, the parallel RC-IGBT has the advantages that the reliability problem caused by current concentration and heat concentration in the working mode of the IGBT and the working mode of the diode is solved, the reliability of the parallel RC-IGBT in use is improved, the forward conduction voltage drop of the diode is reduced, the reverse recovery of the diode is facilitated, the reverse recovery charge and the reverse recovery time of the diode are reduced, and the loss of a chip is reduced.
And thirdly, the starting voltage drop of a PN junction formed between the emitter region and the base region is improved, the latch-up effect is avoided, and the latch-up resistance of the RC-IGBT device is improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional IGBT device cell;
FIG. 2 is a schematic structural diagram of a conventional parallel RC-IGBT device cell;
FIG. 3 is a schematic structural diagram of a conventional RC-IGBT device cell;
fig. 4 is a schematic structural diagram of a cell of an RC-IGBT device provided in embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a cell junction of an RC-IGBT device provided in embodiment 2 of the present invention;
FIG. 6 is a band diagram of a heterojunction formed by a uniformly doped N-type silicon carbide collector short-circuited region and an N-type silicon field stop layer provided in example 1 of the present invention;
FIG. 7 is a band diagram of a heterojunction formed by a collector short-circuiting region of a graded-doped N-type silicon carbide and an N-type silicon field stop layer, which is provided in embodiment 2 of the present invention;
fig. 8 is a schematic structural diagram of a cell of an RC-IGBT device provided in embodiment 3 of the present invention;
fig. 9 is an energy band diagram of a heterojunction formed by an N-type silicon carbide collector short-circuit region and an N-type silicon field stop layer, which are formed by uniformly doped sub-regions, in the RC-IGBT device provided in embodiment 3 of the present invention;
fig. 10 is an energy band diagram of a heterojunction formed by the N-type silicon carbide collector short-circuit region and the N-type silicon field stop layer, which are formed by the graded doping partition and the uniform doping partition, in the RC-IGBT device provided in embodiment 3 of the present invention;
fig. 11 is a schematic structural diagram of a cell of an RC-IGBT device provided in embodiment 4 of the present invention;
fig. 12 is an energy band diagram of a heterojunction formed by an N-type silicon carbide collector short-circuit region and an N-type silicon field stop layer, which are formed by uniformly doped sub-regions, in the RC-IGBT device provided in embodiment 4 of the present invention;
fig. 13 is an energy band diagram of a heterojunction formed by the N-type silicon carbide collector short-circuit region and the N-type silicon field stop layer, which are formed by the graded doping partition and the uniform doping partition, in the RC-IGBT device provided in embodiment 4 of the present invention;
fig. 14 is a schematic structural diagram of a RC-IGBT device cell provided in embodiment 5 of the present invention;
fig. 15 is an energy band diagram of a heterojunction formed by a uniformly doped N + silicon carbide collector short-circuit partition, an N-type silicon semiconductor region of an ultra-wide bandgap, and an N-type silicon field stop layer in an RC-IGBT device according to embodiment 5 of the present invention;
FIG. 16 is an energy band diagram of an N + silicon emitter region and a P-type silicon base region forming a PN junction;
FIG. 17 is a band diagram of an N + silicon carbide emitter region and a P-type silicon base region forming a P-Si/N-SiC heterojunction;
FIG. 18 is a schematic view of a silicon N-type silicon substrate selected by the method for manufacturing the RC-IGBT device according to the present invention;
FIG. 19 is a schematic diagram of a P-type silicon base region formed by an ion implantation process in the method for manufacturing an RC-IGBT device according to the present invention;
FIG. 20 is a schematic diagram of a trench formed by a trench etching process in the method for manufacturing an RC-IGBT device according to the present invention;
FIG. 21 is a schematic diagram of a method for fabricating an RC-IGBT device according to the present invention, wherein a gate dielectric is formed by a dry oxygen oxidation process;
FIG. 22 is a schematic diagram of a method for manufacturing an RC-IGBT device according to the present invention, in which N + polysilicon is formed by a polysilicon deposition process;
fig. 23 is a schematic diagram of an N + silicon emitter region formed by photolithography, ion implantation and other processes according to the method for manufacturing an RC-IGBT device provided by the present invention;
fig. 24 is a schematic diagram of a P + silicon contact region formed by photolithography, ion implantation and other processes according to the method for manufacturing an RC-IGBT device provided by the present invention;
fig. 25 is a schematic diagram of the method for manufacturing an RC-IGBT device according to the present invention, which performs N-type silicon ion implantation through back-side photolithography, ion implantation, and the like, and then completes a junction-pulling process to form an N-type silicon field stop layer;
fig. 26 is a schematic diagram of forming a P + collector region by performing P-type silicon ion implantation through the processes of photolithography, ion implantation, and the like in the method for manufacturing an RC-IGBT device according to the present invention;
FIG. 27 is a schematic diagram of an N-type silicon carbide collector short-circuited region formed by a local laser annealing process in the method for manufacturing an RC-IGBT device according to the present invention;
fig. 28 is a schematic diagram of a metal gate electrode, a metal emitter and a metal collector formed by deposition and photolithography processes according to the method for manufacturing the RC-IGBT device provided by the present invention.
In the figure: the structure comprises a substrate, a substrate.
Detailed Description
The principles and features of the present invention will be described in detail below with reference to the accompanying drawings and embodiments:
the cell structure of the conventional field-resistance type RC-IGBT device is shown in fig. 3, and includes: the N-type silicon drift region 4, an emitter structure and a gate structure which are positioned on the upper layer of the N-type silicon drift region 4, and a collector structure which is positioned on the lower layer of the N-type silicon drift region 4; the emitter structure comprises a metal emitter 8, an N + silicon emitter region 9, a P + silicon contact region 10 and a P type silicon base region 11, the P type silicon base region 11 is positioned at the top of the N type silicon drift region 4, the N + silicon emitter region 9 is positioned on two sides of the top of the P type silicon base region 11, the P + silicon contact region 10 is positioned between the N + silicon emitter regions 9 and connected with the N + silicon emitter regions 9, and the metal emitter 8 is positioned on the upper surfaces of the N + silicon emitter region 9 and the P + silicon contact region 10; the gate structure comprises a metal gate electrode 1, polycrystalline silicon 2 and a gate dielectric 3, wherein the polycrystalline silicon 2 is positioned in the gate dielectric 3, the metal gate electrode 1 is positioned on the upper surface of the polycrystalline silicon 2, and the gate dielectric 3 is positioned in N-type silicon drift regions 4 on two sides of the emitter structure; the collector structure comprises a P-type silicon collector region 6, an N-type silicon collector short-circuit region 12 and a metal collector 7, the N-type silicon field resistance layer 5 is located at the bottom of the N-type silicon drift region 4, the P-type silicon collector region 6 and the N-type silicon collector short-circuit region 12 are located at the bottom of the N-type silicon field resistance layer 5 in parallel, and the metal collector 7 is located on the lower surfaces of the P-type silicon collector region 6 and the N-type silicon collector short-circuit region 12.
Example 1:
an RC-IGBT device whose cell structure is shown in fig. 4, includes: the N-type silicon drift region 4, an emitter structure and a gate structure which are positioned on the upper layer of the N-type silicon drift region 4, and a collector structure which is positioned on the lower layer of the N-type silicon drift region 4; the emitter structure comprises a metal emitter 8, an N + silicon emitter region 9, a P + silicon contact region 10 and a P type silicon base region 11, the P type silicon base region 11 is positioned at the top of the N type silicon drift region 4, the N + silicon emitter region 9 is positioned on two sides of the top of the P type silicon base region 11, the P + silicon contact region 10 is positioned between the N + silicon emitter regions 9 and connected with the N + silicon emitter regions 9, and the metal emitter 8 is positioned on the upper surfaces of the N + silicon emitter region 9 and the P + silicon contact region 10; the gate structure comprises a metal gate electrode 1, polycrystalline silicon 2 and a gate dielectric 3, wherein the polycrystalline silicon 2 is positioned in the gate dielectric 3, the metal gate electrode 1 is positioned on the upper surface of the polycrystalline silicon 2, and the gate dielectric 3 is positioned in N-type silicon drift regions 4 on two sides of the emitter structure; the collector structure comprises a P-type silicon collector region 6, an N-type silicon carbide collector short-circuit region 13 and a metal collector 7, the N-type silicon field resistance layer 5 is positioned at the bottom of the N-type silicon drift region 4, the P-type silicon collector region 6 and the N-type silicon carbide collector short-circuit region 13 are positioned at the bottom of the N-type silicon field resistance layer 5 in parallel, and the metal collector 7 is positioned on the lower surfaces of the P-type silicon collector region 6 and the N-type silicon carbide collector short-circuit region 13; an N-Si/N-SiC heterojunction is formed between the N + silicon carbide collector short-circuit region 13 and the upper part of the N + silicon carbide collector short-circuit region, and a P-Si/N-SiC heterojunction is formed at the interface of the N type silicon carbide collector short-circuit region 13 and the P type silicon collector region 6.
The thicknesses of the metal collector 7, the metal emitter 8 and the metal gate electrode 1 in the embodiment are 3-6 μm; the thickness of the N-type silicon drift region 4 is about 100-150 μm, and the doping concentration is about 5 × 1013～5×1014/cm3(ii) a The grid structure adopts a groove grid structure, the depth of the groove grid structure is about 3-6 μm, and the width of the groove grid structure is about 0.6-3 μm; the width of the unit cell of the device is about 4-8 μm; the depth of the P-type silicon base region 11 is about 2.5-5 μm, and the width thereofThe degree is about 2-5 μm, and the doping is about 1 × 1016～5×1017/cm3(ii) a The N + silicon emitter region 9 has a thickness of about 0.2 μm to about 0.5 μm, a width of about 0.2 μm to about 0.5 μm, and a doping concentration of about 5X 1018～5×1019/cm3(ii) a The thickness of the P-type silicon collector region 6 is about 0.2-0.5 μm, and the doping concentration is about 1 × 1018～5×1019cm-3(ii) a The thickness of the N-type silicon field resistance layer 5 is about 2-15 μm, and the doping concentration is about 1 × 1015～1×1017/cm3(ii) a The N-type silicon carbide collector short-circuit region 13 has a width of about 0.5-2 μm, a thickness of about 0.2-0.5 μm, and a doping concentration of about 1 × 1016～5×1018/cm3。
As shown in fig. 6, the energy band diagram of the N-Si/N-SiC heterojunction formed by the uniformly doped N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5.
Example 2:
the present embodiment is different from embodiment 1 in that: the number of the P-type silicon collector region 6 and the N-type silicon carbide collector short-circuit region 13 is different; in this embodiment, the number of the N-type silicon carbide collector short-circuit regions 13 and the number of the P-type silicon collector regions 6 are not less than two, and the plurality of N-type silicon carbide collector short-circuit regions 13 and the plurality of P-type silicon collector regions 6 are arranged at intervals, as shown in fig. 5.
Compared with the embodiment 1, the current can reach the collector short-circuit region only through a transverse resistor at a position far away from the collector short-circuit region, and the resistance value of the transverse resistor formed by the RC-IGBT above the P-type silicon collector region 6 is reduced because the Si/SiC heterojunction is uniformly distributed at the metal collector 7 and has small interval, so that the loss of conduction voltage drop when the current passes through the transverse resistor is reduced, and the conduction voltage drop of the IGBT and the diode in the working mode is effectively reduced; meanwhile, the narrow intervals of the P-type silicon collector region 6 and the N-type silicon carbide collector short-circuit region 13 are uniformly distributed, so that the current distribution and the heat distribution of the N-type silicon drift region 4 are uniform. Therefore, the device structure of the embodiment can further improve the conduction voltage drop in the IGBT working mode and the diode working mode, and simultaneously improve the uniformity of the current and the heat distribution in the drift region.
Example 3:
the present embodiment is different from embodiment 1 in that: the N-type silicon carbide collector short-circuit region 13 is formed by adopting gradual doping; the gradual doping in this embodiment specifically means that the doping concentration of the N-type silicon carbide collector short-circuit region 13 gradually decreases from top to bottom (i.e., the doping concentration gradually decreases from the junction of the N-type silicon field stop layer 5 and the N-type silicon carbide collector short-circuit region 13 to the interface of the N-type silicon carbide collector short-circuit region 13 and the metal collector 7).
FIG. 7 shows the band diagram of the N-Si/N-SiC heterojunction formed by the N-type doped silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5. Compared with embodiment 1, the additional electron barrier provided by the present embodiment further prevents the electron current reaching the metal collector 7 through diffusion via the N-Si/N-SiC heterojunction when the device IGBT is turned on in the forward direction, further improves the conductance modulation of the N-type drift region, reduces the forward on-state voltage drop of the IGBT, and obtains a better compromise of the on-state voltage drop and the turn-off loss of the device.
Example 4:
the present embodiment is different from embodiment 1 in that: the N-type silicon carbide collector short-circuiting region 13 is composed of a first partition 13a and a second partition 13b which are different in doping concentration, both the first partition 13a and the second partition 13b are uniformly doped, and the doping concentration of the first partition 13a is greater than that of the second partition 13b, as shown in fig. 8.
As shown in fig. 9, the energy band diagram of the N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5 forming an N-Si/N-SiC heterojunction. Compared with embodiment 1, the additional electron barrier provided by the present embodiment further prevents the electron current reaching the metal collector 7 through diffusion via the N-Si/N-SiC heterojunction when the device IGBT is turned on in the forward direction, further improves the conductance modulation of the N-type drift region, reduces the forward on-state voltage drop of the IGBT, and obtains a better compromise of the on-state voltage drop and the turn-off loss of the device.
Example 5:
the present embodiment is different from embodiment 4 in that: the first subarea 13a adopts gradual doping; the doping concentration of the first segment 13a gradually decreases from top to bottom (i.e., the doping concentration gradually decreases from the junction of the N-type silicon field stop layer 5 and the first segment 13a to the interface of the first segment 13a and the second segment 13 b).
As shown in fig. 10, the energy band diagram of the N-type silicon carbide collector short-circuiting region 13 and the N-type silicon field stop layer 5 forming an N-Si/N-SiC heterojunction. Compared with embodiment 4, the additional electron barrier provided by this embodiment further prevents the electron current reaching the metal collector 7 through diffusion via the N-Si/N-SiC heterojunction when the device IGBT is turned on in the forward direction, further improves the conductance modulation of the N-type drift region, reduces the forward on-state voltage drop of the IGBT, and obtains a better compromise of the on-state voltage drop and the turn-off loss of the device.
Example 6:
the present embodiment is different from embodiment 4 in that: the N-type silicon carbide collector short-circuit region 13 is composed of a first region 13a, a second region 13b and a third region 13c which are different in doping concentration; all three of the first, second and third sections 13a, 13b, 13c are uniformly doped, and the doping concentration of each of the first and third sections 13a, 13c is greater than that of the second section 13b, as shown in fig. 11.
As shown in fig. 12, is an energy band diagram of the N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5 forming an N-Si/N-SiC heterojunction. This embodiment further improves the contact characteristics of the N-type silicon carbide collector short-circuiting region 13 and the metal collector, compared to embodiment 4.
Example 7:
the present embodiment is different from embodiment 6 in that: the second partition 13b is doped in a gradient manner, and the doping concentration of the second partition 13b is gradually reduced from top to bottom (i.e. the doping concentration is gradually reduced from the junction surface of the N-type silicon field stop layer 5 and the second partition 13b to the interface surface of the second partition 13b and the third partition 13 c).
As shown in fig. 13, is the energy band diagram of the N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5 forming an N-Si/N-SiC heterojunction. Compared with embodiment 6, the additional electron barrier provided by this embodiment further prevents the electron current reaching the metal collector 7 through diffusion via the N-Si/N-SiC heterojunction when the device IGBT is turned on in the forward direction, further improves the conductance modulation of the N-type drift region, reduces the forward on-state voltage drop of the IGBT, and obtains a better compromise of the on-state voltage drop and the turn-off loss of the device.
Example 8:
the present embodiment is different from embodiment 1 in that: an N-type semiconductor region 14 is further arranged between the N-type silicon carbide collector short-circuit region 13 and the metal collector 7, the material of the N-type semiconductor region 14 is an ultra-wide forbidden band third semiconductor material, the forbidden band width of the material of the N-type semiconductor region is larger than that of the material of the N-type silicon carbide collector short-circuit region 13, and the ultra-wide forbidden band third semiconductor material can be Ga2O3Sapphire, diamond, or any suitable ultra-wide bandgap semiconductor material; the N-type silicon carbide collector short-circuiting region 13 forms a homotype heterojunction with the N-type semiconductor region 14 as shown in fig. 14.
As shown in fig. 15, it is an energy band diagram of N-Si/N-SiC/N-type ultra wide bandgap semiconductor heterojunction formed by the N-type semiconductor region 14, the N-type silicon carbide collector short-circuit region 13 and the N-type silicon field stop layer 5.
Compared with embodiment 1, the additional electron barrier provided by the present embodiment further prevents the electron current reaching the metal collector 7 through diffusion via the N-Si/N-SiC heterojunction when the device IGBT is turned on in the forward direction, further improves the conductance modulation of the N-type drift region, reduces the forward on-state voltage drop of the IGBT, and obtains a better compromise of the on-state voltage drop and the turn-off loss of the device.
Example 9:
the present embodiment is different from embodiment 1 in that: the N + silicon emitter region 9 is replaced with an N + silicon carbide emitter region 91.
Fig. 16 is an energy band diagram of a PN junction formed by a conventional N + silicon emitter region 9 and a P-type silicon base region 11, and fig. 17 is an energy band diagram of a heterojunction formed by an N + silicon carbide emitter region 91 and a P-type silicon base region 11 in this embodiment.
Example 10:
the method for manufacturing the 1200VRC-IGBT device is taken as an example to explain, and the devices with different performance parameters can be manufactured according to actual requirements according to the common knowledge in the field.
A preparation method of an RC-IGBT device is characterized by comprising the following steps: the method comprises the following steps:
step 1: as shown in FIG. 18, an N-type lightly doped monocrystalline silicon wafer with a thickness of 500 μm to 700 μm and a doping concentration of about 5 × 10 is used as the N-type silicon drift region 4 of the device13～5×1014/cm3(ii) a According to the common knowledge in the field, the step can also be realized by directly selecting an FS substrate and then extending the N-type silicon drift region 4 on the FS substrate, so that the FS layer does not need to be prepared in the subsequent process;
step 2: as shown in fig. 19, boron ion implantation is performed on the top layer of the N-type silicon drift region 4 by an ion implantation process, and then junction is pushed at a certain temperature, wherein the energy of the ion implantation is 60-120 keV, and the implantation dose is 1 × 1013～1×1014/cm2The annealing temperature is 1100-1150 ℃, the annealing time is 10-30 minutes, and the doping concentration formed by the above operations is about 1 multiplied by 1016～5×1017/cm3A P-type silicon-based region 11 with a depth of about 2.5-5 μm;
and step 3: as shown in fig. 20, trenches with a depth of about 3 μm to 6 μm and a width of about 0.5 μm to 3 μm are etched on both sides of the N-type silicon drift region 4 by a trench etching process;
step 4: as shown in FIG. 21, O at 1050 deg.C-1150 deg.C2Forming a gate dielectric 3 by a dry oxygen oxidation process under an atmosphere;
and 5: as shown in fig. 22, a polysilicon layer is formed by a polysilicon deposition process at 750 to 950 ℃, and excess polysilicon is removed by etching process to form N + polysilicon 2;
step 6: as shown in fig. 23, the implantation of phosphorus ions is completed by photolithography, ion implantation, and annealing treatment, and then junction pushing is performed at a certain temperature, the ion implantation energy is 10-30 keV, and the implantation dose is 1 × 1014～1×1015/cm2Annealing at 950 ℃ for 10-30 minutes, and forming a thick layer on two sides of the top layer of the P-type silicon-based region 11 by the above operationA degree of about 0.2 μm to about 0.5 μm, a width of about 0.2 μm to about 0.5 μm, and a doping concentration of about 5X 1018～5×1019/cm3The N + silicon emitter region 9;
and 7: as shown in fig. 24, the implantation of phosphorus ions is completed by photolithography, ion implantation, and annealing treatment, and then junction pushing is performed at a certain temperature, the ion implantation energy is 10-30 keV, and the implantation dose is 1 × 1014～1×1015/cm2The annealing temperature is 950 ℃, the annealing time is 10-30 minutes, the thickness of the N + silicon emitting region 9 is about 0.2-0.5 μm, the doping is about 1 multiplied by 1018～5×1019cm-3P + silicon contact region 10;
and 8: as shown in fig. 25, the silicon wafer is turned over, phosphorus ion implantation is performed three times through the processes of back side lithography, ion implantation and the like, the maximum implantation energy is about 1500-2000 keV, then a laser annealing process is completed, and an N-type silicon field stop layer 5 with the thickness of about 2-15 μm is formed at the bottom of the N-type silicon drift region 4;
and step 9: as shown in fig. 26, boron ion implantation is performed by back side lithography, ion implantation, etc., with an implantation energy of 10 to 30keV and an implantation dose of 1 × 1012～5×1013/cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 350-450 ℃ for 20-40 minutes, or finishing annealing by adopting a laser annealing process, and forming a P-type silicon collector region 6 at the bottom of the N-type silicon field resistance layer 5 by the above operation;
step 10: as shown in fig. 27, a local laser annealing process is used to grow a silicon carbide material in a preset region, and the specific operations are as follows: firstly, ultrasonically cleaning the back of a silicon wafer by using acetone and isopropanol, then cleaning the back of the silicon wafer in deionized water, washing the silicon wafer by using diluted hydrofluoric acid, and then cleaning the silicon wafer by using deionized water; spin coating PMMA with the thickness of about 300-500 nm on the back of a silicon wafer in a spin coating mode, baking the silicon wafer for 90 seconds at the temperature of 180 ℃, then placing the silicon wafer in an XYZ mechanical arm under the conditions of room temperature and normal pressure, then radiating the silicon wafer by using a high-power KrF laser, decomposing the PMMA into solid carbon under the radiation of the high-power laser, and meanwhile, under the radiation of the high-power laser, decomposing PMMA to be solid carbon below PMMAThe silicon is radiated by high-energy laser to be in a molten state, under the condition, the solid carbon and the molten silicon react rapidly to generate silicon carbide, the required thickness and width of the silicon carbide can be obtained by adjusting the parameters of a laser and PMMA (polymethyl methacrylate), and after the required thickness and width of the silicon carbide are obtained in a preset area on the back of the silicon wafer, the silicon carbide is implanted by high-energy ions and annealed to form the silicon carbide with the doping concentration of about 1 × 1016～5×1018/cm3An N-type silicon carbide collector short-circuit region 13 with the thickness of 0.2-0.5 μm and the width of 0.5-2 μm;
step 11: as shown in fig. 28, the metal gate electrode 1, the metal emitter 8, and the metal collector 7 are formed by deposition, photolithography, and etching processes.
Specifically, when the N-type silicon carbide collector short-circuit region 13 is formed in step 10, by adjusting local laser annealing process parameters and high-energy ion implantation process parameters, the uniformly doped N-type silicon carbide collector short-circuit region 13 may be formed, the gradually doped N-type silicon carbide collector short-circuit region 13 may also be formed, and the N-type silicon carbide collector short-circuit regions 13 formed by sequentially stacking a plurality of N-type silicon carbide collector short-circuit regions with different doping concentrations from bottom to top may also be formed.
Example 11:
the difference of this embodiment from example 10 is that: in step 10, a groove is formed in the P-type silicon collector region 6 by etching, then silicon carbide is epitaxially grown in the groove in an impurity-containing atmosphere, and the N-type silicon carbide collector short-circuit region 13 is obtained by etching the redundant silicon carbide material.
Example 12:
the difference of this embodiment from example 10 is that: when the N + silicon emitter region 9 is formed in step 6, a step of growing a silicon carbide material by using the local laser annealing process of step 10 is further included, thereby forming an N + silicon carbide emitter region 91.
It is to be claimed here that: according to the common knowledge in the field, the technical characteristics of the RC-IGBT device structure and the preparation process can be combined with each other; the dielectric material is not limited to silicon dioxide mentioned in the examples, and can also be realized by high-K dielectric materials such as silicon nitride (Si3N4), hafnium dioxide (HfO2), aluminum oxide (Al2O3) and the like; the semiconductor material with the forbidden band width larger than that of the semiconductor substrate used by the device is not limited to silicon carbide, and can be any suitable semiconductor material such as gallium nitride, diamond and the like; the device structure is not only suitable for a trench gate RC-IGBT, but also suitable for a planar gate RC-IGBT, an RC-CSTBT, an FSRC-IGBT and an NPTRC-IGBT; the specific implementation of the manufacturing process can also be adjusted according to actual needs.
While the present invention has been described with reference to the embodiments illustrated in the drawings, the present invention is not limited to the embodiments, which are illustrative rather than restrictive, and it will be apparent to those skilled in the art that many more modifications and variations can be made without departing from the spirit of the invention and the scope of the appended claims.
Claims (5)
1. A cell structure of an RC-IGBT device comprises: the semiconductor drift region of the first conduction type, emitter structure and grid structure located on the upper layer of the semiconductor drift region of the first conduction type, collector structure located on the lower layer of the semiconductor drift region of the first conduction type; the emitter structure comprises a metal emitter, a first conduction type semiconductor emitter region, a second conduction type semiconductor contact region and a second conduction type semiconductor base region, the second conduction type semiconductor base region is positioned at the top of the first conduction type semiconductor drift region, the first conduction type semiconductor emitter regions are positioned on two sides of the top of the second conduction type semiconductor base region, the second conduction type semiconductor contact region is positioned between the first conduction type semiconductor emitter regions and connected with the first conduction type semiconductor emitter regions, and the metal emitter is positioned on the upper surfaces of the first conduction type semiconductor emitter regions and the second conduction type semiconductor contact region; the grid structure comprises a metal grid electrode, polycrystalline silicon and a grid medium, wherein the polycrystalline silicon is positioned in the grid medium, the metal grid electrode is positioned on the upper surface of the polycrystalline silicon, and the grid medium is positioned in the first conduction type semiconductor drift regions on two sides of the emitter structure; the collector structure comprises a second conductive type semiconductor collector region, a first conductive type semiconductor collector short-circuit region and a metal collector, the second conductive type semiconductor collector region and the first conductive type semiconductor collector short-circuit region are arranged at the bottom of the first conductive type semiconductor drift region in parallel, and the metal collector is arranged on the lower surfaces of the second conductive type semiconductor collector region and the first conductive type semiconductor collector short-circuit region; the method is characterized in that: the material of the first conduction type semiconductor drift region, the material of the second conduction type semiconductor collector region, the material of the second conduction type semiconductor contact region and the material of the second conduction type semiconductor base region are first semiconductor materials, the material of the first conduction type semiconductor collector short-circuit region is second semiconductor materials, the material of the first conduction type semiconductor emitter region is first semiconductor materials or second semiconductor materials, and the forbidden bandwidth of the second semiconductor materials is larger than that of the first semiconductor materials; a heterojunction is formed between the first conductive type semiconductor collector short-circuit region and the first semiconductor material in contact with the first conductive type semiconductor collector short-circuit region;
the first conductive type semiconductor collector short-circuit region is doped in a gradual change mode or at least formed by stacking two subareas with different doping concentrations from top to bottom.
2. An RC-IGBT device according to claim 1, characterized in that: and a first-conductivity-type semiconductor field stop layer is arranged between the second-conductivity-type semiconductor collector region and the first-conductivity-type semiconductor drift region.
3. An RC-IGBT device according to claim 1, characterized in that: the first semiconductor material is silicon and the second semiconductor material is silicon carbide.
4. An RC-IGBT device according to claim 1, characterized in that: the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
5. A preparation method of an RC-IGBT device is characterized by comprising the following steps:
manufacturing a first conductive type semiconductor drift region by adopting a first semiconductor material, and manufacturing a front structure of the RC-IGBT (resistor-capacitor-insulated gate bipolar translator) on the front surface of the first conductive type semiconductor drift region by multiple photoetching, oxidation, ion implantation, annealing and deposition processes, wherein the front structure comprises an emitter structure and a grid structure; the method comprises the steps that a silicon wafer is turned over, the back of the silicon wafer is thinned, a second conductive type semiconductor collector region is formed on the back of a first semiconductor material through photoetching and ion implantation processes, a first conductive type semiconductor collector short-circuit region formed by growing different semiconductor materials in a preset region on the back of a first conductive type semiconductor drift region is formed, the forbidden bandwidth of the material of the first conductive type semiconductor collector short-circuit region is larger than that of the first semiconductor material, and the first conductive type semiconductor collector short-circuit region is formed by gradual doping or at least two regions with different doping concentrations are stacked from top to bottom; and depositing metal on the back surface to form a metal collector.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921146A (en) * | 2005-08-15 | 2007-02-28 | 国际整流器公司 | Deep N diffusion for trench IGBT |
| CN102318071A (en) * | 2008-12-15 | 2012-01-11 | Abb技术有限公司 | Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device |
| CN102779847A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | Carrier stored groove bipolar transistor |
| CN105226091A (en) * | 2015-11-10 | 2016-01-06 | 株洲南车时代电气股份有限公司 | A kind of igbt and preparation method thereof |
-
2017
- 2017-12-25 CN CN201711425125.9A patent/CN108122971B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1921146A (en) * | 2005-08-15 | 2007-02-28 | 国际整流器公司 | Deep N diffusion for trench IGBT |
| CN102318071A (en) * | 2008-12-15 | 2012-01-11 | Abb技术有限公司 | Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device |
| CN102779847A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | Carrier stored groove bipolar transistor |
| CN105226091A (en) * | 2015-11-10 | 2016-01-06 | 株洲南车时代电气股份有限公司 | A kind of igbt and preparation method thereof |
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