CN115020479B - Depletion type silicon carbide bipolar device structure and manufacturing method - Google Patents
Depletion type silicon carbide bipolar device structure and manufacturing method Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 68
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 150000002500 ions Chemical class 0.000 claims abstract description 34
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims description 40
- 238000000151 deposition Methods 0.000 claims description 11
- 239000007769 metal material Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000011084 recovery Methods 0.000 abstract description 5
- 230000005669 field effect Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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- 239000010409 thin film Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to the technical field of power semiconductors, and particularly provides a depletion type silicon carbide bipolar device structure and a manufacturing method thereof, wherein the depletion type silicon carbide bipolar device structure comprises a front-stage part and a rear-stage part, and the front-stage part is a silicon carbide JFET (junction field effect transistor) structure; the rear-stage part is positioned at the lower part of the device structure, and in the rear-stage part, the N < + > -type substrate layer, the N < + > -ion injection region, the Schottky metal contact region and the collector metal layer form a Schottky diode structure; the N + type substrate layer, the P + ion injection region, the ohmic contact region and the collector metal layer form a PN junction diode structure, and the Schottky diode structure and the PN junction diode structure are arranged at intervals along the length direction of the collector metal layer. The invention has the conductivity modulation effect of a PN junction diode and the low conduction loss and fast reverse recovery capability of a Schottky diode, and can reduce the conduction resistance of the invention.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a depletion type silicon carbide bipolar device structure and a manufacturing method thereof.
Background
Silicon carbide (SiC), a novel wide bandgap semiconductor material, has the advantages of high temperature resistance, radiation resistance, high switching speed and high working frequency, and is widely applied in the technical field of high-voltage power semiconductors. Although the performance of the semiconductor device can be greatly improved by the silicon carbide material, there are still many challenges in device design and process, such as gate oxide reliability, trench process, ohmic contact, etc.
In recent years, siC MOSFET device products are continuously appearing in the power semiconductor market, and have a wide application prospect in the fields of new energy automobiles, photovoltaic solar inverters and the like due to the fact that SiC MOSFET devices have low on-resistance and high switching speed. The SiC MOSFET is a unipolar device, the drift region resistance of the MOSFET increases in a square relation with the blocking voltage, and when the blocking voltage is 10kV or more, the on-resistance of the SiC MOSFET rapidly increases due to its unipolar characteristic, and the application in the high-voltage and large-current field is limited.
Although the trench SiC MOSFET reduces the resistance of the FET region compared to a planar SiC MOSFET, the quality of the gate oxide layer has a very important influence on the carrier mobility and gate oxide reliability of the device, particularly in the high-voltage MOSFET device structure, because the thin film growth process of the silicon carbide gate oxide layer material is not mature. At present, a trench gate SiC MOSFET device with a withstand voltage of 10kV or more is still not developed, mainly because: under the high-voltage condition of 10kV and above, the quality of the SiC gate oxide layer is very unreliable, and the electric field born by the gate oxide under the trench gate structure is far higher than the critical breakdown field strength of the material, so that the existing SiC power device has low reliability under the high-voltage condition.
In addition, the IGBT structure has lower on-resistance in a large-current conducting state due to the conductivity modulation effect of the PN junction under the conducting condition, so that the IGBT structure has great advantage in solving the problem of high voltage and large current. The SiC IGBT can easily realize the voltage withstanding capability of 10kV or above, and has important application prospects in the high-voltage power transmission fields of high-voltage power grids, rail transit and the like. However, for the SiC IGBT device, since the SiC PN junction conduction voltage drop is about 2.7V, the SiC IGBT still has high conduction loss under a high current condition, and the SiC IGBT needs to be connected in anti-parallel with an external fast recovery diode in the application process, which results in high device cost and low reliability.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the background art and to providing a depletion type silicon carbide bipolar device structure and a method for fabricating the same.
To achieve the above object, the present invention provides a depletion type silicon carbide bipolar device structure, comprising:
an N-type buffer layer;
the N-type drift layer is formed on the N-type buffer layer, and one side of the N-type drift layer, which is far away from the N-type buffer layer, is provided with two symmetrical groove structures;
the P-type doped regions are formed on the side walls and the bottoms of the two groove structures of the N-type drift layer;
the P + ohmic contact region is formed on the P-type doped region;
an N + ohmic contact region formed on the N-type drift layer and the P-type doped region;
the insulating medium layer is formed on the side wall of the P-type doped region;
a gate metal layer formed on the P + ohmic contact region;
an emitter metal layer formed on the N + ohmic contact region;
further comprising:
an N + type underlayer;
an N + ion implantation region formed below the N + type substrate layer;
the P + ion implantation regions and the N + ion implantation regions are formed under the N + type substrate layer at intervals along the length direction of the N + type substrate layer;
the Schottky metal contact region is correspondingly formed below the N + ion implantation region;
the ohmic contact region is correspondingly formed below the P + ion implantation region;
a collector metal layer formed under the Schottky metal contact region and the ohmic contact region.
According to an aspect of the invention, the collector metal layer is formed of metal Ti, ni or Ag.
According to an aspect of the invention, the schottky metal contact region is formed of a metal material Ti, pt, sb, co or Mo.
According to an aspect of the present invention, the N + -type substrate layer has a thickness of 50 to 200 μm.
According to an aspect of the present invention, the N-type buffer layer has a thickness of 0.5 to 2 μm.
According to an aspect of the invention, the N-type drift layer has a thickness of 3 to 150 μm.
According to one aspect of the invention, the P-type doped region is a P-type doped SiC layer, formed by ion implantation of Al ions.
According to one aspect of the invention, the insulating dielectric layer is made of SiO 2 SiN or HfO.
According to an aspect of the invention, the gate metal layer and the emitter metal layer are both formed of metal Al.
In order to achieve the above object, the present invention further provides a method for preparing the above depletion type silicon carbide bipolar device structure, comprising:
s01, extending the N-type buffer layer on the N + type substrate layer, and extending the N-type drift layer on the N-type buffer layer;
s02, etching a groove structure on the N-type drift layer, and injecting high-energy Al ions into the side wall and the bottom of the groove structure to form the P-type doped region;
s03, injecting N-type ions into the N-type drift layer to form an N + ohmic contact region;
s04, injecting P-type ions into the P-type doped region to form the P + ohmic contact region;
s05, respectively implanting ions into the N-type drift layer and the P-type doped region, and then annealing the device at a high temperature of 1600-2000 ℃;
s06, growing the insulating medium layer on the side wall of the groove structure;
s07, depositing metal Al on the P + ohmic contact area and the N + ohmic contact area respectively to form the grid metal layer and the emitter metal layer;
s08, thinning one side, far away from the N-type buffer layer, of the N + type substrate layer;
s09, injecting P-type ions into one side, far away from the N-type buffer layer, of the N + type substrate layer to form the P + ion injection region, wherein the part, not injected with the P + type ions, of the N + type substrate layer forms the N + ion injection region;
s10, depositing a Schottky metal material on one side of the N + ion injection region, which is far away from the N-type buffer layer, to form the Schottky metal contact region, and making ohmic contact on one side of the P + ion injection region, which is far away from the N-type buffer layer, to form the ohmic contact region;
and S11, depositing a metal material on the Schottky metal contact region and the ohmic contact region on the side far away from the N-type buffer layer to form the collector metal layer.
According to the scheme of the invention, the device comprises a preceding stage part and a rear stage part, wherein the preceding stage part is positioned at the upper part of the device structure and comprises a silicon carbide JFET structure comprising an N-type buffer layer, an N-type drift layer, a P-type doped region, a P + ohmic contact region, an N + ohmic contact region, an insulating dielectric layer, a grid metal layer and an emitter metal layer; the rear-stage part is positioned at the lower part of the device structure and comprises an N + type substrate layer, a collector metal layer, an ohmic contact region, a Schottky metal contact region, an N + ion injection region and a P + ion injection region, wherein in the rear-stage part, the N + type substrate layer, the N + ion injection region, the Schottky metal contact region and the collector metal layer form a Schottky diode structure; the N + type substrate layer, the P + ion injection region, the ohmic contact region and the collector metal layer form a PN junction diode structure, and the Schottky diode structure and the PN junction diode structure are arranged at intervals along the length direction of the collector metal layer. The N-type buffer layer is connected with the N + type substrate layer and is used for connecting the front-stage part and the rear-stage part in series. The silicon carbide JFET structure is introduced into the front-stage part, so that the silicon carbide JFET structure has the advantages of high withstand voltage and low conduction loss.
According to the scheme of the invention, the silicon carbide JFET structure is introduced into the preceding stage part, the characteristic of multistage series connection can be realized by utilizing the silicon carbide JFET, the multistage combination design of the silicon carbide JFET structure, the Schottky diode structure and the PN junction diode structure is realized, and larger series resistance cannot be introduced.
According to the scheme of the invention, on the basis of introducing the silicon carbide JFET structure into the front-stage part, the rear-stage part adopts the combined design of the Schottky diode structure and the PN junction diode structure, and the normally open characteristic of the silicon carbide JFET is utilized, so that the channel resistance of the device can be effectively reduced. Furthermore, a transverse alternating arrangement design of a Schottky diode structure and a PN junction diode structure is introduced at the bottom of the silicon carbide JFET structure, so that the conductivity modulation effect of the PN junction diode and the low conduction loss and fast reverse recovery capability of the Schottky diode are achieved, and the on-resistance of the Schottky diode can be further reduced.
According to the scheme of the invention, under the low-voltage conduction state, the Schottky diode structure is conducted and is used as a main current channel; the voltage at two ends of a collector metal layer and an emitter metal layer of the device exceeds the starting voltage of the SiC PN junction, the PN junction diode structure is conducted, the conductance regulation and control are carried out on the device, and the on-resistance of the device is further reduced. Meanwhile, through the design of the structure, the design that a bipolar power switch device such as an IGBT needs an external anti-parallel diode is simplified, the dynamic performance of the device is improved, and the cost of the device is further reduced.
Drawings
FIG. 1 schematically shows a structure of a depletion mode silicon carbide bipolar device according to an embodiment of the invention;
FIG. 2 is a schematic representation of the on current flow direction at a lower voltage of the present invention;
FIG. 3 schematically shows the on-current flow at higher voltages (VCE > 2.7V) according to the present invention;
fig. 4, 5, 6 and 7 are structural diagrams showing different states of the structure of the depletion type silicon carbide bipolar device;
figure 8 schematically illustrates a structure of a depletion mode silicon carbide bipolar device according to an embodiment of another embodiment of the present invention;
in the figure: 100-a preceding stage portion;
110-N type buffer layer, 120-N type drift layer, 121-groove structure, 122-P type doping region, 123-N + ohm contact region, 124-P + ohm contact region, 130-insulating medium layer, 140-grid metal layer and 150-emitter metal layer;
200-a later stage part;
210-Schottky diode structure, 211-N + ion implantation area, 212-Schottky metal contact area, 220-PN junction diode structure, 221-P + ion implantation area, 222-ohm contact area, 230-collector metal layer and 240-N + type substrate layer.
Detailed Description
The content of the invention will now be discussed with reference to exemplary embodiments. It is to be understood that the embodiments discussed are merely intended to enable one of ordinary skill in the art to better understand and thus implement the teachings of the present invention, and do not imply any limitations on the scope of the invention.
As used herein, the term "include" and its variants are to be read as open-ended terms meaning "including, but not limited to. The term "based on" is to be read as "based, at least in part, on". The terms "one embodiment" and "an embodiment" are to be read as "at least one embodiment".
Figure 1 schematically shows a structure of a depletion mode silicon carbide bipolar device according to one embodiment of the present invention. As shown in fig. 1, the depletion type silicon carbide bipolar device structure in this embodiment includes a front-stage portion 100 and a rear-stage portion 200, the front-stage portion 100 is located on the upper portion of the device structure, the front-stage portion 100 includes a silicon carbide JFET structure having an N-type buffer layer 110, an N-type drift layer 120, a P-type doped region 122, a P + ohmic contact region 124, an N + ohmic contact region 123, an insulating dielectric layer 130, a gate metal layer 140 and an emitter metal layer 150, specifically, the N-type buffer layer 110, the N-type drift layer 120, the P-type doped region 122, the P + ohmic contact region 124, the insulating dielectric layer 130 and the gate metal layer 140 are sequentially located from bottom to top on both sides of the N-type drift layer 120, and the top is the N + ohmic contact region 123 and the emitter metal layer 150. The silicon carbide JFET structure is introduced into the front-stage part 100, so that the silicon carbide JFET structure has the advantages of high withstand voltage and low conduction loss.
As shown in fig. 1, the rear-stage portion 200 is located at the lower part of the device structure, and the rear-stage portion 200 is, from top to bottom: an N + type substrate layer 240, an N + ion implantation region 211 and a P + ion implantation region 221, an ohmic contact region 222 and a schottky metal contact region 212, and a collector metal layer 230, wherein in the back-stage part 200, the N + type substrate layer 240, the N + ion implantation region 211, the schottky metal contact region 212, and the collector metal layer 230 form a schottky diode structure 210; the N + -type substrate layer 240, the P + -type ion implantation region 221, the ohmic contact region 222, and the collector metal layer 230 form a PN junction diode structure 220, and the schottky diode structures 210 and the PN junction diode structures 220 are alternately arranged along the length direction of the collector metal layer 230. Wherein the N-type buffer layer 110 and the N + -type substrate layer 240 are connected for connecting the front stage part 100 and the rear stage part 200 in series. According to the invention, the front-stage part 100 introduces the silicon carbide JFET structure, the characteristic of multistage series connection can be realized by using the silicon carbide JFET, the multistage combination design of the silicon carbide JFET structure, the Schottky diode structure 210 and the PN junction diode structure 220 is realized, and larger series resistance cannot be introduced. The rear-stage part 200 adopts the combined design of the Schottky diode structure 210 and the PN junction diode structure 220, and the normally-on characteristic of the silicon carbide JFET is utilized, so that the channel resistance of the device can be effectively reduced. Further, a laterally alternating arrangement design of schottky diode structures 210 and PN junction diode structures 220 is introduced at the bottom of the silicon carbide JFET structure. After the PN junction diode is turned on, minority hole carriers are injected into the N-type drift layer 120, so that a conductivity modulation effect is generated, and the on-resistance of the device can be greatly reduced. In addition, the Schottky diode is a unipolar device, and the forward turn-on voltage of the device is small, so that the Schottky diode has low conduction loss and fast reverse recovery capability. The invention utilizes the combination of the PN junction diode and the Schottky diode, has the conductance modulation effect of the PN junction diode and the low conduction loss and the quick reverse recovery capability of the Schottky diode, and can further reduce the conduction resistance of the invention.
In some embodiments of the present invention, as shown in fig. 1, the depletion-mode silicon carbide bipolar device structure includes a front-stage portion 100 and a rear-stage portion 200, the front-stage portion 100 is a silicon carbide JFET structure, and the rear-stage portion 200 is, in order from top to bottom: an N + type substrate layer 240, N + ion implantation regions 211 and 221, an ohmic contact region 222 and a schottky metal contact region 212, a collector metal layer 230; the N + type substrate layer 240, the P + ion implantation region 221, the ohmic contact region 222, and the collector metal layer 230 form a PN junction diode structure 220, the N + type substrate layer 240, the N + ion implantation region 211, the schottky metal contact region 212, and the collector metal layer 230 form a schottky diode structure 210, wherein two schottky diode structures 210 are respectively located at both sides of the PN junction diode structure 220.
In some embodiments of the present invention, as shown in fig. 8, the depletion-mode silicon carbide bipolar device structure includes a front-stage portion 100 and a rear-stage portion 200, the front-stage portion 100 is a silicon carbide JFET structure, and the rear-stage portion 200 is, in order from top to bottom: an N + type substrate layer 240, an N + ion implantation region 211 and a P + ion implantation region 221, an ohmic contact region 222 and a schottky metal contact region 212, a collector metal layer 230; in the latter part 200, the N + -type substrate layer 240, the N + -ion implantation region 211, the schottky metal contact region 212, and the collector metal layer 230 form a schottky diode structure 210; the N + -type substrate layer 240, the P + -type ion implantation region 221, the ohmic contact region 222, and the collector metal layer 230 form a PN junction diode structure 220, wherein the plurality of schottky diode structures 210 and the plurality of PN junction diode structures 220 are alternately arranged along a length direction of the collector metal layer 230.
As shown in fig. 2, in the low voltage conducting state of the present invention, the schottky diode structure 210 is turned on, and the schottky diode structure 210 serves as a main current channel. Current is conducted from the collector metal layer 230 to the emitter metal layer 150 through the schottky metal contact region 212, the N + ion implantation region 211, the N + type substrate layer 240, the N type buffer layer 110, the N-type drift layer 120, and the N + ohmic contact region 123.
As shown in fig. 3, when the voltage at the two ends of the collector metal layer 230-the emitter metal layer 150 of the device exceeds the turn-on voltage of the SiC PN junction, i.e., about 2.7V, the PN junction diode structure 220 is turned on, and the conductance of the invention is controlled, thereby further reducing the on-resistance of the invention. The current flows from the collector metal layer 230 into the N + type substrate layer 240 through the schottky metal contact region 212, the N + ion implantation region 211, the ohmic contact region 222, and the P + ion implantation region 221, and then is conducted to the emitter metal layer 150 through the N-type buffer layer 110, the N-type drift layer 120, and the N + ohmic contact region 123. Meanwhile, through the design of the structure, the design that a bipolar power switch device such as an IGBT needs an external anti-parallel diode is simplified, the dynamic performance of the device is improved, and the cost of the device is further reduced.
Specifically, in this embodiment, collector metal layer 230 is formed of Ti, ni, or Ag, which is a metal to form a collector electrode.
The schottky metal contact region 212 is formed by depositing a schottky metal material including, but not limited to, ti, pt, sb, co, or Mo.
The thickness of the N + type substrate layer (240) is 50-200 μm.
The thickness of the N-type buffer layer 110 is 0.5 to 2 μm.
The thickness of the N-type drift layer 120 is 3 to 150 μm.
The P-type doped region 122 is a P-type doped SiC layer, and is formed by ion implantation of Al ions.
The insulating dielectric layer 130 is made of SiO 2 SiN or HfO.
The gate metal layer 140 and the emitter metal layer 150 are formed by depositing metal Al to form gate conduction or emitter conduction.
Further, in order to achieve the above object, the present invention also provides a method for preparing the depletion type silicon carbide bipolar device structure, and fig. 4, fig. 5, fig. 6 and fig. 7 respectively show structural diagrams in different states of preparing the depletion type silicon carbide bipolar device structure, and in combination with fig. 4 to fig. 7, the method comprises the following steps:
s01, as shown in FIG. 4, extending the N-type buffer layer 110 on the N + type substrate layer 240, extending the N-type drift layer 120 on the N-type buffer layer 110, wherein the doping concentration of the N + type substrate layer 240 is C1, the doping concentration of the N-type buffer layer 110 is C2, and the doping concentration of the N-type drift layer 120 is C3; the N + type substrate layer 240, the N type buffer layer 110 and the N-type drift layer 120 are all doped in an N type; wherein, C1 is more than 1e19 cm -3 ，e18 cm -3 ≤C2≤1e19 cm -3 ，1e14 cm -3 ≤C3＜1e18 cm -3 (ii) a The thickness of the N-type buffer layer 110 is 0.5-2 μm, and the thickness of the N-type drift layer 120 is 3-150 μm;
s02, as shown in FIG. 5, a trench structure 121 is etched in the N-type drift layer 120, and high-energy Al ions are implanted into the sidewall and the bottom of the trench structure 121 to form a P-type doped region 122, wherein the P-type doped region 122 is formed in the P-type doped region 122The implantation energy is 100 keV to 800 keV, and the implantation dose is 1e11 cm -3 To 1e14 cm -3 ；
S03, as shown in FIG. 5, implanting N-type ions on the N-type drift layer 120 to form an N + ohmic contact region 123, wherein the N + ohmic contact region 123 is implanted by N ions, the implantation energy is 30keV to 200keV, and the implantation dose is 1e12 cm -3 To 1e15 cm -3 ；
S04, as shown in FIG. 5, implanting P-type ions into the P-type doped region 122 to form a P + ohmic contact region 124, wherein the P + ohmic contact region 124 is formed by combining vertical and inclined Al ion implantation, the implantation energy is 30keV to 200keV, and the implantation dose is 1e12 cm -3 To 1e15 cm -3 ；
S05, as shown in fig. 5, after ion implantation is performed on the N-type drift layer 120 and the P-type doped region 122, respectively, high-temperature annealing is performed on the device, where the annealing temperature is 2400 ℃ to 2000 ℃, and the annealing time is 5 minutes to 100 minutes;
s06, as shown in FIG. 5, growing an insulating dielectric layer 130 on the sidewall of the trench structure 121 by chemical vapor deposition and thermal oxidation, wherein the material of the insulating dielectric layer 130 includes but is not limited to SiO 2 SiN, hfO, etc., further, after the growth of the insulating dielectric layer 130 is completed, the excess insulating dielectric except the sidewall needs to be removed;
s07, as shown in FIG. 5, depositing metal Al on the P + ohmic contact region 124 and the N + ohmic contact region 123 to form a gate metal layer 140 and an emitter metal layer 150;
and S08, as shown in FIG. 6, thinning the side, away from the N-type buffer layer 110, of the N + -type substrate layer 240, wherein the thickness of the thinned N + -type substrate layer 240 is 50-200 μm. The on-resistance of the invention can be further reduced by the thinning process. The thinning method of the N + type substrate layer 240 includes: chemical etching, mechanical polishing, grinding and the like, and further, after the N + type substrate layer 240 is thinned, the damage of the N + type substrate layer 240 needs to be repaired, wherein the repair mode is laser annealing;
s09, as shown in FIG. 7, the side of the N + type substrate layer 240 away from the N-type buffer layer 110 is blocked by a mask, and the position of the P-type implantation region 221 is etched, and thenImplanting P-type ions into the implantation position of the P-type implantation region 221 to form a P + ion implantation region 221, and forming an N + ion implantation region 211 on the portion of the N + substrate layer 240 not implanted with P + ions, wherein the implantation energy of the P-type ions is 400 keV to 1000 keV, and the implantation dosage is 1e14 cm -3 To 5e15 cm -3 Furthermore, after ion implantation is completed, rapid laser annealing needs to be performed on the P + ion implantation region 221, so as to repair lattice damage caused by ion implantation and activate doped impurities;
s10, as shown in fig. 1, depositing a schottky metal material on a side of the N + ion implantation region 211 away from the N-type buffer layer 110 to form a schottky metal contact region 212, and making an ohmic contact on a side of the P + ion implantation region 221 away from the N-type buffer layer 110 to form an ohmic contact region 222, wherein the deposited schottky metal material includes but is not limited to Ti, pt, sb, co, mo, and the like;
s11, as shown in fig. 1, a collector metal layer 230 is formed by depositing a metal material on the schottky metal contact region 212 and the ohmic contact region 222 away from the N-type buffer layer 110, wherein the deposited metal material is Ti, ni or Ag.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A depletion mode silicon carbide bipolar device structure comprising:
an N-type buffer layer (110);
an N-type drift layer (120) which is formed on the N-type buffer layer (110) and has two symmetrical groove structures (121) on one side away from the N-type buffer layer (110);
a P-type doped region (122) formed on the sidewall and the bottom of the two trench structures (121) of the N-type drift layer (120);
a P + ohmic contact region (124) formed on the P-type doped region (122) at the bottom of the trench structure (121);
an N + ohmic contact region (123) on the N-type drift layer (120) and the P-type doped region (122) connecting the N-type drift layer (120) and the P-type doped region (122);
a gate metal layer (140) formed on the P + ohmic contact region (124);
an insulating dielectric layer (130) formed on the sidewall of the P-type doped region (122) for separating the gate metal layer (140) and the P-type doped region (122);
an emitter metal layer (150) formed on the N + ohmic contact region (123);
it is characterized by also comprising:
an N + -type substrate layer (240) formed under the N-type buffer layer (110);
an N + ion implantation region (211) formed below the N + type substrate layer (240);
p + ion implantation regions (221), the P + ion implantation regions (221) and the N + ion implantation regions (211) being formed alternately below the N + type substrate layer (240) along a length direction of the N + type substrate layer (240);
a Schottky metal contact region (212) correspondingly formed below the N + ion implantation region (211);
an ohmic contact region (222) correspondingly formed below the P + ion implantation region (221);
a collector metal layer (230) formed below the Schottky metal contact region (212) and the ohmic contact region (222).
2. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said collector metal layer (230) is formed of metal Ti, ni or Ag.
3. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said schottky metal contact region (212) is formed of a metallic material Ti, pt, sb, co or Mo.
4. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said N + type substrate layer (240) has a thickness of 50-200 μm.
5. The depletion-mode silicon carbide bipolar device structure of claim 4, wherein said N-type buffer layer (110) has a thickness of 0.5-2 μm.
6. The depletion-mode silicon carbide bipolar device structure of claim 4, wherein said N-type drift layer (120) has a thickness of 3-150 μm.
7. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said P-type doped region (122) is a P-type doped SiC layer formed by ion implantation of Al ions.
8. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said insulating dielectric layer (130) is made of SiO 2 SiN or HfO.
9. The depletion-mode silicon carbide bipolar device structure of claim 1, wherein said gate metal layer (140) and said emitter metal layer (150) are both formed of metallic Al.
10. A method of making a depletion mode silicon carbide bipolar device structure according to any of claims 1 to 9, comprising:
s01, extending the N-type buffer layer (110) on the N + type substrate layer (240) and extending the N-type drift layer (120) on the N-type buffer layer (110);
s02, etching a groove structure (121) on the N-type drift layer (120), and injecting high-energy Al ions into the side wall and the bottom of the groove structure (121) to form the P-type doped region (122);
s03, injecting N-type ions into the N-type drift layer (120) to form an N + ohmic contact region (123);
s04, injecting P-type ions into the P-type doped region (122) to form a P + ohmic contact region (124);
s05, respectively carrying out the above ion implantation on the N-type drift layer (120) and the P-type doped region (122), and then carrying out high-temperature annealing on the device, wherein the annealing temperature is 1600-2000 ℃;
s06, growing the insulating medium layer (130) on the side wall of the groove structure (121);
s07, depositing metal Al on the P + ohmic contact region (124) and the N + ohmic contact region (123) respectively to form the gate metal layer (140) and the emitter metal layer (150);
s08, thinning one side, far away from the N-type buffer layer (110), of the N + type substrate layer (240);
s09, injecting P-type ions into one side, far away from the N-type buffer layer (110), of the N + type substrate layer (240) to form the P + ion injection region (221), and forming the N + ion injection region (211) on the part, not injected with the P + ions, of the N + type substrate layer (240);
s10, depositing a Schottky metal material on one side of the N + ion injection region (211) far away from the N-type buffer layer (110) to form the Schottky metal contact region (212), and making ohmic contact on one side of the P + ion injection region (221) far away from the N-type buffer layer (110) to form the ohmic contact region (222);
s11, depositing a metal material on the side of the Schottky metal contact region (212) and the ohmic contact region (222) far away from the N-type buffer layer (110) to form the collector metal layer (230).
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