CN115799344A - Silicon carbide JFET cellular structure and manufacturing method thereof - Google Patents
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 171
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 167
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 210000003850 cellular structure Anatomy 0.000 title claims abstract description 22
- 238000002347 injection Methods 0.000 claims abstract description 63
- 239000007924 injection Substances 0.000 claims abstract description 63
- 210000004027 cell Anatomy 0.000 claims abstract description 60
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- 238000005468 ion implantation Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 18
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- 238000000034 method Methods 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 12
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- 150000002500 ions Chemical class 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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Abstract
The invention provides a silicon carbide JFET cellular structure and a manufacturing method thereof. The cell structure comprises a silicon carbide N + substrate layer, a silicon carbide N-first epitaxial layer, a P doping region, a silicon carbide N-second epitaxial layer, a P + ohmic injection region, a P + grid injection region, a grid electrode region, an insulating medium layer, an ohmic contact region, a Schottky contact region, an emitter and a collector; the P + ohmic injection regions are positioned in the silicon carbide N-second epitaxial layer and are arranged in the silicon carbide N-second epitaxial layer in a staggered mode; the ohmic contact regions and the Schottky contact regions are repeatedly distributed at intervals in the middle area of the cellular structure to form a hybrid diode layout. The invention realizes the switching function of the conductive channel by utilizing the depletion function of the PN junction, reduces the structure of a grid oxide layer, improves the reliability of the device, and simultaneously, the P + ohm injection regions are arranged in the silicon carbide N-second epitaxial layer in a staggered way, thereby increasing the current flowing area and reducing the on-resistance of the device.
Description
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a silicon carbide JFET cellular structure and a manufacturing method thereof.
Background
The silicon carbide material has more excellent characteristics than a silicon material as a wide bandgap semiconductor material, wherein the bandgap width is 3 times that of silicon, the critical breakdown electric field is 10 times that of silicon, and the thermal conductivity is 4 times that of silicon. The power device made of the silicon carbide material has higher working frequency, smaller loss and higher working temperature and power density than a silicon device, and is not suitable for being applied to high-voltage, high-power, high-temperature and radiation-resistant power electronic devices.
In recent years, silicon carbide metal oxide field effect transistors (abbreviated as SiC MOSFETs) have been introduced into the power device market. The SiC MOSFET has higher operating temperature, lower switching loss and higher switching frequency than a conventional silicon-insulated gate bipolar field effect transistor (abbreviated as Si IGBT) with the same withstand voltage capability. Although SiC MOSFETs have excellent performance, the gate oxide reliability of SiC MOSFET devices is severely affected under high-temperature and high-pressure conditions, and the properties of silicon carbide materials are not fully developed. In addition, the reverse recovery speed of the parasitic diode of the SiC MOSFET is relatively poor, and the reverse recovery loss of the body diode accounts for a large proportion of the switching loss of the SiC MOSFET device under a fast switching frequency, which severely limits the performance of the SiC MOSFET device. How to solve the reliability of the silicon carbide device under the condition of high temperature and high pressure and reduce the switching loss of the device becomes a technical problem to be solved urgently.
Junction Field Effect Transistors (JFETs) are depletion mode devices that achieve drain-source current control by applying a voltage across the PN junction to change the channel conductivity. The silicon carbide JFET device has the advantages of simple driving, no gate oxide layer, high reliability and the like, is very suitable for being used under the conditions of high temperature and high pressure, and has wide application prospect in the field of power devices.
Disclosure of Invention
In order to solve at least one technical problem in the background art, the invention provides a silicon carbide JFET cellular structure, the switching action of a conducting channel is realized by utilizing the depletion action of a PN junction, the structure of a grid oxide layer is reduced, the reliability of a device is improved, meanwhile, P + ohm injection regions are arranged in a staggered mode in a silicon carbide N-second epitaxial layer, the current flowing area is increased, and the on-resistance of the device is reduced.
According to a first aspect of the invention, the invention firstly provides a silicon carbide JFET cell structure, which comprises a silicon carbide N + substrate layer, a silicon carbide N-first epitaxial layer, a P doped region, a silicon carbide N-second epitaxial layer, a P + ohmic injection region, a P + gate injection region, a gate electrode region, an insulating dielectric layer, an ohmic contact region, a schottky contact region, an emitter and a collector; the area between the silicon carbide N-first epitaxial layer and the P + grid injection region is a conductive channel;
the silicon carbide N-first epitaxial layer is positioned on the upper surface of the silicon carbide N + substrate layer;
the silicon carbide N-second epitaxial layer is positioned on the upper surface of the silicon carbide N-first epitaxial layer, and the thickness of the silicon carbide N-second epitaxial layer is smaller than that of the silicon carbide N-first epitaxial layer;
the P doped region is positioned below the upper surface of the silicon carbide N-first epitaxial layer;
the P + ohmic injection regions are positioned in the silicon carbide N-second epitaxial layer and are distributed in the silicon carbide N-second epitaxial layer in a staggered mode;
the ohmic contact regions are positioned above the silicon carbide N-second epitaxial layer and above the P + ohmic injection region in the middle region of the cellular structure, and are distributed in a strip shape on two sides of the cellular structure;
the Schottky contact region is positioned above the silicon carbide N-second epitaxial layer and between the two gate electrode regions;
the ohmic contact regions and the Schottky contact regions are repeatedly distributed at intervals in the middle area of the cellular structure to form a hybrid diode layout.
Furthermore, the P + ohmic injection regions are positioned on two sides of the insulating medium layer, and the depth of the P + ohmic injection regions is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer;
the P + grid electrode injection region is positioned in the silicon carbide N-second epitaxial layer, and the thickness of the P + grid electrode injection region is smaller than that of the silicon carbide N-second epitaxial layer;
the gate electrode region is positioned above the silicon carbide N-second epitaxial layer, and the insulating medium layer is positioned in the gate electrode region and wraps the gate electrode material;
the emitters are distributed above the ohmic contact region, the insulating medium layer and the Schottky contact region;
the collector is located below the silicon carbide N + substrate layer.
Furthermore, the P + ohmic injection regions are positioned on two sides of the insulating medium layer, and the depth of the P + ohmic injection regions is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer;
the P + grid electrode injection region is positioned in the silicon carbide N-second epitaxial layer, and the thickness of the P + grid electrode injection region is smaller than that of the silicon carbide N-second epitaxial layer;
the gate electrode region is positioned above the silicon carbide N-second epitaxial layer, and the insulating medium layer is positioned in the gate electrode region and wraps the gate electrode material;
the emitters are distributed above the ohmic contact region, the insulating medium layer and the Schottky contact region;
the collector is located below the silicon carbide N + substrate layer.
Furthermore, the Schottky contact region is arranged above the blank region of the middle region of the unit cell.
Furthermore, the width of the ohmic contact region is the width from the cell boundary to the insulating medium layer.
Furthermore, the doped impurities of the silicon carbide N + substrate layer are N, the doped impurities of the silicon carbide N-first epitaxial layer are N, the doped impurities of the P doped region are Al, the doped impurities of the silicon carbide N-second epitaxial layer are N, the doped impurities of the P + ohmic injection region are Al, and the depth of the P + ohmic injection region is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer; and the doping impurity of the P + grid electrode injection region is Al.
Furthermore, the P doped regions are distributed on two sides of the cellular structure, extend inwards from the two sides to be shorter than or equal to the grid, and are close to the lower part of one side edge of the middle of the cellular structure.
Furthermore, the P + gate injection regions are distributed in a stripe shape on the cell structure and penetrate through the whole cell structure.
Further, the P + gate injection region is distributed between two P + ohmic injection regions in the cell.
According to a second aspect of the present invention, the present invention further provides a method for manufacturing a silicon carbide JFET cell structure, comprising the following steps:
step 8, depositing an ohmic contact metal material, etching the areas except the P + ohmic injection area on the two sides of the unit cell and the middle position of the unit cell, removing the ohmic contact metal material, annealing, and forming an ohmic contact area on the surface of the unit cell; performing Schottky metal material deposition in the region except the P + ohmic injection region in the middle of the cell, and annealing to form a Schottky contact region in the Schottky region;
and step 10, depositing electrode metal in the direction of the silicon carbide N + substrate layer far away from the silicon carbide N-first substrate layer to form a collector.
Through the embodiment of the application, the following technical effects can be realized:
(1) The depletion effect of the PN junction is utilized to realize the switching action of the conductive channel, the structure of a grid oxide layer is reduced, and the reliability of the device is greatly improved;
(2) The P + ohmic injection regions are arranged in the silicon carbide N-second epitaxial layer in a staggered mode, so that the current conduction area is increased, and the on-resistance of the device is reduced;
(3) The PN diodes and the Schottky diodes are distributed in a staggered mode in the middle area of the unit cell, and reverse recovery time is shortened; meanwhile, due to the blocking effect of a P + ohm injection region in the PN diode, an electric field borne by the device in a Schottky interface region when the device is closed is reduced, and therefore leakage current of the device is reduced;
(4) The manufacturing method of the silicon carbide JFET cellular structure is compatible with the existing wafer manufacturing process, simple in process, low in cost and suitable for large-scale production.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
FIG. 1 is a schematic diagram of a silicon carbide JFET cell according to the present invention;
FIGS. 2-3 are schematic cross-sectional views A-A' and corresponding cross-sectional views ofbase:Sub>A silicon carbide JFET cell structure according to the present invention;
FIGS. 4-5 are schematic cross-sectional views of a silicon carbide JFET cell structure according to the present invention along lines B-B' and corresponding cross-sectional views;
FIGS. 6-7 are schematic cross-sectional views of a silicon carbide JFET cell structure according to the present invention along the line C-C;
FIG. 8 is a flow chart of a method for fabricating a silicon carbide JFET cell structure according to the present invention;
fig. 9-20 are schematic structural diagrams of intermediate products of the steps of a method for fabricating a silicon carbide JFET cell structure according to the present invention.
The attached drawings are as follows: the solar cell comprises a 1-silicon carbide N + substrate layer, a 2-silicon carbide N-first epitaxial layer, a 3-P doped region, a 4-silicon carbide N-second epitaxial layer, a 5-P + ohmic injection region, a 6-P + grid injection region, a 7-grid electrode region, an 8-insulating dielectric layer, a 9-ohmic contact region, a 10-Schottky contact region, an 11-emitter and a 12-collector.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
According to an embodiment of the present invention, fig. 1 is a schematic diagram of a silicon carbide JFET cell structure in the present invention, as shown in fig. 1, the cell structure includes a silicon carbide N + substrate layer, a silicon carbide N-first epitaxial layer, a P doped region, a silicon carbide N-second epitaxial layer, a P + ohmic injection region, a P + gate injection region, a gate electrode region, an insulating dielectric layer, an ohmic contact region, a schottky contact region, an emitter, and a collector; the area between the silicon carbide N-first epitaxial layer and the P + grid injection region is a conductive channel;
the silicon carbide N-first epitaxial layer is positioned on the upper surface of the silicon carbide N + substrate layer;
the silicon carbide N-second epitaxial layer is positioned on the upper surface of the silicon carbide N-first epitaxial layer, and the thickness of the silicon carbide N-second epitaxial layer is smaller than that of the silicon carbide N-first epitaxial layer;
the P doped region is positioned below the upper surface of the silicon carbide N-first epitaxial layer;
the P + ohmic injection regions are positioned in the silicon carbide N-second epitaxial layer and are distributed in the silicon carbide N-second epitaxial layer in a staggered mode;
the ohmic contact region is positioned above the silicon carbide N-second epitaxial layer and the P + ohmic injection region in the middle region of the cellular structure, and is in strip distribution at two sides of the cellular structure;
the Schottky contact region is positioned above the silicon carbide N-second epitaxial layer and is positioned between the two gate electrode regions;
the ohmic contact regions and the Schottky contact regions are repeatedly distributed at intervals in the middle region of the cellular structure to form a hybrid diode layout.
In the embodiment, the depletion effect of the PN junction is utilized to realize the switching effect of the conductive channel, the structure of a grid oxide layer is reduced, and the reliability of the device is greatly improved; the P + ohmic injection regions are arranged in the silicon carbide N-second epitaxial layer in a staggered mode, so that the current conduction area is increased, and the on-resistance of the device is reduced;
according to one embodiment of the invention, the P + ohmic injection regions are positioned at two sides of the insulating medium layer, and the depth of the P + ohmic injection regions is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer;
the P + grid electrode injection region is positioned in the silicon carbide N-second epitaxial layer, and the thickness of the P + grid electrode injection region is smaller than that of the silicon carbide N-second epitaxial layer;
the gate electrode region is positioned above the silicon carbide N-second epitaxial layer, and the insulating medium layer is positioned in the gate electrode region and wraps the gate electrode material;
the emitting electrodes are distributed above the ohmic contact region, the insulating medium layer and the Schottky contact region;
the collector is positioned below the silicon carbide N + substrate layer.
According to one embodiment of the invention, the P + ohmic injection regions are positioned at two sides of the insulating medium layer, and the depth of the P + ohmic injection regions is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer;
the P + grid electrode injection region is positioned in the silicon carbide N-second epitaxial layer, and the thickness of the P + grid electrode injection region is smaller than that of the silicon carbide N-second epitaxial layer;
the gate electrode region is positioned above the silicon carbide N-second epitaxial layer, and the insulating medium layer is positioned in the gate electrode region and wraps the gate electrode material;
the emitting electrodes are distributed above the ohmic contact region, the insulating medium layer and the Schottky contact region;
the collector is positioned below the silicon carbide N + substrate layer.
According to one embodiment of the present invention, the schottky contact region is disposed above the empty region of the middle region of the cell.
In the embodiment, the PN diodes and the Schottky diodes are distributed in a staggered manner in the middle area of the unit cell, so that the reverse recovery time is shortened; meanwhile, due to the blocking effect of the P + ohm injection region in the PN diode, the electric field borne by the device in the Schottky interface region when the device is closed is reduced, and therefore the leakage current of the device is reduced.
According to one embodiment of the invention, the width of the ohmic contact region is the width between the cell boundary and the insulating medium layer.
According to one embodiment of the invention, the doped impurity of the silicon carbide N + substrate layer is N, the doped impurity of the silicon carbide N-first epitaxial layer is N, the doped impurity of the P doped region is Al, the doped impurity of the silicon carbide N-second epitaxial layer is N, the doped impurity of the P + ohmic injection region is A1, and the depth of the P + ohmic injection region is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer; the doping impurity of the P + grid electrode injection region is Al.
According to one embodiment of the invention, the P doped regions are distributed on two sides of the cellular structure and extend inwards from the two sides to be shorter than or equal to the grid and are close to the middle of the cellular structure and below one side edge.
According to one embodiment of the present invention, the P + gate implant regions are stripe-shaped on the cell structure, and extend throughout the entire cell structure.
According to one embodiment of the present invention, the P + gate implant region is distributed between two P + ohmic implant regions within the cell.
Fig. 2-3 are schematic cross-sectional viewsbase:Sub>A-base:Sub>A' and corresponding cross-sectional views ofbase:Sub>A silicon carbide JFET cell structure according to an embodiment of the invention; FIGS. 4-5 are schematic cross-sectional views of a silicon carbide JFET cell structure according to the present invention along lines B-B' and corresponding cross-sectional views; FIGS. 6-7 are schematic cross-sectional views of a silicon carbide JFET cell structure according to the present invention along the line C-C; fig. 8 is a flowchart of a method for manufacturing a silicon carbide JFET cell structure according to the present invention, fig. 9 to 20 are schematic structural diagrams of intermediate products of the steps of the manufacturing method according to the present invention, and the method for manufacturing the silicon carbide JFET cell structure specifically includes the following steps:
step 8, depositing an ohmic contact metal material, etching the areas except the P + ohmic injection area on the two sides of the cell and the middle position of the cell, removing the ohmic contact metal material, annealing, and forming an ohmic contact area on the surface of the cell, as shown in FIG. 17; performing schottky metal material deposition in the middle of the cell except for the P + ohmic injection region, and annealing to form a schottky contact region in the schottky region, as shown in fig. 18;
and step 10, depositing electrode metal in the direction of the silicon carbide N + substrate layer far away from the silicon carbide N-first substrate layer to form a collector, as shown in fig. 20.
According to the invention, the structure of the silicon carbide JFET cellular is optimized, and the P + ohmic injection region and the silicon carbide N-second epitaxial layer are arranged in a staggered mode in space, so that the area of on-state current is increased, and the specific on-state resistance of the device is reduced. In addition, PN diodes and Schottky diodes are distributed in a staggered mode in the middle area of the unit cell, reverse recovery time is shortened, and reverse leakage current when the device is closed is reduced. The invention also provides a process method for preparing the cellular structure device, which is compatible with the existing wafer manufacturing process, has simple process and low cost and is suitable for large-scale production.
Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and devices may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative.
It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
It should be understood that, the serial numbers of the steps in the summary and the embodiments of the present invention do not absolutely imply the sequence of execution, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Claims (9)
1. A silicon carbide JFET cellular structure is characterized by comprising a silicon carbide N + substrate layer, a silicon carbide N-first epitaxial layer, a P doping region, a silicon carbide N-second epitaxial layer, a P + ohmic injection region, a P + grid injection region, a grid electrode region, an insulating medium layer, an ohmic contact region, a Schottky contact region, an emitter and a collector; the area between the silicon carbide N-first epitaxial layer and the P + grid injection region is a conductive channel;
the silicon carbide N-first epitaxial layer is positioned on the upper surface of the silicon carbide N + substrate layer;
the silicon carbide N-second epitaxial layer is positioned on the upper surface of the silicon carbide N-first epitaxial layer, and the thickness of the silicon carbide N-second epitaxial layer is smaller than that of the silicon carbide N-first epitaxial layer;
the P doped region is positioned below the upper surface of the silicon carbide N-first epitaxial layer;
the P + ohmic injection regions are positioned in the silicon carbide N-second epitaxial layer and are distributed in the silicon carbide N-second epitaxial layer in a staggered mode;
the ohmic contact regions are positioned above the silicon carbide N-second epitaxial layer and above the P + ohmic injection region in the middle region of the cellular structure, and are distributed in a strip shape on two sides of the cellular structure;
the Schottky contact region is positioned above the silicon carbide N-second epitaxial layer and between the two gate electrode regions;
the ohmic contact region and the Schottky contact region are repeatedly distributed at intervals in the middle area of the cellular structure to form a hybrid diode layout.
2. The silicon carbide JFET cell structure of claim 1,
the P + ohmic injection regions are positioned on two sides of the insulating medium layer, and the depth of the P + ohmic injection regions is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer;
the P + grid electrode injection region is positioned in the silicon carbide N-second epitaxial layer, and the thickness of the P + grid electrode injection region is smaller than that of the silicon carbide N-second epitaxial layer;
the gate electrode region is positioned above the silicon carbide N-second epitaxial layer, and the insulating medium layer is positioned in the gate electrode region and wraps the gate electrode material;
the emitters are distributed above the ohmic contact region, the insulating medium layer and the Schottky contact region;
the collector is located below the silicon carbide N + substrate layer.
3. The silicon carbide JFET cell structure of claim 1, wherein the schottky contact region is disposed above the void region in the middle region of the cell.
4. The silicon carbide JFET cell structure of claim 1, wherein the ohmic contact region has a width from a cell boundary to an insulating dielectric layer.
5. The silicon carbide JFET cell structure of claim 1, wherein the doped impurity of the silicon carbide N + substrate layer is N, the doped impurity of the silicon carbide N-first epitaxial layer is N, the doped impurity of the P doped region is Al, the doped impurity of the silicon carbide N-second epitaxial layer is N, the doped impurity of the P + ohmic implanted region is Al, and the depth of the P + ohmic implanted region is greater than or equal to the thickness of the silicon carbide N-second epitaxial layer; and the doping impurity of the P + grid electrode injection region is Al.
6. The silicon carbide JFET cell structure of claim 1, wherein the P doped regions are distributed on two sides of the cell structure and extend inwards from the two sides to be shorter than or equal to a gate electrode and are arranged below one side edge of the middle of the cell.
7. The silicon carbide JFET cell structure of claim 2, wherein the P + gate implant regions are stripe-shaped across the cell structure and extend across the entire cell structure.
8. The silicon carbide JFET cell structure of claim 2, wherein the P + gate implant regions are distributed within the cell between two of the P + ohmic implant regions.
9. A method of forming a silicon carbide JFET cell structure according to any one of claims 1 to 8, the method comprising the steps of:
step 1, obtaining a silicon carbide N + substrate layer;
step 2, epitaxially growing a silicon carbide N-first epitaxial layer on the silicon carbide N + substrate layer;
step 3, manufacturing an ion implantation barrier layer on the surface of the silicon carbide N-first epitaxial layer for Al ion implantation, and performing ion activation at a high temperature after implantation to form a P doped region;
step 4, epitaxially growing a silicon carbide N-second epitaxial layer on the upper surface of the silicon carbide N-first epitaxial layer;
step 5, manufacturing an ion implantation barrier layer on the surface of the silicon carbide N-second epitaxial layer, and performing Al ion implantation in a specified area to form a high-concentration P + ohmic implantation area;
step 6, on the basis of the step 5, manufacturing an ion implantation barrier layer again, performing Al ion implantation in a designated area to form a high-concentration P + grid ion implantation area, performing ion activation under a high-temperature condition after implantation, and forming a P + ohmic implantation area and a P + grid ion implantation area in the cell;
step 7, depositing polycrystalline silicon on the surface of the silicon carbide N-second epitaxial layer, etching to form a gate electrode region, and manufacturing a gate electrode; depositing an insulating medium layer on the surface of the silicon carbide N-second epitaxial layer and the surface of the grid electrode, and etching to form an insulating medium layer;
step 8, depositing an ohmic contact metal material, etching the areas except the P + ohmic injection area on the two sides of the cell and the middle position of the cell, removing the ohmic contact metal material, annealing, and forming an ohmic contact area on the surface of the cell; performing Schottky metal material deposition in the region except the P + ohmic injection region in the middle of the cell, annealing, and forming a Schottky contact region in the Schottky region;
step 9, depositing electrode metal to form an emitter;
and step 10, depositing electrode metal in the direction of the silicon carbide N + substrate layer far away from the silicon carbide N-first substrate layer to form a collector.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116110796A (en) * | 2023-04-17 | 2023-05-12 | 深圳平创半导体有限公司 | SBD integrated silicon carbide SGT-MOSFET and preparation method thereof |
| CN117497580A (en) * | 2023-12-29 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Heterojunction silicon carbide IGBT device, preparation method thereof and chip |
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| CN116110796B (en) * | 2023-04-17 | 2023-06-13 | 深圳平创半导体有限公司 | SBD integrated silicon carbide SGT-MOSFET and preparation method thereof |
| CN117497580A (en) * | 2023-12-29 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Heterojunction silicon carbide IGBT device, preparation method thereof and chip |
| CN117497580B (en) * | 2023-12-29 | 2024-04-19 | 深圳天狼芯半导体有限公司 | Heterojunction silicon carbide IGBT device, preparation method thereof and chip |
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