CN117219672B - Quasi-vertical gallium nitride accumulation type power device - Google Patents
Quasi-vertical gallium nitride accumulation type power device Download PDFInfo
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 114
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 113
- 238000009825 accumulation Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 230000005684 electric field Effects 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 19
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 15
- 230000000903 blocking effect Effects 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 238000009413 insulation Methods 0.000 description 5
- 230000003139 buffering effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000011031 large-scale manufacturing process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a quasi-vertical gallium nitride accumulation type power device, which comprises a silicon substrate, a buffer layer, a second heavily doped gallium nitride conducting layer, a lightly doped gallium nitride conducting layer, a first heavily doped gallium nitride conducting layer and a source electrode which are sequentially arranged from bottom to top, wherein the upper end of the lightly doped gallium nitride conducting layer is provided with a transverse groove, a gate electrode wrapped with an oxide layer is arranged in the transverse groove, and the first heavily doped gallium nitride conducting layer is arranged between the gate electrodes at intervals; vertical grooves are formed in two ends of the lightly doped gallium nitride conductive layer, drain electrodes are fixed in the vertical grooves, ohmic contact is formed between the lower ends of the drain electrodes and the second heavily doped gallium nitride conductive layer, and the upper ends of the drain electrodes and the source electrodes are located on the same horizontal plane; semi-insulating polysilicon layers are respectively arranged between the two ends of the source electrode and the upper end of the drain electrode, and insulating medium layers are respectively arranged above and below the semi-insulating polysilicon layers. The invention achieves the purposes of reducing the process steps, reducing the process difficulty and saving the production cost.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a quasi-vertical gallium nitride accumulation type power device.
Background
Gallium nitride (GaN), which is a third generation semiconductor, has a large forbidden band width (3.45 eV), a high electron saturation velocity, and good high temperature resistance, and is widely used in radio frequency and power semiconductors. Gallium nitride-based power devices achieve low on-loss and high current density, as well as excellent withstand voltage capability and frequency characteristics. The gallium nitride-based power device is mainly divided into a vertical structure and a transverse structure, compared with the transverse device, the power device with the vertical structure has the advantages that current flows in a body, a larger current path is provided, the current density is increased, and the current collapse effect is more effectively restrained. The power device with the vertical structure has obviously better withstand voltage than a transverse device on the premise of not changing the size of a wafer.
In recent years, gallium nitride power devices have been developed rapidly, and new technologies based on vertical structure power devices are increasing, and the vertical structure power devices are divided into quasi-vertical structures and complete vertical structures. The power device with the completely vertical structure needs a GaN monocrystal substrate, and then the metal drain electrode is prepared on the back of the substrate, which not only provides great challenges for the preparation process of the substrate material, but also greatly increases the cost (more than 50 times of the silicon substrate material). By preparing the buffer layer on the mature silicon substrate, the quasi-vertical structure formed by regrowing GaN epitaxy is certainly a better compromise between performance and cost, so that the quasi-vertical power device is also widely used.
Patent document publication No. CN115621321a discloses a structure of a quasi-vertical power device by including an upper arm structure and a lower arm structure which are bilaterally symmetrical; the left-right symmetrical tangential plane is a sagittal plane, and the upper arm structure and the lower arm structure comprise a first epitaxial layer, a second epitaxial layer, a channel layer, an active layer, a grid structure, an isolation column, a first metal column, a first insulation column, a second metal column and a second insulation column; the side surface of the isolation column is overlapped with the sagittal plane and penetrates from the upper surface of the active layer to the lower surface of the first epitaxial layer; the isolation column, the first metal column, the first insulation column, the second metal column and the second insulation column are sequentially arranged; the first metal column, the first insulating column, the second metal column and the second insulating column penetrate from the upper surface of the active layer to the second epitaxial layer; the depth of the first metal pillar is greater than the depth of the second metal pillar. The quasi-vertical power device conducts electricity by utilizing inversion of the channel layer in practical application, and enables the channel layer to be inverted by applying gate voltage to form a conducting channel, so that carrier circulation between source and drain is realized, and the quasi-vertical power device belongs to a groove type GaN MOSFET. However, the structure needs to realize high-concentration P-type GaN doping, and the P-type GaN doped by Mg ions has the technical problems of high ionization energy, low activation rate, strict annealing temperature, poor doping capacity of a selective region, low current density and high specific on-resistance, high process difficulty and high production and manufacturing cost.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provide a quasi-vertical gallium nitride accumulation type power device, and the invention realizes the turn-off and turn-on of the device by utilizing the work function difference between a gate material and one side of a semiconductor and the applied voltage of the gate, compared with the prior art, the invention does not conduct electricity through inversion of a channel layer or adopt high-concentration P-type GaN doping, thereby achieving the purposes of reducing process steps, lowering process difficulty and saving production cost.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
A quasi-vertical gallium nitride accumulation type power device, characterized in that: the semiconductor device comprises a silicon substrate, a buffer layer, a second heavily doped gallium nitride conducting layer, a lightly doped gallium nitride conducting layer, a first heavily doped gallium nitride conducting layer and a source electrode which are sequentially arranged from bottom to top, wherein a plurality of transverse grooves are formed at intervals in the width direction at the upper end of the lightly doped gallium nitride conducting layer, gate electrodes wrapped with oxide layers are arranged in the transverse grooves, and the first heavily doped gallium nitride conducting layer is arranged between the gate electrodes at intervals and forms ohmic contact with the source electrode; vertical grooves penetrating through the two ends of the lightly doped gallium nitride conductive layer are respectively formed, drain electrodes are fixed in the vertical grooves, ohmic contact is formed between the lower ends of the drain electrodes and the second heavily doped gallium nitride conductive layer, and the upper ends of the drain electrodes and the source electrodes are located on the same horizontal plane; semi-insulating polysilicon layers are respectively arranged between the two ends of the source electrode and the upper end of the drain electrode, and an upper insulating dielectric layer and a lower insulating dielectric layer are respectively arranged above and below the semi-insulating polysilicon layers.
And an electric field shielding layer is arranged at the bottom of the transverse groove.
The electric field shielding layer is made of a heavily doped P-type material semiconductor or Al 2O3.
The buffer layer is provided with a drain metal layer, and the lower end of the drain electrode penetrates through the second heavily doped gallium nitride conducting layer and then is connected with the drain metal layer.
The drain metal layer is in a strip pattern structure, a field-shaped pattern structure, an interdigital pattern structure or a honeycomb pattern structure which are physically vapor deposited on the buffer layer.
The conductivity types of the first heavily doped gallium nitride conductive layer and the second heavily doped gallium nitride conductive layer are N-type.
The upper insulating medium layer is one or the combination of any several of Al 2O3、SiN、SiO2, and the lower insulating medium layer is one or the combination of any several of Al 2O3、SiN、SiO2.
The invention has the advantages that:
1. The invention forms a quasi-vertical gallium nitride accumulation type power device by a silicon substrate, a buffer layer, a second heavily doped gallium nitride conducting layer, a lightly doped gallium nitride conducting layer, a first heavily doped gallium nitride conducting layer, a source electrode, a gate electrode, a drain electrode, a semi-insulating polycrystalline silicon layer, an upper insulating dielectric layer and a lower insulating dielectric layer. Wherein,
The invention adopts the silicon substrate to be compatible with the existing preparation process of the silicon material, and is beneficial to large-scale production.
According to the invention, one side of the lightly doped gallium nitride conducting layer is depleted through the work function difference between the gate electrode wrapped by the oxide layer and the lightly doped gallium nitride conducting layer arranged in the transverse groove, and whether the lightly doped gallium nitride conducting layer is depleted or not between the two gate regions can be controlled by combining the potential difference between the gate electrode and the source electrode so as to control the turn-off and turn-on of an accumulation type channel of the power device, and the threshold voltage of the power device can be controlled by adjusting the width and the depth of the transverse groove, so that depletion type and enhancement type gallium nitride power devices are realized.
The invention can optimize the surface electric field through the semi-insulating polycrystalline silicon layer (SIPOS), so that the electric field becomes more uniform, and has the advantages of improving the stability of the power device, shortening the length of the withstand voltage region of the surface electric field, reducing the area of a chip, improving the reliability and the like. The upper insulating dielectric layer and the lower insulating dielectric layer can also play a role in insulating protection and buffering of the semi-insulating polycrystalline silicon layer.
In addition, a state in which accumulation of majority carriers occurs in a local region in a semiconductor with respect to a depletion state in which carriers are absent in the semiconductor is referred to as an accumulation type. Compared with the common inversion layer power device with the P-type doping channel and inversion electron channel, the invention has the advantages that the N-type doping channel and the accumulation type power device with accumulation electron channel have lower channel resistance.
In summary, the accumulation type power device based on the structure can enable the current from the source electrode to the second heavily doped gallium nitride conducting layer to longitudinally flow, so that the current density is effectively improved, the specific on-resistance of the power device is reduced, and the accumulation type power device has excellent blocking characteristics. In addition, the invention can realize the turn-off and turn-on of the device by utilizing the work function difference between the gate material and one side of the semiconductor and the gate applied voltage, compared with the prior art, the invention does not conduct electricity through inversion of the channel layer, does not adopt high-concentration P-type GaN doping, and achieves the purposes of reducing process steps, lowering process difficulty and saving production cost.
2. According to the invention, the electric field shielding layer is arranged at the bottom of the transverse groove, and the high electric field caused by the curvature effect of the bottom of the gate electrode can be relieved through the electric field shielding layer, so that the breakdown voltage of the power device is increased.
3. The invention limits that the electric field shielding layer is made of heavily doped P-type semiconductor material or Al 2O3, and has the advantages of optimizing the electric field peak value at the bottom of the grid electrode and further improving the breakdown voltage of the device.
4. According to the invention, the ohmic contact area between the second heavily doped gallium nitride conducting layer and the drain electrode can be enlarged through the drain metal layer, so that the current capacity is improved, the thickness of the second heavily doped gallium nitride conducting layer is reduced, and the production cost of the power device can be reduced.
5. According to the invention, the strip-shaped pattern structure, the field-shaped pattern structure, the interdigital pattern structure or the honeycomb pattern structure is arranged on the buffer layer, so that the contact area of the drain electrode and the second heavily doped gallium nitride conductive layer can be increased without affecting lattice matching, and the ohmic contact resistance and the resistance of the second heavily doped gallium nitride conductive layer can be reduced, thereby reducing the specific on-resistance of the power device.
6. In the invention, the conductivity types of the first heavily doped gallium nitride conductive layer and the second heavily doped gallium nitride conductive layer are both N types, which is beneficial to further reducing the manufacturing difficulty of the process.
7. The upper insulating medium layer and the lower insulating medium layer can be one or the combination of any two of Al 2O3、SiN、SiO2, and the invention has the advantages of easily available materials and convenient manufacture.
Drawings
Fig. 1 is a schematic plan view of embodiment 1;
Fig. 2 is a schematic plan view of embodiment 2;
fig. 3 is a schematic perspective view of embodiment 2;
fig. 4 is a schematic plan view of embodiment 3;
fig. 5 is a schematic plan view of embodiment 4;
Fig. 6 is a schematic perspective view of embodiment 4;
Fig. 7 is a schematic structural diagram of the drain metal layer in the stripe pattern structure in embodiment 5;
Fig. 8 is a schematic structural diagram of the drain metal layer in the structure of the pattern of the letter-pad in embodiment 5;
Fig. 9 is a schematic structural diagram of the drain metal layer in the structure of the interdigital pattern in embodiment 5;
fig. 10 is a schematic structural diagram of the drain metal layer in the honeycomb pattern structure in embodiment 5;
FIG. 11 is a simulation test chart of example 1;
fig. 12 is a simulation test chart of example 2.
The drawing is marked as follows: 1-1 parts of source electrode, 1-2 parts of upper insulating dielectric layer, 1-3 parts of semi-insulating polysilicon layer, 1-4 parts of lower insulating dielectric layer, 1-5 parts of first heavily doped gallium nitride conducting layer, 1-6 parts of oxide layer, 1-7 parts of gate electrode, 1-8 parts of lightly doped gallium nitride conducting layer, 1-9 parts of drain electrode, 1-10 parts of second heavily doped gallium nitride conducting layer, 1-11 parts of buffer layer, 1-12 parts of silicon substrate, 1-13 parts of electric field shielding layer, 1-14 parts of drain metal layer.
Detailed Description
Example 1
The embodiment provides a quasi-vertical gallium nitride accumulation-mode power device, as shown in fig. 1, which comprises a silicon substrate 1-12, a buffer layer 1-11, a second heavily doped gallium nitride conductive layer 1-10, a lightly doped gallium nitride conductive layer 1-8, a first heavily doped gallium nitride conductive layer 1-5 and a source electrode 1-1, which are sequentially arranged from bottom to top. The first heavily doped gallium nitride conductive layer 1-5 and the second heavily doped gallium nitride conductive layer 1-10 are both N-type in conductivity type, and a plurality of transverse grooves are formed at the upper end of the lightly doped gallium nitride conductive layer 1-8 at intervals along the width direction, and the number of the transverse grooves is determined according to practical requirements, for example, the number of the transverse grooves can be 5-10. The gate electrodes 1-7 wrapped with the oxide layers 1-6 are fixedly arranged in each transverse groove, and the first heavily doped gallium nitride conductive layers 1-5 are arranged between the gate electrodes 1-7 at intervals and form ohmic contact with the source electrodes 1-1. Two symmetrical vertical grooves are respectively formed in two ends of the lightly doped gallium nitride conductive layer 1-8, the two vertical grooves penetrate through the upper surface and the lower surface of the lightly doped gallium nitride conductive layer 1-8, a drain electrode 1-9 is fixed in the vertical grooves, ohmic contact is formed between the lower end of the drain electrode 1-9 and the second heavily doped gallium nitride conductive layer 1-10, and the upper end of the drain electrode and the source electrode 1-1 are located on the same horizontal plane.
In order to optimize the surface electric field and make the electric field become more uniform, the embodiment also has semi-insulating polysilicon layers 1-3 between the two ends of the source electrode 1-1 and the upper ends of the drain electrodes 1-9, i.e. in the direction shown in fig. 1, a semi-insulating polysilicon layer 1-3 is arranged between the left side of the source electrode 1-1 and the drain electrode 1-9 at the left end of the lightly doped gallium nitride conductive layer 1-8, and a semi-insulating polysilicon layer 1-3 is also arranged between the right side of the source electrode 1-1 and the drain electrode 1-9 at the right end of the lightly doped gallium nitride conductive layer 1-8, so as to improve the stability of the power device, and make the power device have the advantages of shortening the length of the surface electric field withstand voltage region, reducing the chip area and improving the reliability.
In order to perform insulation protection and buffering functions on the semi-insulating polycrystalline silicon layer 1-3, the embodiment is further provided with an upper insulating medium layer 1-2 and a lower insulating medium layer 1-4 above and below the semi-insulating polycrystalline silicon layer 1-3 respectively. Specifically, a layer of insulating medium is covered above the semi-insulating polysilicon layer 1-3, and a layer of insulating medium is arranged below the semi-insulating polysilicon layer 1-3 (i.e. between the semi-insulating polysilicon layer 1-3 and the lightly doped gallium nitride conductive layer 1-8).
To facilitate the manufacture of the insulating dielectric layers, the upper insulating dielectric layer 1-2 in this embodiment may be one or a combination of any of several kinds of Al 2O3、SiN、SiO2, and the lower insulating dielectric layer 1-4 may be one or a combination of any of several kinds of Al 2O3、SiN、SiO2.
The working principle of this embodiment is as follows:
In the quasi-vertical gallium nitride accumulation-type power device of the embodiment, the current from the source electrode 1-1 (S region) to the drain region of the second heavily doped gallium nitride conductive layer 1-10 (n+gan region) flows longitudinally, so that the current density is effectively improved, the specific on-resistance of the power device is reduced, and the power device has excellent blocking characteristics. The preparation method adopts the Si-based substrate, can be compatible with the existing preparation process of Si materials, and is suitable for large-scale production. The structure forms a depletion region on one side of the semiconductor through the work function difference between the trench gate and the lightly doped semiconductor GaN region, and combines the potential difference between the gate and the source electrode, thereby controlling whether the semiconductor GaN region between the two trench gates is depleted or not so as to control the turn-off and turn-on of a device channel, and the threshold voltage of the device can be controlled by adjusting the width and the depth of the trench gate, so that the enhancement type and depletion type GaN device can be realized. When the potential difference between the gate electrode 1-7 and the source electrode 1-1 is larger than the threshold voltage of the device, the channel of the power device is opened, electrons flow downwards from the first heavily doped gallium nitride conducting layer 1-5 below the source electrode, flow to the second heavily doped gallium nitride conducting layer 1-10 through the drift region, namely the lightly doped gallium nitride conducting layer 1-8, are collected at the bottoms of the drain electrodes 1-9 in the grooves at the two ends, and flow back to the surface of the power device. When the potential difference between the gate electrode 1-7 and the source electrode 1-1 is smaller than the threshold voltage of the device, the channel of the power device is turned off, so that the power device is in a blocking state, under the blocking voltage of the drain electrode 1-9, the semi-insulating polysilicon layers 1-3 on two sides are connected with the source electrode 1-1 and the drain electrode 1-9, a resistance field plate is realized, an even transversely distributed electric field is introduced, and the upper insulating dielectric layer 1-2 and the lower insulating dielectric layer 1-4 above and below the semi-insulating polysilicon layer 1-3 can play an insulating protection and buffering role on the semi-insulating polysilicon layer 1-3.
In addition, as shown in fig. 11, the applicant also carries out simulation test on the embodiment, and tests prove that the specific on-resistance of the power device in the embodiment is 0.77mΩ ∙ cm 2, the BV (withstand voltage) is 1.2kV, and the process difficulty is small and the production cost is low.
Example 2
The embodiment provides a quasi-vertical gallium nitride accumulation-mode power device based on embodiment 1, which comprises a silicon substrate 1-12, a buffer layer 1-11, a second heavily doped gallium nitride conductive layer 1-10, a lightly doped gallium nitride conductive layer 1-8, a first heavily doped gallium nitride conductive layer 1-5 and a source electrode 1-1, which are sequentially arranged from bottom to top as shown in fig. 2 and 3. The upper end of the lightly doped gallium nitride conducting layer 1-8 is provided with a plurality of transverse grooves at intervals along the width direction, a grid electrode 1-7 wrapped with an oxide layer 1-6 and an electric field shielding layer 1-13 are fixedly arranged in each transverse groove, and the electric field shielding layer 1-13 is positioned at the bottom of the transverse groove and below the oxide layer 1-6 of the grid electrode 1-7. The first heavily doped gallium nitride conductive layer 1-5 is disposed between the gate electrodes 1-7 at intervals and forms ohmic contact with the source electrodes 1-1. Two symmetrical vertical grooves are respectively formed in two ends of the lightly doped gallium nitride conductive layer 1-8, the two vertical grooves penetrate through the upper surface and the lower surface of the lightly doped gallium nitride conductive layer 1-8, a drain electrode 1-9 is fixed in the vertical grooves, ohmic contact is formed between the lower end of the drain electrode 1-9 and the second heavily doped gallium nitride conductive layer 1-10, and the upper end of the drain electrode and the source electrode 1-1 are located on the same horizontal plane. Semi-insulating polysilicon layers 1-3 are respectively arranged between two ends of the source electrode 1-1 and the upper end of the drain electrode 1-9, and an upper insulating dielectric layer 1-2 and a lower insulating dielectric layer 1-4 are respectively arranged above and below the semi-insulating polysilicon layers 1-3.
The electric field shielding layer 1-13 in the embodiment is made of a heavily doped P-type material semiconductor or Al 2O3, and the high electric field caused by the bottom curvature effect of the gate electrode 1-7 can be relieved through the electric field shielding layer 1-13, so that the breakdown voltage of the power device is increased, the breakdown voltage of the power device is further improved, and the reliability of the oxide layer 1-6 of the gate electrode 1-7 of the power device is improved.
In addition, as shown in fig. 11, the applicant also carries out simulation test on the embodiment, and tests prove that the specific on-resistance of the power device in the embodiment is 0.81mΩ ∙ cm 2, the BV (withstand voltage) is 1.4kV, and the process difficulty is small and the production cost is low.
Example 3
The embodiment provides a quasi-vertical gallium nitride accumulation-mode power device based on embodiment 1, as shown in fig. 4, the embodiment is provided with a drain metal layer 1-14 on a buffer layer 1-11, the drain metal layer 1-14 forms ohmic contact with a second heavily doped gallium nitride conductive layer 1-10 above, and the lower ends of drain electrodes 1-9 at two ends of the power device penetrate through the second heavily doped gallium nitride conductive layer 1-10 and then are connected with the drain metal layer 1-14. The drain metal layers 1-14 in this embodiment are diversified planar pattern layers, and can be correspondingly set according to specific requirements during practical application.
The working principle of this embodiment is as follows:
In the quasi-vertical gallium nitride accumulation-type power device of the embodiment, the current from the source electrode 1-1 (S region) to the drain region of the second heavily doped gallium nitride conductive layer 1-10 (n+gan region) flows longitudinally, so that the current density is effectively improved, the specific on-resistance of the power device is reduced, and the power device has excellent blocking characteristics. The preparation method adopts the Si-based substrate, can be compatible with the existing preparation process of Si materials, and is suitable for large-scale production. The structure forms a depletion region on one side of the semiconductor through the work function difference between the trench gate and the lightly doped semiconductor GaN region, and combines the potential difference between the gate and the source electrode, thereby controlling whether the semiconductor GaN region between the two trench gates is depleted or not so as to control the turn-off and turn-on of a device channel, and the threshold voltage of the device can be controlled by adjusting the width and the depth of the trench gate, so that the enhancement type and depletion type GaN device can be realized.
When the potential difference between the gate electrode 1-7 and the source electrode 1-1 is larger than the threshold voltage of the device, the channel of the power device is opened, electrons downwards flow from the first heavily doped gallium nitride conducting layer 1-5 below the source electrode, flow to the second heavily doped gallium nitride conducting layer 1-10 through the drift region, namely the lightly doped gallium nitride conducting layer 1-8, are further directly collected by the planar drain metal layer 1-14 below the second heavily doped gallium nitride conducting layer 1-10, and flow back to the surface of the power device through the drain electrode 1-9 in the grooves at the two ends. When the potential difference between the gate electrode 1-7 and the source electrode 1-1 is smaller than the threshold voltage of the device, the channel of the power device is turned off, so that the power device is in a blocking state, under the blocking voltage of the drain electrode 1-9, the semi-insulating polysilicon layers 1-3 on two sides are connected with the source electrode 1-1 and the drain electrode 1-9, a resistance field plate is realized, an even transversely distributed electric field is introduced, and the upper insulating dielectric layer 1-2 and the lower insulating dielectric layer 1-4 above and below the semi-insulating polysilicon layer 1-3 can play an insulating protection and buffering role on the semi-insulating polysilicon layer 1-3.
In addition, the applicant also carries out simulation test on the embodiment, and tests prove that the specific on-resistance of the power device is 0.57mΩ ∙ cm 2, the BV (withstand voltage) is 1.2kV, the process difficulty is small, and the production cost is low.
Example 4
The embodiment provides a quasi-vertical gallium nitride accumulation-mode power device based on embodiment 2, as shown in fig. 5 and 6, the embodiment is provided with a drain metal layer 1-14 on a buffer layer 1-11, the drain metal layer 1-14 forms ohmic contact with a second heavily doped gallium nitride conductive layer 1-10 above, and the lower ends of drain electrodes 1-9 at two ends of the power device penetrate through the second heavily doped gallium nitride conductive layer 1-10 and then are connected with the drain metal layer 1-14. The drain metal layers 1-14 in this embodiment are diversified planar pattern layers, and can be correspondingly set according to specific requirements during practical application.
According to the embodiment, the high electric field caused by the bottom curvature effect of the gate electrode 1-7 can be relieved through the electric field shielding layer 1-13, so that the breakdown voltage of the power device is increased, the breakdown voltage of the power device is further improved, and the reliability of the oxide layer 1-6 of the gate electrode 1-7 of the power device is improved.
In addition, the applicant also carries out simulation test on the embodiment, and tests prove that the specific on-resistance of the power device is 0.60mΩ ∙ cm 2, the BV (withstand voltage) is 1.4kV, the process difficulty is small, and the production cost is low.
Example 5
The present embodiment further defines the drain metal layer 1-14 on the basis of embodiment 3 or embodiment 4, and as shown in fig. 7-10, the drain metal layer 1-14 may be a stripe pattern structure, a field pattern structure, an interdigital pattern structure, or a honeycomb pattern structure deposited on the buffer layer 1-11 by physical vapor deposition.
It should be noted that, the drain metal layers 1 to 14 are planar structures, the pattern shapes thereof are multiple, and the stripe pattern structure, the field-shaped pattern structure, the interdigital pattern structure or the honeycomb pattern structure are preferable, but may be any other pattern, provided that a sufficient ohmic contact area is ensured, and the manufacturing process is compatible.
In addition, the applicant also carries out simulation test on the embodiment, and tests prove that the specific on-resistance of the power device with the different drain metal layer 1-14 structures in the embodiment is 0.60mΩ ∙ cm 2, the BV (withstand voltage) is 1.4kV, the process difficulty is small, and the production cost is low.
While the invention has been described with reference to certain embodiments, it is understood that any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (6)
1. A quasi-vertical gallium nitride accumulation type power device, characterized in that: the semiconductor device comprises a silicon substrate (1-12), a buffer layer (1-11), a second heavily doped gallium nitride conducting layer (1-10), a lightly doped gallium nitride conducting layer (1-8), a first heavily doped gallium nitride conducting layer (1-5) and a source electrode (1-1) which are sequentially arranged from bottom to top, wherein a plurality of transverse grooves are formed in the upper end of the lightly doped gallium nitride conducting layer (1-8) at intervals along the width direction, a gate electrode (1-7) wrapped with an oxide layer (1-6) is arranged in each transverse groove, and the first heavily doped gallium nitride conducting layer (1-5) is arranged between the gate electrodes (1-7) at intervals and forms ohmic contact with the source electrode (1-1); vertical grooves penetrating through the two ends of the lightly doped gallium nitride conductive layer (1-8) are respectively formed, drain electrodes (1-9) are fixed in the vertical grooves, ohmic contact is formed between the lower ends of the drain electrodes (1-9) and the second heavily doped gallium nitride conductive layer (1-10), and the upper ends of the drain electrodes and the source electrodes (1-1) are located on the same horizontal plane; semi-insulating polycrystalline silicon layers (1-3) are respectively arranged between the two ends of the source electrode (1-1) and the upper end of the drain electrode (1-9), and an upper insulating medium layer (1-2) and a lower insulating medium layer (1-4) are respectively arranged above and below the semi-insulating polycrystalline silicon layers (1-3);
The buffer layer (1-11) is provided with a drain metal layer (1-14), and the lower end of the drain electrode (1-9) penetrates through the second heavily doped gallium nitride conducting layer (1-10) and then is connected with the drain metal layer (1-14).
2. The quasi-vertical gallium nitride accumulation mode power device of claim 1, wherein: the bottom of the transverse groove is provided with an electric field shielding layer (1-13).
3. The quasi-vertical gallium nitride accumulation mode power device of claim 2, wherein: the electric field shielding layers (1-13) are made of heavily doped P-type material semiconductors or Al 2O3.
4. The quasi-vertical gallium nitride accumulation mode power device of claim 1, wherein: the drain metal layer (1-14) is in a strip pattern structure, a field-shaped pattern structure, an interdigital pattern structure or a honeycomb pattern structure which are physically vapor deposited on the buffer layer (1-11).
5. The quasi-vertical gallium nitride accumulation mode power device of claim 1, wherein: the conductivity types of the first heavily doped gallium nitride conductive layer (1-5) and the second heavily doped gallium nitride conductive layer (1-10) are N types.
6. The quasi-vertical gallium nitride accumulation mode power device of claim 1, wherein: the upper insulating medium layer (1-2) is one or the combination of any several of Al 2O3、SiN、SiO2, and the lower insulating medium layer (1-4) is one or the combination of any several of Al 2O3、SiN、SiO2.
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