CN112838131A - Schottky diode based on silicon carbide planar MOS structure - Google Patents
Schottky diode based on silicon carbide planar MOS structure Download PDFInfo
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- CN112838131A CN112838131A CN202110025615.XA CN202110025615A CN112838131A CN 112838131 A CN112838131 A CN 112838131A CN 202110025615 A CN202110025615 A CN 202110025615A CN 112838131 A CN112838131 A CN 112838131A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Abstract
The invention relates to a semiconductor device, in particular to a Schottky diode based on a silicon carbide planar MOS structure. According to the technical scheme provided by the invention, the Schottky diode based on the silicon carbide planar MOS structure comprises a semiconductor substrate and a P-type well region arranged on the semiconductor substrate, wherein a cathode region structure is arranged on one side of the P-type well region, an anode region structure is arranged on the other side of the P-type well region, the P-type well region is in contact with a gate structure region arranged on the P-type well region, a gate metal is arranged on the gate structure region, and the gate metal is in ohmic contact with the gate structure region. The invention effectively reduces the switching loss of the semiconductor device and improves the switching speed of the semiconductor device, and can also realize that the MOS gate channel controls the switching of the Schottky diode, thereby improving the electrical property of the Schottky diode.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a Schottky diode based on a silicon carbide planar MOS structure.
Background
The silicon carbide (SiC) material has the advantages of large forbidden band width, high critical breakdown field strength, large thermal conductivity, high saturated electron drift velocity, low dielectric constant and the like, and is widely applied to electronic devices with high frequency, high power, high temperature resistance, radiation resistance and the like.
The silicon carbide schottky diode has a majority of conductive carriers, has a low turn-on voltage when forward biased, has almost no reverse recovery current when the applied voltage is switched from forward to reverse blocking, and can recover quickly, but can generate a severe leakage current phenomenon under reverse bias due to schottky barrier lowering effect.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a Schottky diode based on a silicon carbide planar MOS structure, which effectively reduces the switching loss of a semiconductor device and improves the switching speed of the semiconductor device, and can realize that an MOS gate channel controls the switching of the Schottky diode, thereby improving the electrical performance of the Schottky diode.
According to the technical scheme provided by the invention, the Schottky diode based on the silicon carbide planar MOS structure comprises a semiconductor substrate and a P-type well region arranged on the semiconductor substrate, wherein a cathode region structure is arranged on one side of the P-type well region, an anode region structure is arranged on the other side of the P-type well region, the P-type well region is in contact with a gate structure region arranged on the P-type well region, a gate metal is arranged on the gate structure region, and the gate metal is in ohmic contact with the gate structure region.
The negative electrode region structure comprises an N-type lightly doped negative electrode region in contact with the P-type well region, an N-type heavily doped negative electrode region located in the N-type lightly doped negative electrode region and a negative electrode metal layer located right above the N-type heavily doped negative electrode region, and the negative electrode metal layer is in ohmic contact with the N-type heavily doped negative electrode region.
The positive electrode area structure comprises an N-type lightly doped positive electrode area, a positive electrode metal area and a positive electrode metal layer, wherein the N-type lightly doped positive electrode area is arranged in the P-type trap area, the positive electrode metal area is arranged in the N-type lightly doped positive electrode area, the positive electrode metal layer is arranged above the positive electrode metal area, and the positive electrode metal layer is electrically connected with the positive electrode metal area.
The gate structure region comprises a polycrystalline silicon layer and a high-dielectric-constant insulating layer positioned below the polycrystalline silicon layer, and the polycrystalline silicon layer is in ohmic contact with the gate metal layer.
The semiconductor substrate includes a SiC substrate.
The negative metal layer and the grid metal layer are the same process layer, and the negative metal layer and the grid metal layer comprise copper or aluminum.
The positive electrode metal layer and the grid electrode metal layer are the same process layer and comprise copper or aluminum.
The invention has the advantages that: by adopting the N-type lightly doped anode region and the N-type lightly doped cathode region, the gate-channel ratio and the on-resistance of the MOS transistor can be effectively reduced, and the gate leakage current effect can be effectively reduced; when the grid of the MOS tube does not work, the grid channel is cut off, and the Schottky diode does not work; when the grid of the MOS tube works, the grid channel is conducted, at the moment, the Schottky diode is connected with forward voltage, electrons can enter the anode metal region from the N-type heavily doped cathode region through the grid channel, when the Schottky diode is connected with reverse voltage, the Schottky barrier region near the anode metal region is widened, and the switching loss can be effectively reduced and the switching speed can be improved by adjusting the formation of the grid channel of the MOS, so that the electrical property of the semiconductor device can be improved.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
Description of reference numerals: the semiconductor device comprises a 1-semiconductor substrate, a 2-P type well region, a 3-N type light doped negative electrode region, a 4-N type heavy doped negative electrode region, a 5-N type light doped positive electrode region, a 6-positive electrode metal region, a 7-high dielectric constant insulating layer, an 8-positive electrode metal layer, a 9-grid metal layer and a 10-negative electrode metal layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1: in order to effectively reduce the switching loss of the semiconductor device and improve the switching speed of the semiconductor device, and further realize that an MOS gate channel controls the switching of the Schottky diode, so as to improve the electrical performance of the Schottky diode, in the embodiment of the invention, the Schottky diode comprises a semiconductor substrate 1 and a P-type well region 2 arranged on the semiconductor substrate 1, a cathode region structure is arranged on one side of the P-type well region 2, an anode region structure is arranged on the other side of the P-type well region 2, the P-type well region 2 is in contact with a gate structure region arranged on the P-type well region 2, a gate metal 9 is arranged on the gate structure region, and the gate metal 9 is in ohmic contact with the gate structure region.
Specifically, the semiconductor substrate 1 comprises a SiC substrate, and when the semiconductor substrate 1 adopts the SiC substrate, the prepared schottky diode has corresponding advantages; of course, the semiconductor substrate 1 may also be made of other semiconductor materials, which may be selected according to the needs and will not be described herein again. The P-type well region 2 can be prepared by adopting the existing common process, after the P-type well region 2 is prepared, a negative electrode region structure is prepared on one side of the P-type well region 2, a positive electrode region structure is prepared on the other side of the P-type well region 2, and a negative electrode end and a positive electrode end of the schottky diode can be respectively formed by the negative electrode region structure and the positive electrode region structure, and are specifically consistent with the technical field, well known by the technical field personnel and are not repeated here.
A gate structure region is arranged right above the P-type well region 2, the gate structure region is in contact with the upper end face of the P-type well region 2, a gate metal 9 is arranged on the gate structure region, the gate metal 9 is in ohmic contact with the gate structure region, and therefore the gate metal 9 is matched with the gate structure region, and a planar MOSFET structure can be formed by the positive electrode region structure and the negative electrode region structure.
Further, the cathode region structure comprises an N-type lightly doped cathode region 3 in contact with the P-type well region 2, an N-type heavily doped cathode region 4 located in the N-type lightly doped cathode region 3, and a cathode metal layer 10 located right above the N-type heavily doped cathode region 4, wherein the cathode metal layer 10 is in ohmic contact with the N-type heavily doped cathode region 4.
In the embodiment of the present invention, the N-type lightly doped cathode region 3 and the N-type heavily doped cathode region 4 are prepared by a conventional technical means in the field, and a specific process is well known to those skilled in the art, such as ion implantation, and will not be described herein again. The N-type lightly doped cathode region 3 is in contact with the P-type well region 2, the thickness of the N-type lightly doped cathode region 3 is smaller than that of the P-type well region 2, the N-type lightly doped cathode region 3 can be isolated from the semiconductor substrate 1 through the P-type well region 2, the doping concentration of the N-type heavily doped cathode region 4 is larger than that of the N-type lightly doped cathode region 3, and the N-type heavily doped cathode region 4 is located in the N-type lightly doped cathode region 3. The cathode metal layer 10 is in ohmic contact with the N-type heavily doped cathode region 4, and the cathode end of the Schottky diode can be formed through the cathode metal layer 10.
Further, the positive electrode region structure comprises an N-type lightly doped positive electrode region 5 of the P-type well region 2, a positive electrode metal region 6 located in the N-type lightly doped positive electrode region 5, and a positive electrode metal layer 8 located above the positive electrode metal region 6, wherein the positive electrode metal layer 8 is electrically connected with the positive electrode metal region 6.
In the embodiment of the present invention, the condition of the N-type lightly doped anode region 5 is similar to that of the N-type lightly doped cathode region 3, and specific reference may be made to the description of the N-type lightly doped cathode region 3, which is not repeated herein. The positive metal region 6 is disposed in the N-type lightly doped positive region 5, and the positive metal layer 8 is formed with the positive metal region 6, so that the positive terminal of the schottky diode can be formed by the positive metal layer 8. In specific implementation, the metal filling region may be obtained by processes such as photolithography and etching, and then the metal is deposited by processes such as CVD to obtain the positive electrode metal region 6, and the specific process for preparing the positive electrode metal region 6 is well known to those skilled in the art and will not be described herein again.
In specific implementation, the cathode metal layer 10, the gate metal layer 9, and the anode metal layer 8 are the same process layer, and the materials of the cathode metal layer 10, the gate metal layer 9, and the anode metal layer 8 include copper or aluminum.
The gate structure region comprises a polysilicon layer 11 and a high dielectric constant insulating layer 7 positioned below the polysilicon layer 11, and the polysilicon layer 11 is in ohmic contact with the gate metal layer 9. In the embodiment of the present invention, the dielectric constant of the high-k insulating layer 7 may generally be a material having a dielectric constant greater than 2.8, and when a voltage is applied to the gate metal layer 9 during specific operation, ions of opposite charges are absorbed by the high-k insulating layer 7, so that a gate channel can be formed.
In the embodiment of the invention, the gate-channel ratio and the on-resistance of the MOS transistor can be effectively reduced and the gate leakage current effect can be reduced by adopting the N-type lightly doped anode 5 and the N-type lightly doped cathode region 3, and the switching effect of the Schottky diode can be effectively realized by adopting the N-type lightly doped anode region 5; when the grid of the MOS tube does not work (specifically, the grid is not loaded with voltage or the loaded voltage does not reach a threshold circuit for starting the grid), the grid channel is cut off, and the Schottky diode does not work; when the grid of the MOS tube works, the grid channel is conducted, at the moment, the Schottky diode is connected with forward voltage, electrons can enter the anode metal region 6 from the N-type heavily doped cathode region 4 through the grid channel, when the Schottky diode is connected with reverse voltage, the Schottky barrier region near the anode metal region 6 is widened, and the grid channel of the MOS is adjusted to form, so that the switching loss can be effectively reduced, the switching speed can be effectively increased, and the electrical property of the semiconductor device can be further improved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A Schottky diode based on a silicon carbide planar MOS structure is characterized in that: on schottky diode's the cross-section, including semiconductor substrate (1) and set up in well region (2) of P type on semiconductor substrate (1) one side of well region (2) of P type sets up negative pole district structure the opposite side of well region (2) of P type sets up positive polar region structure, and well region (2) of P type with be located grid structure district contact on the well region (2) of P type sets up grid metal (9) on the grid structure district, grid metal (9) and grid structure district ohmic contact.
2. The schottky diode of claim 1 based on a silicon carbide planar MOS structure, wherein: the negative electrode region structure comprises an N-type lightly doped negative electrode region (3) in contact with a P-type well region (2), an N-type heavily doped negative electrode region (4) located in the N-type lightly doped negative electrode region (3) and a negative electrode metal layer (10) located right above the N-type heavily doped negative electrode region (4), wherein the negative electrode metal layer (10) is in ohmic contact with the N-type heavily doped negative electrode region (4).
3. The schottky diode of claim 1 based on a silicon carbide planar MOS structure, wherein: the positive pole district structure includes with N type lightly doped positive pole district (5) of P type trap district (2), be located anodal metal area (6) in N type lightly doped positive pole district (5) and be located anodal metal level (8) of anodal metal area (6) top, anodal metal level (8) are connected with anodal metal area (6) electricity.
4. The schottky diode based on the silicon carbide planar MOS structure of claim 1, 2 or 3, wherein: the grid structure region comprises a polycrystalline silicon layer (11) and a high-dielectric-constant insulating layer (7) positioned below the polycrystalline silicon layer (11), and the polycrystalline silicon layer (11) is in ohmic contact with a grid metal layer (9).
5. The schottky diode of claim 1 based on a silicon carbide planar MOS structure, wherein: the semiconductor substrate (1) includes a SiC substrate.
6. The schottky diode of claim 2 based on a silicon carbide planar MOS structure, wherein: the negative metal layer (10) and the grid metal layer (9) are the same process layer, and the negative metal layer (10) and the grid metal layer (9) comprise copper or aluminum.
7. The schottky diode of claim 3 based on a silicon carbide planar MOS structure, wherein: the positive electrode metal layer (8) and the grid electrode metal layer (9) are the same process layer, and the positive electrode metal layer (8) and the grid electrode metal layer (9) comprise copper or aluminum.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110025615.XA CN112838131B (en) | 2021-01-08 | 2021-01-08 | Schottky diode based on silicon carbide planar MOS structure |
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| CN202110025615.XA CN112838131B (en) | 2021-01-08 | 2021-01-08 | Schottky diode based on silicon carbide planar MOS structure |
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| CN112838131A true CN112838131A (en) | 2021-05-25 |
| CN112838131B CN112838131B (en) | 2022-02-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725077A (en) * | 2021-08-31 | 2021-11-30 | 江苏东海半导体科技有限公司 | Schottky barrier device and method of forming the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060125040A1 (en) * | 2004-12-15 | 2006-06-15 | Tower Semiconductor Ltd. | Cobalt silicide schottky diode on isolated well |
| CN102347373A (en) * | 2010-08-03 | 2012-02-08 | 旺宏电子股份有限公司 | Schottky diode |
| US20160233210A1 (en) * | 2015-02-11 | 2016-08-11 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN106784008A (en) * | 2017-01-22 | 2017-05-31 | 北京世纪金光半导体有限公司 | A kind of SiC MOSFET elements of integrated schottky diode |
| CN110459540A (en) * | 2019-07-30 | 2019-11-15 | 创能动力科技有限公司 | The semiconductor device and its manufacturing method of integrated MOSFET and diode |
-
2021
- 2021-01-08 CN CN202110025615.XA patent/CN112838131B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060125040A1 (en) * | 2004-12-15 | 2006-06-15 | Tower Semiconductor Ltd. | Cobalt silicide schottky diode on isolated well |
| CN102347373A (en) * | 2010-08-03 | 2012-02-08 | 旺宏电子股份有限公司 | Schottky diode |
| US20160233210A1 (en) * | 2015-02-11 | 2016-08-11 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN106784008A (en) * | 2017-01-22 | 2017-05-31 | 北京世纪金光半导体有限公司 | A kind of SiC MOSFET elements of integrated schottky diode |
| CN110459540A (en) * | 2019-07-30 | 2019-11-15 | 创能动力科技有限公司 | The semiconductor device and its manufacturing method of integrated MOSFET and diode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725077A (en) * | 2021-08-31 | 2021-11-30 | 江苏东海半导体科技有限公司 | Schottky barrier device and method of forming the same |
| CN113725077B (en) * | 2021-08-31 | 2022-08-05 | 江苏东海半导体股份有限公司 | Schottky barrier device and method of forming the same |
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| CN112838131B (en) | 2022-02-11 |
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Address after: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee after: Jiangsu Donghai Semiconductor Co.,Ltd. Address before: No. 88, Zhongtong East Road, Shuofang street, Xinwu District, Wuxi City, Jiangsu Province Patentee before: WUXI ROUM SEMICONDUCTOR TECHNOLOGY Co.,Ltd. |
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