CN115579397A - Two-stage trench gate silicon carbide MOSFET and preparation method thereof - Google Patents
Two-stage trench gate silicon carbide MOSFET and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 74
- 239000002184 metal Substances 0.000 claims description 74
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- 229920005591 polysilicon Polymers 0.000 claims description 18
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
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- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 9
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention relates to a two-stage trench gate silicon carbide MOSFET and a preparation method thereof, which simultaneously realize high blocking voltage, low gate oxide electric field and low on-resistance by introducing a two-stage gate trench and a current expansion layer below the two-stage gate trench: in a blocking state, the P + shielding layer is connected to the P-type base region through the P-type side wall region, so that an electric field of the gate oxide layer is effectively shielded; when the high-doping current is conducted in the forward direction, electron current enters the drift region along the multi-stage grooves in the high-doping current expansion layer, and the forward conduction capability is improved; in a short-circuit state, depletion pinch-off is formed between adjacent P + shielding layers, and the short-circuit capability of the device is improved. On the premise of ensuring the reliability of the gate oxide layer of the two-stage trench gate silicon carbide MOSFET, the invention keeps the advantages of low on-resistance and low switching loss and simultaneously improves the short-circuit capability of the trench gate silicon carbide MOSFET device.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a two-stage trench gate silicon carbide MOSFET.
Background
Silicon Carbide (Silicon Carbide) material is one of the representatives of the third generation wide bandgap semiconductor material, has the characteristics of large forbidden bandwidth, high critical avalanche breakdown field strength, high heat conductivity coefficient, strong radiation resistance and the like, and has wide application prospect in high-voltage high-power systems. The silicon carbide MOSFET has the characteristics of low conduction loss, high voltage of resistance to power failure, high switching speed, good high-temperature performance, strong irradiation resistance and the like. Silicon carbide MOSFETs mainly have two types, planar gate and trench gate: JFET effect exists between adjacent P-type base regions of the planar silicon carbide MOSFET so that the planar silicon carbide MOSFET has on-resistance; and the groove type silicon carbide MOSFET eliminates JFET effect, and is beneficial to improving the electrical characteristics of the device.
Although the trench gate silicon carbide MOSFET is more favorable for relieving the contradictory relationship between the on-resistance and the blocking voltage, when the trench gate silicon carbide MOSFET is in the blocking state, the blocking voltage is borne by the P-type base region and the PN junction of the drift region, which are reversely biased. When the device is in critical breakdown, the field intensity in the gate oxide layer is far higher than the peak value of the field intensity in the silicon carbide, about 2.5 times of the field intensity in the silicon carbide, and the failure risk caused by the degradation of the gate oxide layer is increased steeply. In order to solve the problem that the electric field intensity of the gate oxide of the device in a blocking state is too large, the electric field intensity of the gate oxide is weakened by adopting a grounding P + shielding layer, and the reliability of the gate oxide is improved.
The grounded P + shielding layer can effectively reduce the electric field intensity of the trench gate oxide layer, but the forward on-resistance is sharply improved, so that the on-loss of the silicon carbide MOSFET device is remarkably improved.
Disclosure of Invention
In order to solve the above problems, the present invention provides a two-stage trench gate silicon carbide MOSFET and a method for manufacturing the same. The high blocking voltage, the low gate oxide electric field and the low on-resistance are realized simultaneously by introducing the double-stage gate groove and the current expansion layer below the double-stage gate groove: when the grid oxide layer is in a blocking state, the P + shielding layer is connected to the P type base region through the P type side wall region, and an electric field of the grid oxide layer is effectively shielded; when the high-doping current is conducted in the forward direction, electron current enters the drift region along the multi-stage grooves in the high-doping current expansion layer, and the forward conduction capability is improved; in a short-circuit state, depletion pinch-off is formed between adjacent P + shielding layers, and the short-circuit capability of the device is improved. On the premise of ensuring the reliability of the gate oxide layer of the two-stage trench gate silicon carbide MOSFET, the invention keeps the advantages of low on-resistance and low switching loss and simultaneously improves the short-circuit capability of the trench gate silicon carbide MOSFET device.
In order to achieve the purpose, the invention adopts the following technical scheme:
a double-stage trench gate silicon carbide MOSFET comprises a drain metal 8, an N + substrate 7 above the drain metal 8, and an N-drift region 6 above the N + substrate 7; a first P + shielding layer 5 is arranged on the left side of the upper part inside the N-drift region 6, a first P-type side wall region 4 is arranged above the first P + shielding layer 5, a first P-type base region 3 is arranged above the first P-type side wall region 4, a first P + ohmic contact region 2 is arranged on the left upper part of the first P-type base region 3, and a first N + source region 10 is arranged on the right upper part of the first P-type base region 3; a second P + shielding layer 51 is arranged on the right side of the upper part inside the N-drift region 6, a second P-type side wall region 41 is arranged above the second P + shielding layer 51, a second P-type base region 31 is arranged above the second P-type side wall region 41, a second P + ohmic contact region 21 is arranged on the right upper part of the second P-type base region 31, and a second N + source region 101 is arranged on the left upper part of the second P-type base region 31; a double-stage groove is formed in the upper center inside the N-drift region 6, a polycrystalline silicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer 9 is arranged below the double-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10; a second source metal 11 is arranged above the second P + ohmic contact region 21 and the second N + source region 101; above the polysilicon gate 121 is a gate metal 12.
Preferably, the gate dielectric 111 is SiO 2 。
As a preferred mode, the first P + ohmic contact region 2, the first N + source region 10, the first P-type base region 3, the first P-type sidewall region 4, the first P + shielding layer 5, the second P + ohmic contact region 21, the second N + source region 101, the second P-type base region 31, the first P-type sidewall region 41, the second P + shielding layer 51, and the N-type current spreading layer 9 are all formed by multiple ion implantation.
Preferably, the first P + ohmic contact region 2, the first N + source region 10, the first P-type base region 3, the first P-type sidewall region 4, the first P + shielding layer 5, the second P + ohmic contact region 21, the second N + source region 101, the second P-type base region 31, the first P-type sidewall region 41, the second P + shielding layer 51, the N-type current spreading layer 9, the N-drift region 6, and the N + substrate 7 of the device are all made of silicon carbide.
In order to achieve the above object, the present invention further provides a second two-stage trench gate silicon carbide MOSFET, including a drain metal 8, an N + substrate 7 over the drain metal 8, and an N-drift region 6 over the N + substrate 7; a double-stage groove is formed in the center of the upper portion inside the N-drift region 6, a polysilicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, an N-type current expansion layer 9 is arranged on the left side of the double-stage groove, a first P-type base region 3 is arranged on the upper left side of the N-type current expansion layer 9, a first P + ohmic contact region 2 is arranged on the upper left side of the first P-type base region 3, a first N + source region 10 is arranged on the upper right side of the first P-type base region 3, a second P-type side wall region 41 is arranged on the right side of the double-stage groove, a second P-type base region 31 is arranged on the upper right side of the second P-type side wall region 41, and a second P + ohmic contact region 21 is arranged on the upper side of the second P-type base region 31; a first P + shielding layer 5 is arranged below the double-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10; a second source metal 11 is arranged above the second P + ohmic contact region 21; above the polysilicon gate 121 is a gate metal 12.
In order to achieve the above object, the present invention further provides a third two-stage trench gate silicon carbide MOSFET, including a drain metal 8, an N + substrate 7 over the drain metal 8, and an N-drift region 6 over the N + substrate 7; a first P + shielding layer 5 is arranged on the left side of the upper portion inside the N-drift region 6, a first P-type side wall region 4 is arranged on the first P + shielding layer 5, a first dielectric layer 14 is arranged on the left side of the first P-type side wall region 4, a first schottky metal 13 is arranged on the left lower side of the first dielectric layer 14, a first P-type base region 3 is arranged on the upper portion of the first P-type side wall region 4, a first P + ohmic contact region 2 is arranged on the left upper portion of the first P-type base region 3, and a first N + source region 10 is arranged on the right upper portion of the first P-type base region 3; a second P + shielding layer 51 is arranged on the right side above the inside of the N-drift region 6, a second P-type side wall region 41 is arranged above the second P + shielding layer 51, a second dielectric layer 141 is arranged on the right side of the second P-type side wall region 41, a second schottky metal 131 is arranged on the right lower side of the second dielectric layer 141, a second P-type base region 31 is arranged above the second P-type side wall region 41, a second P + ohmic contact region 21 is arranged on the right upper side of the second P-type base region 31, and a second N + source region 101 is arranged on the left upper side of the second P-type base region 31; a double-stage groove is formed in the upper center inside the N-drift region 6, a polycrystalline silicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer 9 is arranged below the double-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10, and a first source metal 1 is arranged above the first schottky metal 13 and on the left side of the first dielectric layer 14; a second source metal 11 is arranged above the second P + ohmic contact region 21 and the second N + source region 101, and a second source metal 11 is arranged above the second schottky metal 131 and on the right side of the second dielectric layer 141; above the polysilicon gate 121 is a gate metal 12.
In order to achieve the above object, the present invention further provides a method for manufacturing a two-stage trench gate silicon carbide MOSFET, comprising the following steps:
the first step is as follows: cleaning an epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking the polycrystalline silicon as an injection barrier layer to form a P + shielding layer;
the second step: performing secondary epitaxy and injecting aluminum ions by taking the polycrystalline silicon as an injection barrier layer to form a P-type side wall region;
the third step: performing third epitaxy and injecting aluminum ions to form a P-type base region;
the fourth step: injecting aluminum ions to form a P + ohmic contact region;
the fifth step: injecting nitrogen ions to form an N + source region and activating and annealing;
and a sixth step: etching the gate groove;
the seventh step: injecting nitrogen ions by taking the polycrystalline silicon as an injection barrier layer to form an N-type current expansion layer;
eighth step: oxidizing dry oxygen to generate a gate oxide layer, then annealing and depositing polycrystalline silicon in a nitrogen atmosphere, and patterning the polycrystalline silicon;
the ninth step: depositing and etching metal to form an electrode;
according to the invention, by introducing the double-stage gate groove structure and the N-type current expansion layer below the double-stage gate groove structure, the electric field intensity of the gate oxide layer is effectively reduced when the device is in a forward blocking state, and meanwhile, the device is ensured to have good forward conduction characteristics, the switching loss of the device is reduced, and the short-circuit capability of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional trench-gate silicon carbide MOSFET structure with a P-type sidewall region and a P + shield layer;
fig. 2 is a schematic structural view of a two-stage trench gate silicon carbide MOSFET of embodiment 1 of the present invention;
fig. 3 is a schematic diagram of cleaning an epitaxial wafer, and implanting aluminum ions to form a P + shielding layer on an N-epi by using polysilicon as an implantation barrier layer according to embodiment 4 of the present invention;
fig. 4 is a schematic view of forming a P-type sidewall region by performing second epitaxy and implanting aluminum ions using polysilicon as an implantation barrier layer in embodiment 4 of the present invention;
fig. 5 is a schematic view of a third epitaxy and implantation of aluminum ions to form a P-type base region according to embodiment 4 of the present invention;
FIG. 6 is a schematic diagram of forming a P + ohmic contact region by aluminum ion implantation in example 4 of the present invention;
FIG. 7 is a schematic diagram of implanting nitrogen ions to form N + source regions and activating annealing according to example 4 of the present invention;
FIG. 8 is a schematic view of an etched gate trench according to embodiment 4 of the present invention;
fig. 9 is a schematic view of forming an N-type current spreading layer by implanting nitrogen ions using polysilicon as an implantation barrier layer according to embodiment 4 of the present invention;
FIG. 10 is a schematic diagram of the patterning of polysilicon by the dry oxygen oxidation to form a gate oxide layer followed by the annealing deposition of polysilicon under a nitrogen atmosphere in accordance with example 4 of the present invention;
FIG. 11 is a schematic view of depositing and etching a metal to form an electrode according to embodiment 4 of the present invention;
fig. 12 is a schematic view of a two-stage trench gate silicon carbide MOSFET structure according to embodiment 2 of the present invention;
fig. 13 is a schematic structural view of a two-stage trench-gate silicon carbide MOSFET of embodiment 3 of the present invention;
1 is a first source metal, 2 is a first P + ohmic contact region, 3 is a first P-type base region, 4 is a first P-type sidewall region, 5 is a first P + shield layer, 6 is an N-drift region, 7 is an N + substrate, 8 is a drain metal, 9 is an N-type current spreading layer, 10 is a first N + source region, 11 is a second source metal, 12 is a gate metal, 13 is a first schottky metal, 14 is a first dielectric layer, 21 is a second P + ohmic contact region, 31 is a second P-type base region, 41 is a second P-type sidewall region, 51 is a second P + shield layer, 101 is a second N + source region, 111 is a gate dielectric, 121 is a polysilicon gate, 131 is a second schottky metal, 141 is a second dielectric layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 2, a two-stage trench gate silicon carbide MOSFET device includes a drain metal 8, an N + substrate 7 over the drain metal 8, and an N-drift region 6 over the N + substrate 7; a first P + shielding layer 5 is arranged on the left side of the upper part inside the N-drift region 6, a first P-type side wall region 4 is arranged above the first P + shielding layer 5, a first P-type base region 3 is arranged above the first P-type side wall region 4, a first P + ohmic contact region 2 is arranged on the upper left side of the first P-type base region 3, and a first N + source region 10 is arranged on the upper right side of the first P-type base region 3; a second P + shielding layer 51 is arranged on the right side of the upper part inside the N-drift region 6, a second P-type side wall region 41 is arranged above the second P + shielding layer 51, a second P-type base region 31 is arranged above the second P-type side wall region 41, a second P + ohmic contact region 21 is arranged on the right upper part of the second P-type base region 31, and a second N + source region 101 is arranged on the left upper part of the second P-type base region 31; a double-stage groove is formed in the upper center inside the N-drift region 6, a polycrystalline silicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer 9 is arranged below the double-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10; a second source metal 11 is arranged above the second P + ohmic contact region 21 and the second N + source region 101; above the polysilicon gate 121 is a gate metal 12.
Preferably, the gate dielectric is SiO 2 。
As a preferred mode, the first P + ohmic contact region 2, the first N + source region 10, the first P-type base region 3, the first P-type sidewall region 4, the first P + shielding layer 5, the second P + ohmic contact region 21, the second N + source region 101, the second P-type base region 31, the first P-type sidewall region 41, the second P + shielding layer 51, and the N-type current spreading layer 9 are all formed by multiple ion implantation.
Preferably, the first P + ohmic contact region 2, the first N + source region 10, the first P-type base region 3, the first P-type sidewall region 4, the first P + shielding layer 5, the second P + ohmic contact region 21, the second N + source region 101, the second P-type base region 31, the first P-type sidewall region 41, the second P + shielding layer 51, the N-type current spreading layer 9, the N-drift region 6, and the N + substrate 7 of the device are all made of silicon carbide.
In the embodiment, the double-stage gate groove structure and the N-type current expansion layer below the double-stage gate groove structure are introduced, so that the electric field intensity of the gate oxide layer is effectively reduced when the device is in a forward blocking state, the device is guaranteed to have good forward conduction characteristics, the switching loss of the device is reduced, and the short circuit capability of the device is improved.
Example 2
In this embodiment, the P-type shielding layer is formed by injecting aluminum ions after the trench is etched, the N-type current spreading layer is formed by injecting oblique ion nitrogen, and the P-type sidewall region is formed by injecting oblique aluminum ions. A normally-on P-MOSFET is introduced on the front side of the device to automatically adjust the potential of the P-shield.
As shown in fig. 12, a two-stage trench gate silicon carbide MOSFET device comprises a drain metal 8, an N + substrate 7 over the drain metal 8, and an N-drift region 6 over the N + substrate 7; a double-stage groove is formed in the center of the upper portion inside the N-drift region 6, a polysilicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, an N-type current expansion layer 9 is arranged on the left side of the double-stage groove, a first P-type base region 3 is arranged on the left upper portion of the N-type current expansion layer 9, a first P + ohmic contact region 2 is arranged on the left upper portion of the first P-type base region 3, a first N + source region 10 is arranged on the right upper portion of the first P-type base region 3, a second P-type side wall region 41 is arranged on the right upper portion of the double-stage groove, a second P-type base region 31 is arranged on the right upper portion of the second P-type side wall region 41, and a second P + ohmic contact region 21 is arranged on the upper portion of the second P-type base region 31; a first P + shielding layer 5 is arranged below the two-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10; a second source metal 11 is arranged above the second P + ohmic contact region 21; above the polysilicon gate 121 is a gate metal 12.
Example 3
On the basis of embodiment 1, the schottky barrier diode is monolithically integrated on the side surface of the P-type side wall region to improve the third quadrant characteristic of the device, and the schottky metal is wrapped by the P-type shielding layer, so that the thermionic emission current of the schottky barrier diode is reduced, and the electric leakage of the device is reduced.
As shown in fig. 13, a two-stage trench gate silicon carbide MOSFET device includes a drain metal 8, an N + substrate 7 over the drain metal 8, an N-drift region 6 over the N + substrate 7; a first P + shielding layer 5 is arranged on the left side of the upper part inside the N-drift region 6, a first P-type side wall region 4 is arranged on the upper part of the first P + shielding layer 5, a first dielectric layer 14 is arranged on the left side of the first P-type side wall region 4, a first schottky metal 13 is arranged on the left lower part of the first dielectric layer 14, a first P-type base region 3 is arranged on the upper part of the first P-type side wall region 4, a first P + ohmic contact region 2 is arranged on the left upper part of the first P-type base region 3, and a first N + source region 10 is arranged on the right upper part of the first P-type base region 3; a second P + shielding layer 51 is arranged on the right side above the inside of the N-drift region 6, a second P-type side wall region 41 is arranged above the second P + shielding layer 51, a second dielectric layer 141 is arranged on the right side of the second P-type side wall region 41, a second schottky metal 131 is arranged on the right lower side of the second dielectric layer 141, a second P-type base region 31 is arranged above the second P-type side wall region 41, a second P + ohmic contact region 21 is arranged on the right upper side of the second P-type base region 31, and a second N + source region 101 is arranged on the left upper side of the second P-type base region 31; a double-stage groove is formed in the center of the upper portion inside the N-drift region 6, a polycrystalline silicon gate 121 and a gate medium 111 filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer 9 is arranged below the double-stage groove; a first source metal 1 is arranged above the first P + ohmic contact region 2 and the first N + source region 10, and a first source metal 1 is arranged above the first schottky metal 13 and on the left side of the first dielectric layer 14; a second source metal 11 is arranged above the second P + ohmic contact region 21 and the second N + source region 101, and a second source metal 11 is arranged above the second schottky metal 131 and on the right side of the second dielectric layer 141; above the polysilicon gate 121 is a gate metal 12.
Example 4
As shown in fig. 3 to 11, the present example provides a method for manufacturing a dual-stage trench gate silicon carbide MOSFET device, including the steps of:
the first step is as follows: cleaning an epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking polycrystalline silicon as an injection barrier layer to form a P + shielding layer; as shown in fig. 3;
the second step: performing secondary epitaxy and injecting aluminum ions by taking the polycrystalline silicon as an injection barrier layer to form a P-type side wall region; as shown in fig. 4;
the third step: performing third epitaxy and injecting aluminum ions to form a P-type base region; as shown in fig. 5;
the fourth step: injecting aluminum ions to form a P + ohmic contact region; as shown in fig. 6;
the fifth step: injecting nitrogen ions to form an N + source region and activating and annealing; as shown in fig. 7;
and a sixth step: etching the gate groove; as shown in fig. 8;
the seventh step: injecting nitrogen ions by taking the polycrystalline silicon as an injection barrier layer to form an N-type current expansion layer; as shown in fig. 9;
eighth step: oxidizing dry oxygen to generate a gate oxide layer, then annealing and depositing polycrystalline silicon in a nitrogen atmosphere, and patterning the polycrystalline silicon; as shown in fig. 10;
the ninth step: depositing and etching metal to form an electrode; as shown in fig. 11;
the foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A two-stage trench gate silicon carbide MOSFET is characterized in that: the transistor comprises drain electrode metal (8), an N + substrate (7) above the drain electrode metal (8) and an N-drift region (6) above the N + substrate (7); a first P + shielding layer (5) is arranged on the left side of the upper portion inside the N-drift region (6), a first P type side wall region (4) is arranged above the first P + shielding layer (5), a first P type base region (3) is arranged above the first P type side wall region (4), a first P + ohmic contact region (2) is arranged on the left upper portion of the first P type base region (3), and a first N + source region (10) is arranged on the right upper portion of the first P type base region (3); a second P + shielding layer (51) is arranged on the right side of the upper part inside the N-drift region (6), a second P-type side wall region (41) is arranged above the second P + shielding layer (51), a second P-type base region (31) is arranged above the second P-type side wall region (41), a second P + ohmic contact region (21) is arranged on the right upper part of the second P-type base region (31), and a second N + source region (101) is arranged on the left upper part of the second P-type base region (31); a double-stage groove is formed in the center of the upper portion inside the N-drift region (6), a polycrystalline silicon gate (121) and a gate medium (111) filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer (9) is arranged below the double-stage groove; a first source metal (1) is arranged above the first P + ohmic contact region (2) and the first N + source region (10); a second source metal (11) is arranged above the second P + ohmic contact region (21) and the second N + source region (101); and a gate metal (12) is arranged above the polysilicon gate (121).
2. The two-stage trench-gate silicon carbide MOSFET of claim 1, wherein: the gate dielectric (111) is SiO 2 。
3. The dual-stage trench-gate silicon carbide MOSFET of claim 1, wherein: the first P + ohmic contact region (2), the first N + source region (10), the first P type base region (3), the first P type side wall region (4), the first P + shielding layer (5), the second P + ohmic contact region (21), the second N + source region (101), the second P type base region (31), the first P type side wall region (41), the second P + shielding layer (51) and the N type current expansion layer (9) are formed by multiple times of ion implantation.
4. The two-stage trench-gate silicon carbide MOSFET of claim 1, wherein: the device is characterized in that the first P + ohmic contact region (2), the first N + source region (10), the first P type base region (3), the first P type side wall region (4), the first P + shielding layer (5), the second P + ohmic contact region (21), the second N + source region (101), the second P type base region (31), the first P type side wall region (41), the second P + shielding layer (51), the N type current expansion layer (9), the N-drift region (6) and the N + substrate (7) are made of silicon carbide.
5. A two-stage trench gate silicon carbide MOSFET is characterized in that: the transistor comprises drain electrode metal (8), an N + substrate (7) above the drain electrode metal (8) and an N-drift region (6) above the N + substrate (7); a double-stage groove is formed in the center of the upper portion inside the N-drift region (6), a polysilicon gate (121) and a gate medium (111) filling the double-stage groove are arranged in the double-stage groove, an N-type current expansion layer (9) is arranged on the left side of the double-stage groove, a first P-type base region (3) is arranged above the left side of the N-type current expansion layer (9), a first P + ohmic contact region (2) is arranged above the left side of the first P-type base region (3), a first N + source region (10) is arranged above the right side of the first P-type base region (3), a second P-type side wall region (41) is arranged on the right side of the double-stage groove, a second P-type base region (31) is arranged above the second P-type side wall region (41), and a second P + ohmic contact region (21) is arranged above the second P-type base region (31); a first P + shielding layer (5) is arranged below the double-stage groove; a first source metal (1) is arranged above the first P + ohmic contact region (2) and the first N + source region (10); a second source metal (11) is arranged above the second P + ohmic contact region (21); and a gate metal (12) is arranged above the polysilicon gate (121).
6. A two-stage trench gate silicon carbide MOSFET is characterized in that: comprises drain metal (8), an N + substrate (7) above the drain metal (8), and an N-drift region (6) above the N + substrate (7); a first P + shielding layer (5) is arranged on the left side of the upper portion inside the N-drift region (6), a first P-type side wall region (4) is arranged on the upper portion of the first P + shielding layer (5), a first dielectric layer (14) is arranged on the left side of the first P-type side wall region (4), a first Schottky metal (13) is arranged on the lower left of the first dielectric layer (14), a first P-type base region (3) is arranged on the upper portion of the first P-type side wall region (4), a first P + ohmic contact region (2) is arranged on the upper left of the first P-type base region (3), and a first N + source region (10) is arranged on the upper right of the first P-type base region (3); a second P + shielding layer (51) is arranged on the right side of the upper portion inside the N-drift region (6), a second P-type side wall region (41) is arranged on the upper portion of the second P + shielding layer (51), a second dielectric layer (141) is arranged on the right side of the second P-type side wall region (41), second Schottky metal (131) is arranged on the lower right portion of the second dielectric layer (141), a second P-type base region (31) is arranged on the upper portion of the second P-type side wall region (41), a second P + ohmic contact region (21) is arranged on the upper right portion of the second P-type base region (31), and a second N + source region (101) is arranged on the upper left portion of the second P-type base region (31); a double-stage groove is formed in the center of the upper portion inside the N-drift region (6), a polycrystalline silicon gate (121) and a gate medium (111) filling the double-stage groove are arranged in the double-stage groove, and an N-type current expansion layer (9) is arranged below the double-stage groove; a first source metal (1) is arranged above the first P + ohmic contact region (2) and the first N + source region (10), and a first source metal (1) is arranged above the first Schottky metal (13) and on the left side of the first dielectric layer (14); a second source metal (11) is arranged above the second P + ohmic contact region (21) and the second N + source region (101), and a second source metal (11) is arranged above the second Schottky metal (131) and on the right side of the second dielectric layer (141); and a gate metal (12) is arranged above the polysilicon gate (121).
7. The method of fabricating a dual-stage trench-gate silicon carbide MOSFET according to any of claims 1 to 6, comprising the steps of:
the first step is as follows: cleaning an epitaxial wafer, and injecting aluminum ions on the N-epitaxy by taking polycrystalline silicon as an injection barrier layer to form a P + shielding layer;
the second step is that: performing secondary epitaxy and injecting aluminum ions by taking the polycrystalline silicon as an injection barrier layer to form a P-type side wall region;
the third step: carrying out third epitaxy and injecting aluminum ions to form a P-type base region;
the fourth step: injecting aluminum ions to form a P + ohmic contact region;
the fifth step: injecting nitrogen ions to form an N + source region and activating and annealing;
and a sixth step: etching the gate groove;
the seventh step: injecting nitrogen ions by taking the polycrystalline silicon as an injection barrier layer to form an N-type current expansion layer;
eighth step: oxidizing dry oxygen to generate a gate oxide layer, then annealing and depositing polycrystalline silicon in a nitrogen atmosphere, and patterning the polycrystalline silicon;
the ninth step: and depositing and etching metal to form the electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116884997A (en) * | 2023-09-07 | 2023-10-13 | 珠海格力电子元器件有限公司 | Insulated gate bipolar transistor and preparation method thereof |
| CN116895699A (en) * | 2023-09-08 | 2023-10-17 | 成都蓉矽半导体有限公司 | Cascade trench MOSFET with heterojunction and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116884997A (en) * | 2023-09-07 | 2023-10-13 | 珠海格力电子元器件有限公司 | Insulated gate bipolar transistor and preparation method thereof |
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| CN116895699A (en) * | 2023-09-08 | 2023-10-17 | 成都蓉矽半导体有限公司 | Cascade trench MOSFET with heterojunction and preparation method |
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| CN117855253A (en) * | 2024-02-22 | 2024-04-09 | 深圳天狼芯半导体有限公司 | Shielding grid MOS device, preparation method thereof and chip |
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