CN115425064A - High-reliability silicon carbide MOSFET device integrated with reverse SBD and preparation method - Google Patents

High-reliability silicon carbide MOSFET device integrated with reverse SBD and preparation method Download PDF

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CN115425064A
CN115425064A CN202211125637.4A CN202211125637A CN115425064A CN 115425064 A CN115425064 A CN 115425064A CN 202211125637 A CN202211125637 A CN 202211125637A CN 115425064 A CN115425064 A CN 115425064A
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contact
region
shield
source electrode
area
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李轩
吴阳阳
李凌峰
赵汉青
邓小川
张波
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University of Electronic Science and Technology of China
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Abstract

The invention provides a high-reliability silicon carbide MOSFET integrated with reverse SBD and a preparation method thereof, wherein the preparation method comprises the following steps: the device comprises an N-type substrate, an N-type epitaxial layer, a P + shield area, schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body area, a P + contact area, an N + contact area and a drain electrode; according to the silicon carbide MOSFET device, the P + shield area with self-regulated potential is formed in the device body, on the premise that the conduction capability of the device is not reduced, the gate oxide layer is protected, the blocking capability of the device is enhanced, when the device is in short circuit, the JFET area is clamped off by the PN junction depletion area formed by the P + shield area and the N-type epitaxial layer, the saturation current of the device in short circuit is reduced, and the short circuit capability of the device is improved.

Description

High-reliability silicon carbide MOSFET device integrated with reverse SBD and preparation method
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a high-reliability silicon carbide MOSFET device integrated with a reverse SBD and a preparation method thereof.
Background
As one of the representatives of the third generation wide bandgap semiconductor materials, silicon Carbide (Silicon Carbide) materials have the advantages of wider bandgap width (3 times), higher critical electric field (10 times), higher carrier saturation drift velocity (2 times), higher thermal conductivity (2.5 times) and the like than Silicon materials, are excellent materials for preparing high-voltage power electronic devices, and have wide application prospects in the fields of high-power, high-temperature, high-voltage and anti-irradiation power electronics.
MOSFETs are one of the most widely used gate-controlled device structures in silicon carbide power devices. The silicon carbide MOSFET is a device characterized by a single-pole transport working mechanism, has no charge storage effect, has lower switching loss and higher frequency characteristic compared with a bipolar device, and simultaneously has low on-resistance and excellent high-temperature characteristic, so that the silicon carbide MOSFET becomes a new generation of extremely competitive low-loss power device.
In the operation process of a power electronic system, the situation that the device bears high voltage and passes large current at the same time can occur due to the fact that the device is switched on by mistake or a load fault occurs, namely the device is short-circuited, and at the moment, the current passing through the device rapidly reaches saturated current. The control is completely lost when the device is in short circuit, so that the device is easy to cause secondary damage, the direct reason of the failure of the device is difficult to determine, and the continuous short circuit state after the failure of the device can cause damage to the whole system. If the silicon carbide MOSFET is turned off by the protection circuit after short circuit, even if the device does not fail, the electrical characteristics of the device can be seriously degraded, and the service life and the reliability of the device are greatly reduced.
When the device is short-circuited, compared with a silicon-based device of the same quantity level, the silicon carbide MOSFET bears stronger electrothermal stress in a short-circuit state due to smaller chip area and larger current density. Thus, the need for short circuit protection designs for silicon carbide MOSFETs is more pressing. Improving the short-circuit reliability of the silicon carbide MOSFET and prolonging the short-circuit endurance time of the device are usually achieved by reducing the saturation current of the device, but reducing the saturation current of the device increases the on-resistance of the device and sacrifices the forward conduction capability of the device.
And when the device is voltage-resistant, a higher peak electric field exists at the gate dielectric, and the reliability of the gate dielectric layer is possibly reduced due to long-time operation.
Disclosure of Invention
The invention aims to provide a high-reliability silicon carbide MOSFET device integrated with a reverse SBD, wherein a P + shield area connected with a source electrode through a Schottky contact is introduced below a gate medium, according to different working modes of the device, the potential difference between the P + shield area and Schottky contact metal is changed under the control of drain voltage, namely, an SBD pointing to the Schottky contact metal from the P + shield area is integrated in the device body, under the control of the SBD, the P + shield area can be switched between a grounding state and a floating state, and the high-reliability silicon carbide MOSFET device integrated with the reverse SBD can enhance the reliability of the gate medium layer of the device, increase the breakdown voltage of the device, reduce the saturation current of the device when short circuit occurs, improve the short circuit tolerance time of the device and enhance the short circuit reliability of the device on the basis of not sacrificing the conduction capability of the original MOSFET and increasing the conduction resistance of the device.
In order to realize the purpose of the invention, the technical scheme of the invention is as follows:
a high reliability silicon carbide MOSFET device integrated with an inverted SBD, comprising: the Schottky barrier diode comprises an N-type substrate 10, an N-type epitaxial layer 9 located above the N-type substrate 10, a P + shield region 8 located in the N-type epitaxial layer 9, schottky contact metal 3 located above the P + shield region 8 and forming Schottky contact with the P + shield region 8, a source electrode 1 located above the Schottky contact metal 3, a gate dielectric 7 located above the P + shield region 8 and a polysilicon gate 2 inside the gate dielectric 7, a P-body region 6 located above the N-type epitaxial layer 9, a P + contact region 4 and an N + contact region 5 located above the P-body region 6 and forming ohmic contact with the source electrode 1, a drain electrode 11 located below the N-type substrate 10 and forming ohmic contact with the N-type substrate 10, wherein the P + contact region 4 and the N + contact region 5 are located on two sides of the gate dielectric 7 and below the source electrode 1.
Preferably, the source electrode 1 is T-shaped, and includes a horizontal source electrode segment above the P + contact region 4 and the N + contact region 5, and a vertical source electrode segment between the gate dielectrics 7, the horizontal source electrode segment 1 forms ohmic contact with the P + contact region 4 and the N + contact region 5, and the vertical source electrode segment 1 is connected to the schottky contact metal 3.
Preferably, a schottky contact exists between the P + shield region 8 and the schottky contact metal 3 to form a schottky diode, and the direction of the schottky diode is from the P + shield region 8 to the schottky contact metal 3.
Preferably, the gate dielectric 7 is SiO 2 Or a high K dielectric.
Preferably, each doping type in the device is correspondingly changed into opposite doping, namely, the P-type doping is changed into the N-type doping, and meanwhile, the N-type doping is changed into the P-type doping.
The invention also provides a preparation method of the high-reliability silicon carbide MOSFET device integrated with the reverse SBD, which comprises the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-type epitaxial layer by taking the oxide layer as an injection barrier layer to form a P-body region;
the second step is that: injecting nitrogen ions to form an N + contact region by taking the oxide layer as an injection barrier layer;
the third step: injecting aluminum ions to form a P + contact region by taking the oxide layer as an injection barrier layer and activating and annealing;
the fourth step: etching a groove;
the fifth step: injecting aluminum ions into the bottom of the trench by taking the oxide layer as an injection barrier layer to form a P + shield area;
and a sixth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the seventh step: depositing polycrystalline silicon and etching the polycrystalline silicon;
eighth step: isolating the polysilicon by wet oxygen oxidation;
the ninth step: depositing ohmic contact metal on the source electrode and sintering at the temperature of over 700 ℃;
the tenth step: etching the gate oxide at the bottom of the trench;
the eleventh step: depositing Schottky contact metal at the bottom of the groove and sintering at the temperature below 500 ℃;
a twelfth step: and depositing and etching the source electrode, the drain electrode and the grid electrode metal to form an ohmic contact electrode.
The invention also provides a second high-reliability silicon carbide MOSFET device integrated with the reverse SBD, which comprises an N-type substrate 10, a P + shield region 8 arranged on two sides in an N-type epitaxial layer 9,N epitaxial layer 9 positioned above the N-type substrate 10, schottky contact metal 3 forming Schottky contact with the P + shield region 8 arranged on the P + shield region 8, a source electrode 1 comprising a horizontal section and vertical sections on two sides, a vertical section of a source electrode 1 arranged above the Schottky contact metal 3, a horizontal section of the source electrode 1 positioned above the P + contact region 4 and the N + contact region 5, a gate medium 7 comprising a middle gate medium and two side gate mediums, two side gate mediums arranged above the P + shield region 8 and on two sides of the vertical section of the source electrode 1, the middle gate medium positioned in the middle of the N-type epitaxial layer 9 and below the horizontal section of the source electrode 1, a polysilicon gate 2 arranged in the middle gate medium, a P-body 6 arranged above the N-type epitaxial layer 9 between the two side gate mediums and the middle gate medium, a P-body contact region 326 arranged above the N-type epitaxial layer 9, and an ohmic contact region 3262 formed with the P + shield region and the N + substrate 3210.
The invention also provides a third high-reliability silicon carbide MOSFET device integrated with the reverse SBD, which comprises an N-type substrate 10, a P + contact region 4 arranged on the left side above the inside of an N-type epitaxial layer 9,N epitaxial layer 9 positioned above the N-type substrate 10, a P + shield region 8 arranged on the right side, a gate medium 7 arranged in the middle, a polysilicon gate 2 arranged in the gate medium, a P + shield region 8 in contact with the bottom and the right side of the gate medium 7, an N + contact region 5 arranged between the P + contact region 4 and the gate medium 7, a P-body region 6,P + contact region 4, an N + contact region 5, a gate medium 7 and a P + shield region 8 below the N + contact region 5, a Schottky contact metal 3 forming a Schottky contact with the P + shield region 8 arranged above the source electrode 1 and the P + shield region 8, and the Schottky contact metal 3 positioned below the source electrode 1;
a drain electrode 11 which forms ohmic contact with the N-type substrate 10 is arranged below the N-type substrate 10.
The device material is SiC material, and can also be other semiconductor materials.
The polycrystalline silicon end of the device is a grid electrode, the bottom end of the N + substrate is a drain electrode, and the N + contact area and the P + contact area are source electrodes.
The invention has the beneficial effects that: 1: when the device works in a conducting state, because the potential of the P + shield area is low, the SBD consisting of the P + shield area and Schottky contact metal is not started, the P + shield area is floated, and the PN junction depletion area formed by the P + shield area and the N-type epitaxial layer has little influence on the resistance of the JFET area; 2: when the device works in a blocking state, the potential of the P + shield area is increased until the SBD is started, and the P + shield area is connected with the source electrode and grounded, so that the electric field of a gate oxide layer can be effectively shielded, and the gate oxide reliability of the silicon carbide MOSFET device is improved; 3: when a short circuit occurs, the potential of the P + shield area is increased until the SBD is started, the P + shield area is grounded at the moment, the temperature of the device is rapidly increased when the short circuit occurs, the Schottky barrier is reduced, the potential of the P + shield area is further reduced, a PN junction depletion area formed by the P + shield area and the N-type epitaxial layer is expanded, the conduction path of current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.
Drawings
FIG. 1 is a conventional trench-gate silicon carbide MOSFET;
FIG. 2 is a schematic view of the device structure of embodiment 1 of the present invention;
fig. 3 is a schematic view of an epitaxial wafer cleaned and an oxide layer is used as an implantation barrier layer on an N-type epitaxial layer to implant aluminum ions to form a P-body region in the manufacturing method in embodiment 1 of the present invention;
fig. 4 is a schematic view of an N + contact region formed by implanting nitrogen ions using an oxide layer as an implantation barrier layer in the manufacturing method of embodiment 1 of the present invention;
fig. 5 is a schematic view of implanting aluminum ions to form a P + contact region and activating annealing by using an oxide layer as an implantation barrier layer in the manufacturing method of embodiment 1 of the present invention;
FIG. 6 is a schematic diagram of a trench etched in the manufacturing method of embodiment 1 of the present invention;
fig. 7 is a process of implanting aluminum ions into the bottom of the trench to form a P + shield region by using the oxide layer as an implantation barrier layer in the manufacturing method of embodiment 1 of the present invention;
FIG. 8 is a schematic diagram of a gate oxide layer formed by dry oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide layer in the manufacturing method of example 1 of the present invention;
fig. 9 is a schematic view of depositing polycrystalline silicon and etching the polycrystalline silicon in the manufacturing method in embodiment 1 of the present invention;
FIG. 10 is a schematic view of the wet oxygen oxidation isolation of polysilicon in the production process in example 1 of the present invention;
FIG. 11 is a schematic view showing that ohmic contact metal is deposited on a source electrode and sintered at a high temperature in the manufacturing method of example 1 of the present invention;
FIG. 12 is a schematic diagram showing etching of trench bottom gate oxide in the manufacturing method according to embodiment 1 of the present invention;
FIG. 13 is a schematic view showing the deposition of Schottky contact metal on the bottom of the trench and the low-temperature sintering in the manufacturing method of example 1;
FIG. 14 is a schematic diagram of the source, drain and gate metals deposited and etched to form ohmic contact electrodes in the manufacturing method of embodiment 1 of the present invention;
FIG. 15 is a schematic view of the device structure of embodiment 2 of the present invention;
fig. 16 is a schematic view of the device structure of embodiment 3 of the present invention.
The structure comprises a source electrode 1, a polysilicon gate 2, schottky contact metal 3, a P + contact region 4, an N + contact region 5, a P-body region 6, a gate dielectric 7, a P + shield region 8, an N-type epitaxial layer 9, an N-type substrate 10 and a drain 11.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1:
as shown in fig. 2, a high-reliability sic MOSFET device integrated with an inverted SBD of the present embodiment includes an N-type substrate 10, an N-type epitaxial layer 9 located above the N-type substrate 10, a P + shield region 8 located in the N-type epitaxial layer 9, a schottky contact metal 3 located above the P + shield region 8 and forming a schottky contact with the P + shield region 8, a source electrode 1 located above the schottky contact metal 3, a gate dielectric 7 located above the P + shield region 8 and a polysilicon gate 2 inside the gate dielectric 7, a P-body region 6 located above the N-type epitaxial layer 9, a P + contact region 4 and an N + contact region 5 located above the P-body region 6 and forming an ohmic contact with the source electrode 1, and a drain electrode 11, a P + contact region 4 and an N + contact region 5 located below the N-type substrate 10 and forming an ohmic contact with the N-type substrate 10, which are located on two sides of the gate dielectric 7 and below the source electrode 1.
The source electrode 1 is T-shaped and comprises a source electrode horizontal section above a P + contact area 4 and an N + contact area 5 and a source electrode vertical section between the gate dielectrics 7, the source electrode 1 horizontal section forms ohmic contact with the P + contact area 4 and the N + contact area 5, and the source electrode 1 vertical section is connected with the Schottky contact metal 3.
And a P + shield region 8 is arranged below the Schottky contact metal 3 and the gate dielectric 7 and in the N-type epitaxial layer 9. Schottky contact exists between the P + shield region 8 and the schottky contact metal 3 to form a schottky diode, and the direction of the schottky diode is from the P + shield region 8 to the schottky contact metal 3.
The working principle of the embodiment is as follows:
when the device works in an on state, the SBD between the P + shield region 8 and the Schottky contact metal is not opened, the P + shield region 8 is floated, and the PN junction depletion region formed by the P + shield region 8 and the N-type epitaxial layer 9 has little influence on the resistance of the JFET region.
When the device works in a blocking state, the SBD between the P + shield area 8 and the Schottky contact metal is opened, and at the moment, the P + shield area 8 is grounded, so that the electric field born by the gate dielectric 7 is alleviated, and the gate oxide reliability of the silicon carbide MOSFET device is improved.
When a short circuit occurs, the potential of the P + shield area is increased until the SBD is started, the P + shield area is grounded at the moment, the temperature of the device is rapidly increased when the short circuit occurs, the Schottky barrier is reduced, the potential of the P + shield area is further reduced, a PN junction depletion area formed by the P + shield area and the N-type epitaxial layer is expanded, the conduction path of current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.
As shown in fig. 3 to fig. 14, the present embodiment further provides a method for manufacturing a high-reliability silicon carbide MOSFET device integrated with an inverted SBD, including the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-type epitaxial layer by taking the oxide layer as an injection barrier layer to form a P-body region;
the second step: injecting nitrogen ions to form an N + contact region by taking the oxide layer as an injection barrier layer;
the third step: injecting aluminum ions to form a P + contact region by taking the oxide layer as an injection barrier layer and activating and annealing;
the fourth step: etching a groove;
the fifth step: injecting aluminum ions into the bottom of the trench by taking the oxide layer as an injection barrier layer to form a P + shield area;
and a sixth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the seventh step: depositing polycrystalline silicon and etching the polycrystalline silicon;
eighth step: isolating the polysilicon by wet oxygen oxidation;
the ninth step: depositing ohmic contact metal on the source electrode and sintering at the temperature of over 700 ℃;
the tenth step: etching the gate oxide at the bottom of the trench;
the eleventh step: depositing Schottky contact metal at the bottom of the groove and sintering at the temperature below 500 ℃;
the twelfth step: and depositing and etching the source electrode, the drain electrode and the grid electrode metal to form an ohmic contact electrode.
Example 2:
as shown in fig. 15, the present embodiment provides a high-reliability silicon carbide MOSFET device integrated with an inverted SBD, which includes an N-type substrate 10, and a P + shield region 8 disposed on two sides of an N-type epitaxial layer 9,N epitaxial layer 9 disposed on the N-type substrate 10, a schottky contact metal 3 forming a schottky contact with the P + shield region 8 disposed on the P + shield region 8, a source electrode 1 includes a horizontal section and vertical sections on two sides, a vertical section of the source electrode 1 is disposed above the schottky contact metal 3, the horizontal section of the source electrode 1 is disposed above the P + contact region 4 and the N + contact region 5, a gate dielectric 7 includes a middle gate dielectric and two side gate dielectrics, the two side gate dielectrics are disposed above the P + shield region 8 and on two sides of the vertical section of the source electrode 1, the middle gate dielectric is disposed in the middle of the N-type epitaxial layer 9, the horizontal section of the source electrode 1, the middle gate dielectric is disposed inside the middle gate dielectric, a P-body contact region 6 is disposed above the N-type epitaxial layer 9 between the two side gate dielectrics, and the P-body contact region 326 is disposed below the N + substrate 324 and the N + substrate 3210 to form an ohmic contact with the P + substrate 3211.
The source electrode 1 is connected with the Schottky contact metal 3, a P + shield region 8 is arranged below the Schottky contact metal 3 and the gate dielectric 7 and in the N-type epitaxial layer 9, schottky contact is arranged between the P + shield region 8 and the Schottky contact metal 3 to form a Schottky diode, and the direction of the Schottky diode is from the P + shield region 8 to the Schottky contact metal 3. When the device works in a conducting state, the SBD between the P + shield region 8 and the Schottky contact metal is not started, the P + shield region 8 is floated, and a PN junction depletion region formed by the P + shield region 8 and the N-type epitaxial layer 9 has little influence on the resistance of the JFET region; when the device works in a blocking state, the SBD between the P + shield region 8 and the Schottky contact metal is started, and at the moment, the P + shield region 8 is grounded, so that the electric field borne by the gate dielectric 7 is alleviated, and the gate oxide reliability of the silicon carbide MOSFET device is improved; when a short circuit occurs, the potential of the P + shield area is increased until the SBD is started, the P + shield area is grounded at the moment, the temperature of the device is rapidly increased when the short circuit occurs, the Schottky barrier is reduced, the potential of the P + shield area is further reduced, a PN junction depletion area formed by the P + shield area and the N-type epitaxial layer is expanded, the conduction path of current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.
In this example, compared to example 1: and a split gate structure is not needed, namely, the polysilicon gate 2 is not needed to be split, so that the process difficulty is reduced.
Example 3:
as shown in fig. 16, this embodiment provides a high-reliability sic MOSFET device integrated with an inverted SBD, which includes an N-type substrate 10, an N-type epitaxial layer 9,N over the N-type substrate 10, a P + contact region 4 disposed on the left side of the inside of the N-type epitaxial layer 9,N epitaxial layer 9, a P + shield region 8 disposed on the right side of the inside of the N-type epitaxial layer, a gate dielectric 7 disposed in the middle of the inside of the gate dielectric, a polysilicon gate 2 disposed in the gate dielectric, a P + shield region 8 contacting the bottom and the right side of the gate dielectric 7, an N + contact region 5 disposed between the P + contact region 4 and the gate dielectric 7, a P-body region 6,P + contact region 4, an N + contact region 5 disposed below the N + contact region 5, a schottky contact metal 3 disposed above the gate dielectric 7 and the P + shield region 8 and forming a schottky contact with the P + shield region 8, and the schottky contact metal 3 disposed below the source electrode 1;
a drain electrode 11 which forms ohmic contact with the N-type substrate 10 is arranged below the N-type substrate 10.
The source electrode 1 is connected with the Schottky contact metal 3, schottky contact exists between the P + shield area 8 and the Schottky contact metal 3 to form a Schottky diode, and the direction of the Schottky diode is from the P + shield area 8 to the Schottky contact metal 3. When the device works in a conducting state, the SBD between the P + shield region 8 and the Schottky contact metal is not started, the P + shield region 8 is floated, and a PN junction depletion region formed by the P + shield region 8 and the N-type epitaxial layer 9 has little influence on the resistance of the JFET region; when the device works in a blocking state, the SBD between the P + shield region 8 and the Schottky contact metal is started, and at the moment, the P + shield region 8 is grounded, so that the electric field borne by the gate dielectric 7 is alleviated, and the gate oxide reliability of the silicon carbide MOSFET device is improved; when a short circuit occurs, the potential of the P + shield area is increased until the SBD is started, the P + shield area is grounded at the moment, the temperature of the device is rapidly increased when the short circuit occurs, the Schottky barrier is reduced, the potential of the P + shield area is further reduced, a PN junction depletion area formed by the P + shield area and the N-type epitaxial layer is expanded, the conduction path of current is narrowed, the short-circuit current is reduced, and the short-circuit reliability of the device is improved.
This example compares with example 1: in the embodiment, a P-shield region 8 is formed between two adjacent trenches, and a PN junction depletion region formed by the P-shield region 8, the P + contact region 4 and the N-type epitaxial layer expands to protect an oxide layer, so that the short-circuit peak current density is reduced.

Claims (8)

1. A high reliability silicon carbide MOSFET device integrated with an inverted SBD, comprising: the Schottky barrier diode comprises an N-type substrate (10), an N-type epitaxial layer (9) located above the N-type substrate (10), a P + shield region (8) located in the N-type epitaxial layer (9), schottky contact metal (3) located above the P + shield region (8) and forming Schottky contact with the P + shield region (8), a source electrode (1) located above the Schottky contact metal (3), a gate medium (7) and a polysilicon gate (2) inside the gate medium (7) located above the P + shield region (8), a P-body region (6) located above the N-type epitaxial layer (9), a P + contact region (4) and an N + contact region (5) located above the P-body region (6) and forming ohmic contact with the source electrode (1), a drain electrode (11) located below the N-type substrate (10) and forming ohmic contact with the N-type substrate (10), wherein the P + contact region (4) and the N + contact region (5) are located on two sides of the gate medium (7), and the source electrode (1) is located below the P + contact region (4).
2. The integrated inverted SBD high reliability silicon carbide MOSFET device of claim 1, wherein: the source electrode (1) is T-shaped and comprises a source electrode horizontal section above a P + contact area (4) and an N + contact area (5) and a source electrode vertical section between grid mediums (7), the source electrode horizontal section, the P + contact area (4) and the N + contact area (5) form ohmic contact, and the source electrode vertical section (1) is connected with Schottky contact metal (3).
3. The integrated inverted SBD high reliability silicon carbide MOSFET device according to claim 1, wherein: and a Schottky contact exists between the P + shield region (8) and the Schottky contact metal (3) to form a Schottky diode, and the direction of the Schottky diode is from the P + shield region (8) to the Schottky contact metal (3).
4. An integrated inverted SBD high reliability silicon carbide MOSFET device as claimed in any one of claims 1 to 3, wherein: the gate dielectric (7) is SiO 2 Or a high K dielectric.
5. An integrated inverted SBD high reliability silicon carbide MOSFET device as claimed in any one of claims 1 to 3 wherein: the doping types in the device are correspondingly changed into opposite doping, namely P-type doping is changed into N-type doping, and simultaneously N-type doping is changed into P-type doping.
6. The method for preparing the integrated reverse SBD high-reliability silicon carbide MOSFET device according to any one of claims 1 to 3, comprising the following steps:
the first step is as follows: cleaning the epitaxial wafer, and injecting aluminum ions on the N-type epitaxial layer by taking the oxide layer as an injection barrier layer to form a P-body region;
the second step: injecting nitrogen ions to form an N + contact region by taking the oxide layer as an injection barrier layer;
the third step: injecting aluminum ions to form a P + contact region by taking the oxide layer as an injection barrier layer and activating and annealing;
the fourth step: etching the groove;
the fifth step: injecting aluminum ions into the bottom of the trench by taking the oxide layer as an injection barrier layer to form a P + shield area;
and a sixth step: generating a gate oxide layer by dry oxygen oxidation, annealing in a nitrogen atmosphere and patterning the gate oxide;
the seventh step: depositing polycrystalline silicon and etching the polycrystalline silicon;
eighth step: isolating the polysilicon by wet oxygen oxidation;
the ninth step: depositing ohmic contact metal on the source electrode and sintering at the temperature of more than 700 ℃;
the tenth step: etching the gate oxide at the bottom of the trench;
the eleventh step: depositing Schottky contact metal at the bottom of the groove and sintering at the temperature below 500 ℃;
the twelfth step: and depositing and etching the source electrode, the drain electrode and the grid electrode metal to form an ohmic contact electrode.
7. A high reliability carborundum MOSFET device of integrated reverse SBD which characterized in that:
the Schottky contact source comprises an N-type substrate (10), an N-type epitaxial layer (9) located above the N-type substrate (10), P + shield regions (8) are arranged on two sides in the N-type epitaxial layer (9), schottky contact metal (3) forming Schottky contact with the P + shield regions (8) is arranged above the P + shield regions (8), a source electrode (1) comprises horizontal sections and vertical sections on two sides, a vertical section of the source electrode (1) is arranged above the Schottky contact metal (3), the horizontal sections of the source electrode (1) are located above a P + contact region (4) and an N + contact region (5), a gate medium (7) comprises a middle gate medium and two side gate mediums, the two side gate mediums are located above the P + shield regions (8), two sides of the vertical section of the source electrode (1), the middle gate medium is located in the N-type epitaxial layer (9), the lower part of the horizontal section of the source electrode (1), polysilicon gates (2) are arranged inside the middle gate medium, the upper part of the N-type epitaxial layer (9) between the middle gate medium and the N-type epitaxial layer (6) is arranged above the P + contact region (10), and the ohmic contact region (5) and the P + contact region (10) is formed below the N-type substrate (10).
8. A high reliability carborundum MOSFET device of integrated reverse SBD which characterized in that: the Schottky contact structure comprises an N-type substrate (10) and an N-type epitaxial layer (9) located above the N-type substrate (10), wherein a P + contact area (4) is arranged on the left side of the upper portion inside the N-type epitaxial layer (9), a P + shield area (8) is arranged on the right side of the upper portion inside the N-type epitaxial layer, a gate dielectric (7) is arranged in the middle of the upper portion, a polysilicon gate (2) is arranged inside the gate dielectric, the P + shield area (8) is in contact with the bottom and the right side of the gate dielectric (7), an N + contact area (5) is arranged between the P + contact area (4) and the gate dielectric (7), a P-body area (6) below the N + contact area (5), a source electrode (1) is arranged above the P + shield area (8), schottky contact metal (3) which forms Schottky contact with the P + shield area (8) is arranged above the P + shield area (8), and the Schottky contact metal (3) is located below the source electrode (1);
a drain electrode (11) which forms ohmic contact with the N-type substrate (10) is arranged below the N-type substrate (10).
CN202211125637.4A 2022-09-16 2022-09-16 High-reliability silicon carbide MOSFET device integrated with reverse SBD and preparation method Pending CN115425064A (en)

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