CN114709255A - Heterojunction-based high-power-density tunneling semiconductor device and manufacturing process thereof - Google Patents
Heterojunction-based high-power-density tunneling semiconductor device and manufacturing process thereof Download PDFInfo
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/1608—Silicon carbide
Abstract
The invention discloses a high power density tunneling semiconductor device based on heterojunction and a manufacturing process thereof, wherein a device cellular structure comprises: the N + substrate is provided with drain metal below and an N-drift region above; the N-drift region is symmetrically provided with a pair of grooves, the bottom of the groove is provided with a P + region, a graphene source region is arranged in the groove, source metal is arranged on the graphene source region, a gate dielectric layer partially overlapped with the graphene source region is arranged on the N-drift region, a polysilicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polysilicon gate, and the graphene source region and the N-drift region form a heterojunction. The device structure has low requirement on an injection process, small cell size and a large number of cells in unit area, greatly improves the power density of the device, effectively reduces the specific on-resistance and the sub-threshold swing of the device, simplifies the manufacturing process and reduces the cost of the device. When the device is reversely biased and resistant to voltage, the electric field peak value is transferred from the heterojunction boundary to the PN junction boundary by the P + region, so that the avalanche capability of the device is improved, and the breakdown voltage is increased.
Description
Technical Field
The invention mainly relates to the field of high-voltage power semiconductor devices, in particular to a heterojunction-based high-power density tunneling semiconductor device and a manufacturing process thereof, which are suitable for the application field of coexistence of extreme environments such as high temperature, high frequency, high power, strong radiation and the like, such as automotive electronics, rail transit, photovoltaic inversion, aerospace, aviation, oil exploration, nuclear energy, radar, communication and the like.
Background
The power semiconductor device plays a very important role in the power electronic industry and has wide application in automobiles, household appliances, high-speed rails and power grids. However, the conventional power device has many disadvantages, such as: large cell size, large on-resistance, high interface state density, complex manufacturing process, damage to the semiconductor surface caused by doping process, etc.
The conduction band and the valence band of the graphene material are symmetrical, and intersect at the top point of the Brillouin zone, namely one point on the Fermi surface, so that the graphene material has an obvious controllable electronic band gap. According to the characteristic of energy band symmetry of the graphene material, the energy band symmetry can be broken by doping or applying an external field, so that the band gap is opened, and the size of the band gap can be controlled. The graphene material has the characteristics of a semiconductor energy band and has the characteristic of high metal conductivity. The graphene material has the characteristics of high mobility, high thermal conductivity, strong high-temperature stability, large-area manufacturing and the like, and meets the requirements of power semiconductor devices.
Shown in fig. 1 is a conventional silicon carbide power semiconductor device comprising: the semiconductor device comprises an N + type substrate 1, wherein one side of the N + type substrate 1 is connected with drain metal 10, the other side of the N + type substrate 1 is provided with an N-type drift region 2, a pair of P-type base regions 3, an N + type source region 5 and a P + type body contact region 4 are symmetrically arranged in the N-type drift region 2, the surface of the N-type drift region 2 is provided with a gate oxide layer 8, the surface of the gate oxide layer 8 is provided with a polysilicon gate 9, a passivation layer 6 is arranged above the polysilicon gate 9, and the N + type source region 5 and the P + type body contact region 4 are connected with source metal 7. The working principle of the conventional silicon carbide power semiconductor device is that when a sufficiently large positive voltage is applied to a polysilicon gate, an inversion channel is generated at the interface of a P-type base region 3 and a gate oxide layer 8, and electrons can be injected into an N-type drift region 2 from an N + type source region 5 through the channel. The P-type base region 3 and the N + type source region 5 need to be doped to form, however, the cell size of the silicon carbide device is limited by the doping process and the JFET region width, so that the limit of the cell width is 4-6um, and the cell width cannot be further reduced, thereby affecting the cell density of the device and the forward current capability of the device. In addition, the ion implantation process of the silicon carbide material can also cause surface damage of the N-type drift region 2, so that a large number of interface state traps exist on the surface of the N-type drift region 2, the effective mobility of an inversion channel carrier is small, and the on-resistance is high. Meanwhile, the traditional semiconductor device is based on a carrier thermal injection working mechanism, and the minimum subthreshold swing amplitude can only reach 60mV/decade at normal temperature. Therefore, it is urgently needed to provide a new power device with high channel electron mobility and high power density.
Disclosure of Invention
The invention provides a high-power-density tunneling semiconductor device based on a heterojunction and a manufacturing process thereof, aiming at the problems. When positive voltage is applied to the grid electrode, the Fermi level of the graphene is moved upwards to enter a conduction band, meanwhile, the electron concentration of the N-type drift region is increased to form an accumulation layer, at the moment, the width of a heterojunction barrier is narrowed, a band-band tunneling effect occurs, and the electron tunnel of the valence band of the graphene penetrates through the heterojunction barrier to enter the conduction band of the N-type drift region.
Meanwhile, the size of the unit cell of the device is smaller than that of the unit cell of the conventional silicon carbide power device, the number of the unit cells is greatly increased in unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
The invention adopts the following technical scheme: a heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure and a manufacturing process thereof,
the transistor comprises an N + substrate, a drain metal arranged below the N + substrate, and an N-drift region arranged above the N + substrate; the tunneling junction field effect transistor is characterized in that a pair of graphene source regions arranged at intervals is arranged above the N-drift region, source metal is arranged on the graphene source regions, a gate dielectric layer partially overlapped with the graphene source regions is arranged on the N-drift region, a polycrystalline silicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polycrystalline silicon gate, the polycrystalline silicon gate is flush with the gate dielectric layer, the polycrystalline silicon gate and the source metal are arranged at intervals, a heterojunction is formed at the contact position of the graphene source regions and the N-drift region, triple contact surfaces are formed among the graphene source regions, the N-type region drift region and the gate dielectric layer, and tunneling effect occurs at the triple contact surfaces.
Furthermore, two spaced grooves are formed in the upper surface of the N-type drift region, the graphene source region is arranged in the grooves, and a P + type region is arranged in the N-type drift region below the graphene source region.
Furthermore, the graphene source region is arranged on the upper surface of the N-type drift region, and a P + type region is arranged in the N-type drift region below the graphene source region.
Further, the graphene source region is arranged on the upper surface of the N-type drift region.
Furthermore, two spaced grooves are formed in the upper surface of the N-type drift region, and the graphene source region is arranged in the grooves.
Furthermore, a P + type region is arranged in the N-type drift region below the graphene source region, a second P + type region is arranged in the N-type drift region below the gate dielectric layer, and a certain distance is reserved between the second P + type region and the graphene source region.
Further, the N + type substrate and the N-type drift region are not limited by materials, silicon carbide, gallium oxide, silicon, diamond or other materials capable of forming a heterojunction tunneling power semiconductor device substrate and a drift region can be used, and the doping concentrations of the N + type substrate and the N-type drift region are also not limited.
Further, the graphene source region is not limited by materials, and graphene, molybdenum disulfide, polysilicon, metal or other materials capable of forming the heterojunction tunneling power semiconductor device source region can be used.
Further, the thickness of the gate dielectric layer is not limited, and the gate dielectric layer is not limited by materials, and silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or other materials capable of forming the gate dielectric layer of the heterojunction tunneling power semiconductor device can be used.
A manufacturing method of a heterojunction-based high-power-density tunneling semiconductor device comprises the following steps:
step 1: attaching silicon carbide on a surface of an N + type substrate to form an N-type drift region;
step 2: forming a groove on the surface of the N-type drift region by using an etching process;
and step 3: forming a P + type shielding layer at the bottom of the groove by using a doping process;
and 4, step 4: forming a graphene source region on the bottom of the groove;
and 5: forming a gate dielectric layer on the upper surface of the N-type drift region by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer by using a deposition process and forming a polysilicon gate;
and 7: forming an isolation passivation layer above the polysilicon gate by using a deposition process;
and step 8: and finally, forming source metal on the upper surface of the graphene source region, and manufacturing drain metal on the other surface of the N + type substrate.
The source electrode of the device adopts a graphene material, and voltage is applied through the grid electrode, so that lower subthreshold swing and higher on-state current characteristic are obtained.
The principle is as follows: when a positive voltage with a sufficient magnitude is applied to the gate, a large amount of electrons are accumulated at the interface of the N-type drift region and the gate oxide layer, the resistance of a channel region is reduced, and the energy band of the N-type drift region below the gate is lowered, the barrier width of a heterojunction is narrowed due to the lowering of the energy band of the N-type drift region, and a band-band tunneling mechanism that valence band electrons of a graphene source region pass through a forbidden band to reach a conduction band of the N-type drift region is more likely to occur, so that the power semiconductor device generates an I-V characteristic as shown in fig. 3 in an on state, wherein a current path is 11 and a depletion layer is distributed as a dotted line 10.
When a negative voltage is applied to the gate, electrons in the channel region are repelled and the electron concentration is reduced, increasing the energy band of the N-drift region under the gate. And the gaps of the conduction band and the valence band of the graphene are opened, the width of a heterojunction barrier is increased, the tunneling effect and the bipolar effect are greatly inhibited, and the power semiconductor device has smaller leakage current in an off state. At this time, the device is in a reverse withstand voltage state, and a homogeneous PN junction formed by the P + -type region and the N-type drift region is in a reverse withstand voltage state as shown in fig. 4, in which a depletion layer distribution is shown by a dotted line 10.
Compared with the prior art, the invention has the following advantages:
(1) the source electrode of the device adopts the graphene material, the conduction band and the valence band of the graphene material are symmetrical, and the graphene material is only intersected at the vertex of the Brillouin zone, namely one point on the Fermi surface, so that the device has an obvious controllable electronic band gap. According to the characteristic of graphene energy band symmetry, the energy band symmetry can be broken by doping or applying an external electric field, so that the band gap is opened, and the work function of graphene is adjustable. Thus, graphene has semiconductor energy band characteristics. When the grid is applied with zero voltage, the device is in a closed state, the intrinsic carrier concentration of the graphene is low, and a high-resistance state is presented. When positive voltage is applied to the grid electrode, the Fermi level of the graphene is moved upwards and enters a conduction band, the height of a heterojunction barrier is reduced, the width of the heterojunction barrier is narrowed, band-band tunneling effect occurs, and forward tunneling current is generated.
(2) The graphene material adopted by the source electrode of the device is low in doping concentration and almost in an intrinsic state, the graphene intrinsic carrier is in a high-resistance state when the concentration is low, and the leakage current is small when the voltage is reversely resisted.
(3) The graphene material adopted by the source electrode of the device has six times of thermal conductivity of silicon carbide and extremely thin thickness, so that the device has better heat dissipation characteristic compared with the traditional power device.
(4) When a positive voltage with enough magnitude is applied to the grid electrode, a large number of electrons can be accumulated on the interface of the N-type drift region and the grid oxide layer of the device, the resistance of a channel region is reduced, and the carrier mobility of a graphene channel is 200000 cm under the ideal state2V · s), the channel resistance is extremely low, so that the device of the present invention has excellent forward I-V characteristics in the on state.
(5) In a follow current state, the heterojunction formed by the graphene material and the N-drift region is adopted to replace a PN homojunction formed by doping of a conventional silicon carbide power semiconductor device through an ion implantation doping process, the potential barrier of the heterojunction is lower, the follow current is larger, meanwhile, the work function of the graphene can be changed through means such as doping to obtain the heterojunction diode with the adjustable potential barrier of the heterojunction, and the advantages of the device in the follow current state are further exerted.
(6) According to the device, the source electrode is made of graphene materials, the graphene materials and the N-type drift region form a heterojunction, a tunneling effect occurs under the control of grid voltage, and the channel is a triple contact surface of the graphene source electrode, the N-type drift region contact surface and the grid insulation layer. In the conventional silicon carbide MOS, due to the characteristic limitation of the silicon carbide material, the P-type base region and the N + type source electrode can be formed only by the ion implantation doping process, and then the inversion layer conductive channel is formed by the gate control. However, the ion implantation doping process may damage the surface of the N-type drift region, resulting in low electron mobility. Compared with the conventional power semiconductor device, the channel of the device is formed by the graphene and the high-concentration electron accumulation region, an electron inversion layer conducting channel is not required to be formed through an ion injection process, the surface of an N-drift region of the channel region is not damaged, the manufacturing process is greatly simplified, the cost of the device is reduced, and the number of unit cells is greatly increased in unit area.
(7) The graphene source region, the N-type region drift region and the gate dielectric layer are in contact with each other to form a triple contact surface, a tunneling effect occurs at the triple contact surface, the channel density is high, and the current capability is strong.
(8) The device is compatible with the traditional device process, and the graphene can be manufactured in a large area with low process difficulty.
(9) According to the device, a P + type region is arranged below a graphene source region, the P + type region and an N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. When the device is reverse biased and voltage-resistant, the electric field peak value in the absence of the P + type region is at the heterojunction boundary formed by the graphene source region and the N-type drift region, the reverse leakage current is large, and the breakdown voltage of the device is small. When the P + type region exists, the electric field peak value is at the PN junction boundary formed by the P + type region and the N-type drift region, so that the avalanche capability of the device is improved, the reverse bias leakage current is reduced, and the breakdown voltage of the device is increased.
Drawings
FIG. 1 is a front view of a conventional silicon carbide power semiconductor device structure;
fig. 2 is a front view of a unit cell of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a schematic diagram of a forward current path according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a reverse-state depletion layer profile according to a first embodiment of the present invention;
fig. 5 is a front view of a semiconductor device cell according to a second embodiment of the present invention;
fig. 6 is a front view of a semiconductor device cell according to a third embodiment of the present invention;
fig. 7 is a front view of a semiconductor device cell according to a fourth embodiment of the present invention;
fig. 8 is a front view of a semiconductor device cell according to a fifth embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings.
Example 1:
referring to fig. 2, a heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure, includes: the semiconductor device comprises an N + type substrate 1, drain metal 8 is connected to the lower surface of the N + type substrate 1, an N-type drift region 2 is arranged on the upper surface of the N + type substrate 1, a pair of P + type regions 9 is arranged in the N-type drift region 2, a pair of graphene source regions 3 is arranged on the upper surface of the N-type drift region 2, source metal 4 is symmetrically arranged on the upper surface of each graphene source region 3, gate dielectric layers 5 are arranged on the upper surfaces of the N-type drift region 2 and the graphene source regions 3, a polysilicon gate 6 is arranged on the upper surface of each gate dielectric layer 5, and a passivation layer 7 is arranged on the upper surface of each polysilicon gate 6. The method comprises the steps of grooving the upper surface of an N-type drift region 2 to enable the N-type drift region 2 to be divided into two parts, namely an N-type drift region 2.1 and an N-type drift region 2.2, arranging a pair of P + type regions 9 in the bottom of a groove, namely the upper surface of the N-type drift region 2.1, symmetrically arranging a pair of graphene source regions 3 in the groove in the upper surface of the N-type drift region 2, enabling a certain distance to exist between the pair of graphene source regions 3, arranging a gate dielectric layer 5 partially overlapped with the graphene source regions 3 on the N-type drift region 2.2, enabling a polysilicon gate 6 and the gate dielectric layer 5 to be flush, enabling the polysilicon gate 6 and a source electrode metal 4 to be at a certain distance, and forming a heterojunction at the contact surface of the graphene source regions 3 and the N-type drift region 2.
The invention adopts the following method to prepare:
step 1: taking an N + type substrate 1, and attaching silicon carbide on one surface of the N + type substrate 1 to form an N-type drift region 2;
step 2: forming a groove on the surface of the N-type drift region 2 by using an etching process;
and step 3: forming a P + type shielding layer 9 at the bottom of the groove by using a doping process;
and 4, step 4: forming a graphene source region 3 on the bottom of the groove;
and 5: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
and 7: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is formed on the other surface of the N + type substrate 1.
The P + type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. On the basis of keeping the breakdown voltage unchanged, the area of the heterojunction is increased through the grooving process. When positive voltage is applied to the grid electrode, the Fermi level of the graphene is moved upwards to enter a conduction band, meanwhile, the electron concentration of the N-type drift region is increased to form an accumulation layer, the width of a heterojunction barrier is narrowed, a band-band tunneling effect occurs at triple contact surfaces of the graphene source region, the N-type drift region and the grid dielectric layer, and the electron tunnel of the graphene valence band penetrates through the heterojunction barrier and enters the conduction band of the N-type drift region to form current. As shown in fig. 3, the current path 11 has a depletion layer 10 below the graphene, and does not affect the current path 11. When the device is reverse biased and voltage-resistant, the electric field peak value in the absence of the P + type region is positioned at the heterojunction boundary formed by the graphene source region and the N-type drift region, the reverse leakage current is large, and the breakdown voltage of the device is small. Referring to fig. 4, when a P + type region exists, the depletion layer 10 completely covers the graphene source region 3, an electric field of a heterojunction interface is shielded, an electric field peak value is transferred to a PN junction boundary formed by the P + type region and the N-type drift region, reverse bias leakage current is reduced, avalanche capability of a device is improved, and breakdown voltage of the device is increased. Meanwhile, the device has a simple doping process and a small doping area, so that the cell size of the device is not limited by the doping process and the JFET area, the cell size of the device is far smaller than that of a conventional silicon carbide power device, the number of cells is greatly increased in unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 2:
referring to fig. 5, a heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure, includes: the semiconductor device comprises an N + type substrate 1, wherein the lower surface of the N + type substrate 1 is connected with drain metal 8, the upper surface of the N + type substrate 1 is provided with an N-type drift region 2, the upper surface of the N-type drift region 2 is provided with a pair of P + type regions 9, the upper surface of the N-type drift region 2 is symmetrically provided with a pair of graphene source regions 3, the upper surface of each graphene source region 3 is symmetrically provided with source metal 4, the upper surfaces of the N-type drift region 2 and the graphene source regions 3 are provided with gate dielectric layers 5, the upper surface of each gate dielectric layer 5 is provided with a polysilicon gate 6, and a passivation layer 7 is arranged above each polysilicon gate 6. A pair of P + type regions 9 is arranged in the upper surface of the N-type drift region 2, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate medium 5 partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate medium layer 5, a certain distance is reserved between the polysilicon gate 6 and a source metal 4, and a heterojunction is formed at the contact surface of the graphene source regions 3 and the N-type drift region 2.
The invention adopts the following method to prepare:
step 1: taking an N + type substrate 1, and attaching silicon carbide on the other surface of the N + type substrate 1 to form an N-type drift region 2;
step 2: forming a P + type shielding layer 9 in the N-type drift region 2 by using a doping process;
and step 3: forming a graphene source region 3 on the N-type drift region 2;
and 4, step 4: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
and 5: depositing polycrystalline silicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polycrystalline silicon gate 6;
step 6: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is formed on the other surface of the N + type substrate 1.
According to the structure, on the basis of keeping breakdown voltage unchanged, a heterojunction is formed by using graphene and a silicon carbide substrate, when positive voltage is applied to a grid electrode, a Fermi level of the graphene moves upwards and enters a conduction band, meanwhile, the electron concentration of an N-type drift region rises to form an accumulation layer, the width of a heterojunction barrier potential is narrowed at the moment, a tunneling effect occurs at triple contact points of a graphene source region, the N-type drift region and a grid dielectric layer, and the electron tunnel of a graphene valence band penetrates through the heterojunction barrier and enters the conduction band of the N-type drift region. The P + type region and the N-type drift region form a PN junction, the graphene source region and the N-type drift region form a heterojunction, when the device is reverse biased and resistant to voltage, an electric field peak value in the absence of the P + type region is located at the boundary of the heterojunction formed by the graphene source region and the N-type drift region, reverse leakage current is large, and breakdown voltage of the device is small. When a P + type region exists, the electric field peak value is transferred to the PN junction boundary formed by the P + type region and the N-type drift region, so that the avalanche capability of the device is improved, the reverse bias leakage current is reduced, and the breakdown voltage of the device is increased. Meanwhile, the size of the unit cell of the device is smaller than that of the unit cell of the conventional silicon carbide power device, the number of the unit cells is greatly increased in unit area, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 3:
referring to fig. 6, a heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure, includes: the structure comprises an N + type substrate 1, drain metal 8 is connected to the lower surface of the N + type substrate 1, an N-type drift region 2 is arranged on the upper surface of the N + type substrate 1, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, source metal 4 is symmetrically arranged on the upper surface of the graphene source regions 3, gate dielectric layers 5 are arranged on the upper surfaces of the N-type drift region 2 and the graphene source regions 3, a polysilicon gate 6 is arranged on the upper surface of each gate dielectric layer 5, and a passivation layer 7 is arranged above the polysilicon gate 6. The upper surface of the N-type drift region 2 is symmetrically provided with a pair of graphene source regions 3, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and a source metal 4, and a heterojunction is formed at the contact surface of the graphene source region 3 and part of the N-type drift region 2.
The invention adopts the following method to prepare:
step 1: taking an N + type substrate 1, and attaching silicon carbide on the other surface of the N + type substrate 1 to form an N-type drift region 2;
step 2: forming a graphene source region 3 on the N-type drift region 2;
and step 3: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
and 4, step 4: depositing polycrystalline silicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polycrystalline silicon gate 6;
and 5: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is formed on the other surface of the N + type substrate 1.
A heterojunction is formed by using graphene and a silicon carbide substrate, when positive voltage is applied to a grid electrode, the Fermi level of the graphene is moved upwards to enter a conduction band, meanwhile, the electron concentration of an N-type drift region is increased to form an accumulation layer, the potential barrier width of the heterojunction is narrowed, band-band tunneling effect occurs at triple contact points of a graphene source region, the drift region of the N-type region and a grid dielectric layer, and the electron tunnel of the valence band of the graphene penetrates through the heterojunction barrier to enter the conduction band of the N-type drift region.
Meanwhile, the three-port power device can be formed without an injection doping process in the embodiment, and the cell size of the device is not limited by the doping process and the JFET region, so that the cell size of the device is smaller than that of the conventional silicon carbide power device, the cell density of the device is greatly improved, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 4:
referring to fig. 7, a heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure, includes: the structure comprises an N + type substrate 1, drain metal 8 is connected to the lower surface of the N + type substrate 1, an N-type drift region 2 is arranged on the upper surface of the N + type substrate 1, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, source metal 4 is symmetrically arranged on the upper surface of the graphene source regions 3, gate dielectric layers 5 are arranged on the upper surfaces of the N-type drift region 2 and the graphene source regions 3, a polysilicon gate 6 is arranged on the upper surface of each gate dielectric layer 5, and a passivation layer 7 is arranged above the polysilicon gate 6. The upper surface of the N-type drift region 2 is grooved, a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and a source electrode metal 4, and a heterojunction formed in a power device is formed at the contact surface of the graphene source regions 3 and part of the N-type drift region 2.
The invention adopts the following method to prepare:
step 1: taking an N + type substrate 1, and attaching silicon carbide on the other surface of the N + type substrate 1 to form an N-type drift region 2;
step 2: forming a groove on the surface of the N-type drift region 2 by using an etching process;
and step 3: forming a graphene source region 3 on the bottom of the groove;
and 4, step 4: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
and 5: depositing polycrystalline silicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polycrystalline silicon gate 6;
step 6: forming an isolation passivation layer 7 above the polysilicon gate 6 by using a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is formed on the other surface of the N + type substrate 1.
A heterojunction is formed by using graphene and a silicon carbide substrate, the area of the heterojunction is enlarged through a grooving process, when positive pressure is applied to a grid electrode, the Fermi level of the graphene shifts and enters a conduction band, meanwhile, the electron concentration of an N-type drift region rises to form an accumulation layer, the width of a heterojunction potential barrier is narrowed, a band-band tunneling effect occurs at triple contact surfaces of a graphene source region, the N-type drift region and a gate dielectric layer, and the electron tunneling of a graphene valence band penetrates through the heterojunction potential barrier and enters the conduction band of the N-type drift region. The structure has larger area for band-to-band tunneling effect and larger current density.
Meanwhile, the three-port power device can be formed without an injection doping process in the embodiment, and the cell size of the device is not limited by the doping process and the JFET region, so that the cell size of the device is smaller than that of the conventional silicon carbide power device, the cell density of the device is greatly improved, the specific on-resistance of the device is effectively reduced, the power density of the device is increased, the subthreshold swing of the device is reduced, the manufacturing process is greatly simplified, and the cost of the device is reduced.
Example 5:
referring to fig. 8, a heterojunction-based high power density tunneling semiconductor device and a manufacturing process thereof, the heterojunction-based high power density tunneling semiconductor device having an axisymmetric structure, includes: the semiconductor device comprises an N + type substrate 1, wherein the lower surface of the N + type silicon carbide substrate 1 is connected with drain metal 8, the upper surface of the N + type substrate 1 is provided with an N-type drift region 2, the upper surface of the N-type drift region 2 is symmetrically provided with a pair of graphene source regions 3, and the upper surface of the graphene source regions 3 is symmetrically provided with source metal 4. The upper surfaces of the N-type drift region 2 and the graphene source region 3 are provided with gate dielectric layers 5, the upper surface of the gate dielectric layer 5 is provided with a polysilicon gate 6, a passivation layer 7 is arranged above the polysilicon gate 6, the N-type drift region 2 is provided with a pair of P + type regions 9, and the N-type drift region 2 below the gate dielectric layer 5 is internally provided with a P + type region 10. The upper surface of an N-type drift region 2 is grooved, a pair of P + type regions 9 are arranged at the bottom of the groove, a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2, a certain distance is reserved between the pair of graphene source regions 3, a gate dielectric layer 5 partially overlapped with the graphene source regions 3 is arranged on the N-type drift region 2, a polysilicon gate 6 is flush with the gate dielectric layer 5, a certain distance is reserved between the polysilicon gate 6 and a source metal 4, a heterojunction is formed at the contact surface of the graphene source regions 3 and the N-type drift region 2, the graphene source regions 3, the N-type drift region 2 and the gate dielectric layer 5 are in contact, a triple contact point is formed, and the contact point is wrapped by depletion layers of the P + type regions 10 and the N-type drift region 2. A certain distance is reserved between the P + type region 10 and the graphene source region 3, the distance is smaller than the widths of depletion layers of the P + type region 10 and the N-drift region 2 when negative pressure or zero pressure is applied to the polysilicon gate 6, the depletion layers wrap the triple contact surfaces at the moment, meanwhile, the distance is larger than the widths of depletion layers of the P + type region 9 and the N-drift region 2 when positive pressure is applied to the polysilicon gate 6, and the depletion layers do not wrap the triple contact points at the moment.
The invention adopts the following method to prepare:
step 1: taking an N + type substrate 1, and attaching silicon carbide on the other surface of the N + type substrate 1 to form an N-type drift region 2;
and 2, step: forming a groove on the surface of the N-type drift region 2 by using an etching process;
and step 3: forming a P + type shielding layer 9 at the bottom of the trench by using a doping process, and doping a III-group element on the upper surface of the N-type drift region 2 to form a P + type shielding layer 10;
and 4, step 4: forming a graphene source region 3 on the bottom of the groove;
and 5: forming a gate dielectric layer 5 on the upper surface of the N-type drift region 2 by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer 5 by using a deposition process and forming a polysilicon gate 6;
and 7: forming an isolation passivation layer 7 above the polysilicon gate 6 by a deposition process; finally, a source metal 4 is formed on the upper surface of the graphene source region 3, and a drain metal 8 is formed on the other surface of the N + type substrate 1.
A heterojunction is formed by using graphene and a silicon carbide substrate, the Fermi level of the graphene is moved upwards by applying positive voltage to a grid electrode and enters a conduction band, and meanwhile, the electron concentration of an N-type drift region is increased to form an accumulation layer. The electron accumulation region enables a depletion layer between the P + type region and the N-drift region below the gate dielectric layer to be narrowed, and the triple contact points are not wrapped. At the moment, enough positive voltage is applied to the grid electrode, a band-to-band tunneling effect is generated at triple contact surfaces of the graphene source region, the N-type region drift region and the grid dielectric layer, and an electron tunnel of a graphene valence band penetrates through a heterojunction barrier and enters a conduction band of the N-type drift region. And when negative voltage or zero voltage is applied to the grid electrode, the depletion layer between the P + type region and the N-drift region below the grid dielectric layer wraps the triple contact point. When the device is reversely biased, the P + region 9 enables the electric field peak value to be transferred to the PN junction boundary from the heterojunction boundary, so that the avalanche capability of the device is improved, the reverse bias leakage current is reduced, the breakdown voltage is increased, the electric field of the gate dielectric layer 5 is shielded by the P + region 10, and the gate oxide reliability of the device is improved.
The structure improves the gate oxide reliability of the device, reduces the gate leakage capacitance and improves the switching characteristic under the condition of not sacrificing the forward conduction capability of the heterojunction-based high-power-density tunneling power semiconductor device.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and amendments can be made without departing from the principle of the present invention, and these modifications and amendments should also be considered as the protection scope of the present invention.
Claims (10)
1. A high-power density tunneling semiconductor device based on a heterojunction is of an axisymmetric structure and comprises an N + substrate, a drain electrode metal arranged below the N + substrate, and an N-drift region arranged on the N + substrate; the tunneling junction transistor is characterized in that a pair of graphene source regions arranged at intervals are arranged above the N-drift region, source metal is arranged on the graphene source regions, a gate dielectric layer partially overlapped with the graphene source regions is arranged on the N-drift region, a polysilicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polysilicon gate, the polysilicon gate and the source metal are arranged at intervals, a heterojunction is formed at the contact position of the graphene source region and the N-drift region, triple contact surfaces are formed among the graphene source region, the N-type region drift region and the gate dielectric layer, and tunneling effect occurs at the triple contact surfaces.
2. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein two spaced grooves are present on the upper surface of the N-type drift region (2), the graphene source region (3) is disposed in the grooves, and the P + -type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).
3. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is disposed on the upper surface of the N-type drift region (2), and a P + type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).
4. A heterojunction-based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is disposed on the upper surface of the N-type drift region (2).
5. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein two spaced grooves exist on the upper surface of the N-type drift region (2), and the graphene source region (3) is arranged in the grooves.
6. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein a P + type region (9) is disposed in the N-type drift region (2) below the graphene source region (3), a second P + type region (10) is disposed in the N-type drift region (2) below the gate dielectric layer (5), and the second P + type region (10) is spaced from the graphene source region (3).
7. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the N + type substrate (1) and the N-type drift region (2) are not limited by materials, silicon carbide, gallium oxide, silicon, diamond or other materials capable of forming the heterojunction tunneling power semiconductor device substrate and drift region can be used, and the doping concentrations of the N + type substrate (1) and the N-type drift region (2) are not limited.
8. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is not limited by materials, and graphene, molybdenum disulfide, polysilicon, metal or other materials that can form the source region of the heterojunction tunneling semiconductor device can be used.
9. The heterojunction-based high-power-density tunneling semiconductor device and the manufacturing process thereof according to claim 1, wherein the thickness of the gate dielectric layer (5) is not limited, and the gate dielectric layer (5) is not limited by materials, and silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or other materials capable of forming the gate dielectric layer of the heterojunction tunneling semiconductor device can be used.
10. A manufacturing method of a heterojunction-based high-power-density tunneling semiconductor device is characterized by comprising the following steps:
step 1: attaching silicon carbide on the surface of an N + type substrate (1) to form an N-type drift region (2);
step 2: forming a groove on the surface of the N-type drift region (2) by using an etching process;
and step 3: forming a P + type shielding layer (9) at the bottom of the groove by using a doping process;
and 4, step 4: forming a layer of graphene source region (3) on the bottom of the trench;
and 5: forming a gate dielectric layer (5) on the upper surface of the N-type drift region (2) by using a deposition process;
step 6: depositing polysilicon on the upper surface of the gate dielectric layer (5) by using a deposition process and forming a polysilicon gate (6);
and 7: forming an isolation passivation layer (7) above the polysilicon gate (6) by a deposition process;
and 8: and finally, forming a source metal (4) on the upper surface of the graphene source region (3), and manufacturing a drain metal (8) on the other surface of the N + type substrate (1).
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| US20070252172A1 (en) * | 2006-04-28 | 2007-11-01 | Nissan Motor Co., Ltd. | Semiconductor device |
| DE102012204539A1 (en) * | 2012-03-21 | 2013-09-26 | Robert Bosch Gmbh | Power transistor e.g. vertical MOSFET, has graphene layer that is formed on source regions and is partially overlapped with the gate electrode so that ducts are formed on graphene layer |
| US20200127130A1 (en) * | 2018-10-17 | 2020-04-23 | The Research Foundation For The State University Of New York | Ballistic field-effect transistors based on bloch resonance and methods of operating a transistor |
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| US10217819B2 (en) * | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
| CN108899369B (en) * | 2018-06-27 | 2020-11-03 | 东南大学 | Graphene channel silicon carbide power semiconductor transistor |
| CN111312802B (en) * | 2020-02-27 | 2022-01-28 | 电子科技大学 | Low-starting-voltage and low-on-resistance silicon carbide diode and preparation method thereof |
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| US20070252172A1 (en) * | 2006-04-28 | 2007-11-01 | Nissan Motor Co., Ltd. | Semiconductor device |
| DE102012204539A1 (en) * | 2012-03-21 | 2013-09-26 | Robert Bosch Gmbh | Power transistor e.g. vertical MOSFET, has graphene layer that is formed on source regions and is partially overlapped with the gate electrode so that ducts are formed on graphene layer |
| US20200127130A1 (en) * | 2018-10-17 | 2020-04-23 | The Research Foundation For The State University Of New York | Ballistic field-effect transistors based on bloch resonance and methods of operating a transistor |
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