CN113488540A - SiC-based trench gate MOSFET structure with vertical field plate protection - Google Patents
SiC-based trench gate MOSFET structure with vertical field plate protection Download PDFInfo
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- CN113488540A CN113488540A CN202110627327.1A CN202110627327A CN113488540A CN 113488540 A CN113488540 A CN 113488540A CN 202110627327 A CN202110627327 A CN 202110627327A CN 113488540 A CN113488540 A CN 113488540A
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- 230000000903 blocking effect Effects 0.000 claims abstract description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 37
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 11
- 239000002184 metal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 210000003850 cellular structure Anatomy 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
A SiC-based trench gate MOSFET structure with vertical field plate protection belongs to a power semiconductor switch device. The structure is added with deep groove groups on the basis of the common groove gate MOSFET. The deep groove and the grid groove are coaxial and have similar shapes, and the distance between the outer edge of the deep groove and the inner edge of the grid groove is uniform and equal and is controlled to be 1-3 microns. The deep groove is 2-10 microns deeper than the gate groove, the polycrystal filled in the deep groove is connected with the source electrode, and the polycrystal plays a role of a vertical bias field plate in the blocking state of the device, so that the electric field intensity at the corner of the gate groove can be effectively reduced, and the gate reliability is improved. The epitaxial layer is divided into two layers, the doping concentration and the thickness of the epitaxial layer of the first layer are related to the blocking voltage, and the doping concentration is required to be 1-2 multiplied by 10 for the withstand voltage of 1200V16cm‑3In the range of 8-10 μm, the doping concentration of the second epitaxial layer is controlled to be 1-5 × 1016cm‑3The range, thickness is the same as the deep groove depth. The total thickness of the first epitaxial layer and the second epitaxial layer is 15-17 microns.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC-based trench gate MOSFET device structure with vertical field plate protection.
Background
The development trend of the current electronic equipment is high efficiency, energy saving and miniaturization, which requires a power semiconductor switch device as a core of electric energy conversion and processing, and has higher blocking capability, lower conduction loss, faster switching speed and better thermal stability. Through decades of development, the device characteristics of silicon-based power semiconductor devices approach the material limit, which greatly limits the promotion space for further optimization of electronic equipment. The third generation semiconductor material represented by silicon carbide has the advantages of wide forbidden band width (more than 3.0 eV), large critical breakdown electric field, high stable working temperature and the like, so that the third generation semiconductor material has great development potential in extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The SiC power MOSFET has many advantages of high input impedance, fast switching speed, high operating frequency, high voltage resistance, etc., has been widely applied to the aspects of switching regulated power supply, high frequency and power amplifier, etc., is a green pioneer to promote the "new energy revolution", and is more promising in high-power application occasions of high-speed railways, hybrid electric vehicles, intelligent high-voltage direct-current transmission, etc.
Compared with a planar gate MOSFET, the trench gate MOSFET has no parasitic JFET (junction field effect transistor) region, and high-density cells are very easy to integrate along with the progress of the process technology, so that the trench gate MOSFET has lower on-state resistance and is a mainstream structure for development of medium-low voltage high-power MOS field effect transistors. However, compared with a silicon-based device, the SiC device has a higher critical breakdown electric field, which results in a blocking state of the trench gate MOSFET, and the electric field in the oxide layer at the corner of the trench bottom is very high, close to the critical breakdown electric field of silicon dioxide, which has a great influence on the gate reliability.
In 1998, J.Tan et al reported an enhanced 4H-SiC UMOSFET structure that uses a P buried layer to reduce the bottom gate oxide electric field and a CSL layer to reduce the JFET region resistance; in 2012, Rohm company reported 4H-SiC double-trench MOSFET, the structure firstly proposed the design concept of double trenches, and a special metal trench was used to inject a P buried layer to shield the electric field lines pointing to the gate trench oxide layer, so as to improve the reliability of the device, but the depth of the double trenches is the same; in 2017, Infineon reported a 4H-SiC asymmetric groove gate MOSFET, the structure adopts a single-channel asymmetric design concept, and the 4H-SiC asymmetric groove gate MOSFET is effectively utilized
Due to the characteristic of high channel mobility, the channel resistance is reduced. Deep P formed by high energy ion implantation+The gate oxide layer can be well protected, meanwhile, the saturation current can be effectively lowered, and the short circuit capability of the device is improved.
Disclosure of Invention
The invention aims to provide a novel MOSFET structure, and by using the structure, the grid reliability can be improved on the basis of not increasing the difficulty of device preparation.
The invention mainly reduces the electric field intensity at the corner of the gate groove by the design of the deep groove group and the improvement effect of the vertical bias field plate on the electric field.
The technical problem to be solved by the invention is realized by the following technical scheme:
the biggest difference between the invention and the common groove grid structure is that a deep groove group is added, see figure 1. From bottom to top in turn is a drain metallisation electrode layer, N+A silicon carbide substrate layer 1 having a thickness of about 400 microns and about 10 microns during device fabrication19cm-3The doping concentration of (a); adjacent to the substrate layer is a first epitaxial layer 2 of silicon carbide having a thickness and doping concentration that vary with the withstand voltage of the device, for example about 15 to 20 microns for a 1700V SiC MOSFET, and a doping concentration of 5X 1015cm-3. Adjacent to the epitaxial layer 2 is a second structure with deep trench clusters 10 and trench gate MOS structuresAn epitaxial layer 3 of silicon carbide with a doping concentration controlled to 1-5 x 1016cm-3In the range of 4 to 12 microns thick. And forming a silicon dioxide dielectric layer with the thickness of 0.2 to 1 micron by a thermal oxidation and chemical vapor deposition process through the deep groove penetrating through the second silicon carbide epitaxial layer, and then carrying out doping polycrystalline filling by a conventional process. The surface of the second silicon carbide epitaxial layer is of a groove grid MOS structure which consists of a grid groove network 6, a P type silicon carbide body region 4 and N+A silicon carbide source region 7 and a back gate short-circuit region 8. The deep groove 10 is similar to the grid groove 6 in a coaxial mode, the distance 11 between the outer edge of the deep groove and the inner edge of the grid groove is uniform and equal, and the distance is controlled to be 1-3 micrometers. The deep groove is 2-10 microns deeper than the gate groove, and the doped polycrystal in the deep groove is connected with the source electrode to form a vertical field plate. The grid groove network structure comprises an insulated grid dielectric layer 5 with the thickness of 500-800 angstroms and shallow groove polysilicon 6, and is prepared according to a conventional groove grid process. And the shallow groove polycrystalline network is used for leading out an electrode through gate metal at the gate pad.
The invention adopts the scheme that the grid groove network surrounds the deep groove group, thereby being suitable for strip-shaped cellular structures and cellular structures with various shapes such as rectangle, circle, ellipse and the like.
The SiC-based trench gate MOSFET structure with the vertical field plate protection is characterized in that deep trench clusters are distributed near a gate trench network, and when a device works in a blocking state, deep trench polycrystal connected with a source electrode plays a role of a field plate, so that electric field distribution can be improved, the electric field intensity at the corner of a gate trench of the device is reduced, the impact of the device on gate oxide in a switching process is reduced, the gate reliability of the MOS device is improved, and the long-term stability of the device is improved.
Drawings
Fig. 1 is a schematic three-dimensional cross-sectional structure of the present invention.
In the figure: 1-silicon carbide N+A substrate; 2-first silicon carbide epitaxial layer N1; 3-second silicon carbide epitaxial layer N2; 4-P-type silicon carbide body region; 5-grid groove silicon dioxide dielectric layer; 6, doping polysilicon in the gate groove; 7-silicon carbide N+A source region; 8-silicon carbide P+A back gate short circuit region; 9-deep groove silicon dioxide dielectric layer; 10-deep groove doping polysilicon; 11-gridThe groove is spaced from the deep groove.
Detailed Description
The invention is further described with reference to the figures and examples.
Examples
This embodiment is a 1200V silicon carbide based trench gate MOSFET with vertical field plate protection, the structure of which is shown in fig. 1. In its structure, except for the deep trench group 10 embodying features of the present invention, the structure is otherwise the same as that of a conventional trench gate MOSFET device: from bottom to top in turn is a drain metallisation electrode layer, N+A silicon carbide substrate layer 1 having a thickness of about 400 microns and about 10 microns during device fabrication19cm-3The doping concentration of (a); adjacent to the substrate layer is a first epitaxial layer 2 of silicon carbide having a thickness of about 8 microns or 10 microns and a doping concentration of 1 x 1016cm-3. Adjoining the epitaxial layer 2 is a second silicon carbide epitaxial layer 3 with deep trench clusters 10 and a trench-gate MOS structure, the doping concentration of which is chosen to be 5 × 1016cm-3And a thickness of 7 μm. The shape of the deep groove is hexagonal as the cellular shape, and the side length of the hexagonal groove is 3 micrometers. The depth of the deep groove is 7 microns, a 500 angstrom oxide layer is generated through thermal oxidation, and then a silicon dioxide dielectric layer with the total thickness of 1 micron is formed through a chemical vapor deposition process. The doped polycrystalline fill is prepared according to conventional processes. The silicon carbide surface groove grid MOS structure is composed of a grid groove network 6, a P-type silicon carbide body region 4 and N+A silicon carbide source region 7 and a back gate short-circuit region 8. The grid groove 6 is coaxial with the deep groove 10 and is also hexagonal in shape, and the distance 11 between the outer edge of the deep groove and the inner edge of the grid groove is uniform and equal and is 1.5 micrometers. The doped polycrystal in the deep groove is connected with the source electrode to form a vertical field plate. The thickness of the grid groove network oxide layer 5 is 500-800 angstroms, and the filled doped polycrystal is prepared according to 6 by a conventional groove grid process. And the shallow groove polycrystalline network is used for leading out an electrode through gate metal at the gate pad.
The implementation method of the embodiment is basically the same as the conventional trench gate MOSFET manufacturing technology, and includes substrate epitaxy (1 time two layers), deep trench lithography and etching, sacrificial oxidation, sacrificial oxide layer removal, deep trench oxidation, deep trench silicon dioxide deposition, deep trench poly deposition, gate trench lithography and etching, sacrificial oxidation, sacrificial oxide layer removal, gate oxidation, poly filling and etching back, P-type body region injection and diffusion, N-type source region injection and diffusion, isolated oxygen deposition, lead hole lithography and etching, source metal sputtering, metal reverse etching, passivation layer deposition, metal sputtering on the back of a pressure pad, alloy and the like.
The sample prepared according to the process has 2000 switching impacts under the conditions of 900V drain electrode pressure and 15V gate electrode pressure, the device is normal, and the threshold voltage and the gate leakage current are not obviously degraded.
The working principle of the embodiment is as follows:
deep groove groups are distributed near the grid groove network, when the device works in a blocking state, the deep groove polycrystal connected with the source electrode plays a role of a field plate, electric field distribution can be improved, electric field intensity at the corner of the grid groove of the device is reduced, impact of the device on grid oxygen in a switching process is reduced, grid reliability of the MOS device is improved, and long-term stability of the device is improved.
Claims (1)
1. SiC-based trench gate MOSFET structure with vertical field plate protection, characterized in that:
from bottom to top in turn is a drain metallisation electrode layer, N+The silicon carbide substrate layer is a first silicon carbide epitaxial layer, and the adjacent epitaxial layer is a second silicon carbide epitaxial layer with a deep groove group and a groove gate MOS structure; the groove grid MOS consists of a grid groove network, a P-type silicon carbide body region and N+The silicon carbide source region and the back gate short circuit region; the deep groove group is coaxial with the grid groove network, and the grid groove network surrounds the deep groove group; the distance between the outer edge of the deep groove and the inner edge of the grid groove is uniform and equal and is controlled to be 1-3 microns; the deep groove is 2-10 microns deeper than the gate groove, and a silicon dioxide dielectric layer with the thickness of 0.2-1 micron is formed in the deep groove through thermal oxidation and chemical vapor deposition; after the silicon dioxide dielectric layer is formed on the deep groove, doping polycrystalline silicon, and connecting the doping polycrystalline silicon with the source electrode to form a vertical field plate; the epitaxial layer is divided into two layers, the doping concentration and the thickness of the epitaxial layer of the first layer are related to the blocking voltage, and the doping concentration is required to be 1-2 multiplied by 10 for the withstand voltage of 1200V16cm-3Second epitaxial layer in the range of 8-10 micronsThe impurity concentration is controlled to be 1-5 × 1016cm-3The range, thickness is the same as deep groove depth; the total thickness of the first epitaxial layer and the second epitaxial layer is 15-17 microns.
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| CN202110627327.1A CN113488540A (en) | 2021-06-05 | 2021-06-05 | SiC-based trench gate MOSFET structure with vertical field plate protection |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809179A (en) * | 2021-10-20 | 2021-12-17 | 无锡橙芯微电子科技有限公司 | SIC DMOS device structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247732A (en) * | 1997-03-05 | 1998-09-14 | Denso Corp | Silicon oxide semiconductor device and manufacture thereof |
| CN1790745A (en) * | 2004-08-27 | 2006-06-21 | 国际整流器公司 | Power devices having trench-based source and gate electrodes |
| CN110637374A (en) * | 2017-05-17 | 2019-12-31 | 罗姆股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112713184A (en) * | 2019-10-24 | 2021-04-27 | 南通尚阳通集成电路有限公司 | Trench gate MOSFET with shield gate and manufacturing method thereof |
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2021
- 2021-06-05 CN CN202110627327.1A patent/CN113488540A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247732A (en) * | 1997-03-05 | 1998-09-14 | Denso Corp | Silicon oxide semiconductor device and manufacture thereof |
| CN1790745A (en) * | 2004-08-27 | 2006-06-21 | 国际整流器公司 | Power devices having trench-based source and gate electrodes |
| CN110637374A (en) * | 2017-05-17 | 2019-12-31 | 罗姆股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112713184A (en) * | 2019-10-24 | 2021-04-27 | 南通尚阳通集成电路有限公司 | Trench gate MOSFET with shield gate and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809179A (en) * | 2021-10-20 | 2021-12-17 | 无锡橙芯微电子科技有限公司 | SIC DMOS device structure |
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