CN110473914A - A kind of preparation method of SiC-MOS device - Google Patents

A kind of preparation method of SiC-MOS device Download PDF

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CN110473914A
CN110473914A CN201910879293.8A CN201910879293A CN110473914A CN 110473914 A CN110473914 A CN 110473914A CN 201910879293 A CN201910879293 A CN 201910879293A CN 110473914 A CN110473914 A CN 110473914A
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silicon carbide
metal
epitaxial layer
layer
etching
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CN110473914B (en
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姚金才
陈宇
朱超群
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Shenzhen Hester Technology Co Ltd
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

The invention discloses a kind of preparation methods of SiC-MOS device, the present invention is by changing metal material, technology controlling and process and silicon carbide N-epitaxial layer concentration, schottky barrier height can be regulated and controled, to form the Schottky contacts compared with low conduction voltage drop (Von), to realize that positive working performance is internal integrated better than the Schottky diode of parasitic diode, with faster reverse recovery time, lower reverse recovery loss and more preferably Reverse recovery reliability, with more preferably Reverse recovery performance, significantly reduce power electronic system volume, encapsulation is reduced to spend, avoid metal lead wire bring ghost effect, to improve system application reliability, with more compact cell density, compare conducting resistance with lower, have the characteristics that electric leakage is low.

Description

A kind of preparation method of SiC-MOS device
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of preparation method of SiC-MOS device.
Background technique
Silicon carbide MOSFET device is the generation semiconductor devices manufactured with semiconductor material with wide forbidden band silicon carbide.Carbonization The many attracting characteristics of silicon materials, critical breakdown electric field intensity, high thermal conductivity, the big forbidden band of such as 10 times of silicon materials are wide Degree and high electronics saturation drift velocity etc. make SiC material become the research hotspot of power semiconductor in the world, and High power applications occasion, such as high-speed railway, hybrid vehicle, intelligent high-pressure direct current transportation, silicon carbide device are endowed Very high expectation.Silicon carbide power device is significant to the reducing effect of power loss simultaneously, so that silicon carbide power device quilt It is described as " green energy resource " device of drive " new energy revolution ".However, because the undesirable of MOS channel leads to MOS channel mobility It is too low, significantly limit silicon carbide MOSFET on state current density.Therefore, bigger with higher gully density, to have The extensive concern and research that the silicon carbide UMOSFET of on state current density is subject to.Although silicon carbide UMOSFET has more low pass state Resistance and more compact cellular layout, due to the problem that bottom gate electric field across oxide is excessively high, make for a long time to silicon carbide UMOSFET With integrity problem is brought, cause long term device stability poor.Conventional silicon carbide UMOSFET structure is as shown in Figure 1.
Silicon carbide UMOSFET is generally required and an inverse parallel in the application of the circuits such as traditional inverter circuit, chopper circuit Diode plays a role jointly, and usually there are two types of modes: one is directly to use device p-well region, NDrift region and N+Substrate shape At parasitic PIN diode.However, big (the silicon carbide PN junction of the conduction voltage drop of the parasitic silicon carbide diode obtained under this mode Conduction voltage drop is about 3V), and reverse recovery characteristic is poor that (drift region conductance modulation injects excessive current-carrying when forward conduction Son), high power loss is resulted in, this is runed counter to environmentally protective application theory is emphasized instantly；Meanwhile due to its operating rate is low Cause working efficiency low, this is totally unfavorable in the application such as inverter circuit, chopper circuit to silicon carbide UMOSFET；Secondly being By device and an external fast recovery diode, ((FRD) inverse parallel is used.However, this mode can cause system cost rising, The increase of volume and because caused by metal connecting line increase reliability reduce, finally make silicon carbide VDMOS device in tradition Popularization in the application of the circuits such as inverter circuit, chopper circuit receives certain obstruction.
Summary of the invention
The purpose of the present invention is to provide a kind of preparation methods of SiC-MOS device, to solve to mention in above-mentioned background technique Out the problem of.
To achieve the above object, present invention employs following technical solutions:
A kind of preparation method of SiC-MOS device, includes the following steps:
S1, silicon carbide N+substrate and silicon carbide N-epitaxial layer are chosen, to silicon carbide N+substrate and silicon carbide N-epitaxial layer into Row cleans and drying；
S2, by trench etch process, etched using Trench mask plate in silicon carbide N-epitaxial layer upper surface specified The source electrode groove and gate trench of size, form mesa structure between source electrode groove and gate trench；
S3, pass through photoetching, energetic ion injection technology, using mask plate in silicon carbide N-epi-layer surface mesa structure Upper and source electrode channel bottom carries out Al ion implantation, forms silicon carbide P-doped zone；
S4, pass through photoetching, energetic ion injection technology, the silicon carbide p-type using mask plate in source electrode channel bottom is adulterated It carries out Al ion implantation in area, forms the silicon carbide P+ doped region apart from 0.2 μm of silicon carbide P-doped zone edge；
S5, pass through photoetching, energetic ion injection technology, utilize silicon carbide P-doped zone of the mask plate on mesa structure Surface carries out N~+ implantation, forms silicon carbide N+source region；
S6, high annealing carry out activated to the ion of injection；
S7, gate trench surface is aoxidized, forms the SiO with a thickness of 50nm2Insulate gate dielectric layer；
S8, pass through low pressure hot wall chemical vapor sedimentation in SiO2It is dense to form phosphonium ion doping for deposit on insulation gate dielectric layer Degree is 1 × 1020cm-3, with a thickness of the polysilicon gate of 800nm；
S9, to SiO2Insulation gate dielectric layer and polysilicon gate carry out photoetching, etching, only retain the SiO inside gate trench2 Insulate gate dielectric layer and polysilicon gate, and is ground, so that polysilicon gate upper surface and mesa structure in gate trench It flushes；
S10, gate metal is formed on polysilicon gate by deposit and photoetching, etching technics, and carries out high annealing, Form good ohmic contact；
S11, pass through low pressure hot wall chemical vapor sedimentation in silicon carbide N+substrate lower surface deposit metal-drain, and into Row high annealing makes gate metal form good ohmic with metal-drain and contacts；
S12, one layer of Schottky contacts gold is deposited in source electrode channel bottom by lift-off technique sputtering deposit W metal Belong to, extra W metal is removed by etching, and rapid thermal treatment is handled, and forms good Schottky contacts；
S13, boron-phosphorosilicate glass insulating medium layer, and high temperature reflux, shape are formed by deposit, photoetching and etching technics Camber boundary；
S14, source metal and grid connection metal are formed by deposit, photoetching and etching technics, complete preparation.
Preferably, the step S2 includes:
S21, photoetching is carried out in silicon carbide N-epitaxial layer upper surface, forms grid and source electrode trench openings, so that being located at grid Silicon carbide N-epitaxial layer region partial denudation at pole trench openings and source electrode trench openings；
S22, silicon carbide N-epitaxial layer is performed etching to form gate trench using sense coupling technology With source electrode groove, etching pressure is 0.3~0.5Pa, and temperature is room temperature, and source power is 700~800W, substrate bias power is 100~ 200W；Etching gas includes sulfur hexafluoride, oxygen and argon gas, wherein and the gas flow ratio of sulfur hexafluoride and argon gas is 2:1, The variation range of oxygen content is 45%~50%, and etching depth is 0.8 μm.
Preferably, the step S3 includes:
S31, by low pressure hot wall chemical vapor sedimentation on silicon carbide N-epi-layer surface mesa structure and grid Pole groove and source electrode channel bottom deposit blocking of the Al that a layer thickness is 1.5 μm as silicon carbide P-doped zone ion implanting Layer forms silicon carbide P-doped zone injection region by lithography and etching；
S32,650 DEG C at a temperature of multiple Al ion implanting is carried out to silicon carbide N-epitaxial layer front, in silicon carbide p-type It is 0.6 μm that doped region injection region, which forms depth, and doping concentration is 3 × 1018cm-3Silicon carbide P-doped zone；
S33, the Al that silicon carbide N-epi-layer surface and source electrode channel bottom are removed using phosphoric acid, and be cleaned and dried.
Preferably, the step S4 includes:
S41, by low pressure hot wall chemical vapor sedimentation on silicon carbide N-epi-layer surface mesa structure and grid Pole groove and source electrode channel bottom deposit blocking of the Al that a layer thickness is 1.5 μm as silicon carbide P+ doped region ion implanting Layer forms silicon carbide P+ doped region injection region by lithography and etching；
S42,650 DEG C at a temperature of multiple Al ion implanting is carried out to silicon carbide N-epitaxial layer front, in silicon carbide P+ It is 0.3 μm that doped region injection region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide P+ doped region；
S43, the positive Al of silicon carbide N-epitaxial layer is removed using phosphoric acid, and be cleaned and dried.
Preferably, the step S5 includes:
S51, a layer thickness is deposited in silicon carbide N-epitaxial layer front as 1 μm by low pressure hot wall chemical vapor sedimentation Al forms silicon carbide N+source region injection region as silicon carbide N+source region ion implanting barrier layer, by lithography and etching；
S52,500 DEG C at a temperature of multiple N~+ implantation is carried out to silicon carbide N-epitaxial layer front, silicon carbide N+ It is 0.3 μm that source region injection region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide N+source region；
S53, the positive Al of silicon carbide N-epitaxial layer is removed using phosphoric acid, and be cleaned and dried.
Preferably, the step S6 includes:
S61, silicon carbide N+substrate and silicon carbide N-epi-layer surface are cleaned using RCA cleaning standard, after drying Carbon film protection is made, ion-activated annealing 10min is then carried out in 1700 DEG C of argon atmospheres；
S62, carbon film is removed by oxygen plasma, it is outer to silicon carbide N+substrate and silicon carbide N-using RCA cleaning standard Prolong layer surface to be cleaned, dry.
Preferably, the step S8 mesolow hot wall chemical vapor sedimentation process conditions are: deposition temperature is 600 DEG C, Deposit pressure is 60Pa, and reaction gas uses silane and hydrogen phosphide, and carrier gas uses helium.
Preferably, the metal material of gate metal is any one in Al, Pt, Au, TiN, TiNiAg in the step S10 Kind is several；The overall thickness of the metal-drain be greater than 1 μm, and the metal material of the metal-drain 111 be TiNiAg, Any one or a few in VNiAg, TiNiAu, VNiAu.
Preferably, heat treatment temperature is 850 DEG C in the step S12, and the processing time is 5min under N2 protection.
Technical effect and advantage of the invention:
The present invention is by the way that on the basis of Conventional silicon carbide UMOSFET structure, source area uses groove structure, and in ditch Trench bottom does silicon carbide depth P injection, schottky metal is used in source electrode groove, and schottky metal and silicon carbide N-epitaxial layer exist Source electrode trenched side-wall bottom directly contacts the Schottky diode for being formed and having rectification characteristic.By changing metal material, technique Control and silicon carbide N-epitaxial layer concentration, can regulate and control schottky barrier height, to form Xiao compared with low conduction voltage drop (Von) Te Ji contact, usual contact Von are in the range of 0.8V~2V, to realize positive working performance better than parasitic diode The internal of Schottky diode integrates, and since the diode is how sub- device, deposits in reversely restoring process since there is no few son Storage has faster reverse recovery time, lower reverse recovery loss and more preferably Reverse recovery reliability, compared with There is parasitic diode more preferably Reverse recovery performance to significantly reduce relative to the mode of external one diode of inverse parallel Power electronic system volume reduces encapsulation and spends.Simultaneously because not having the metal lead wire between diode, gold is avoided Belong to the ghost effect of lead bring, to improve system application reliability.Meanwhile relative to numerous internal two poles of single-chip integration The mode of pipe, structure of the invention have more compact cell density.Meanwhile double deep silicon carbide p-type doping designed by the present invention Area helps to promote device pressure resistance level, and reduces device gate dielectric layer electric field, thus to the basic of traditional UMOSFET device Performance and permanent application reliability are also substantially improved.Simultaneously as double depth silicon carbide P-doped zone mentioning for device pressure resistance It rises, so that the doping of the area JFET can effectively improve, therefore SiC-MOS device obtained by the present invention compares electric conduction with lower Resistance, in addition, integrating how sub- rectifying device has the characteristics that electric leakage is low.
Detailed description of the invention
Fig. 1 is existing SiC-MOS device cross section structure schematic diagram；
Fig. 2~Figure 11 is a kind of cross section structure signal of the technical process of the preparation method of SiC-MOS device of the invention Figure.
In figure: 101, silicon carbide N+substrate；102, silicon carbide N-epitaxial layer；103, gate trench；104, source electrode groove； 105, silicon carbide P-doped zone；106, silicon carbide P+ doped region；107, silicon carbide N+source region；108,SiO2Insulate gate dielectric layer； 109, polysilicon gate；110, gate metal；111, metal-drain；112, Schottky contact metal；113, boron-phosphorosilicate glass insulate Dielectric layer；114, source metal.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Herein Described specific embodiment is only used to explain the present invention, is not intended to limit the present invention.Based on the embodiments of the present invention, Every other embodiment obtained by those of ordinary skill in the art without making creative efforts, belongs to this hair The range of bright protection.
The present invention provides a kind of preparation methods of SiC-MOS device as shown in figs. 2-11, include the following steps:
S1, as shown in Fig. 2, silicon carbide N+substrate 101 and silicon carbide N-epitaxial layer 102 are chosen, to silicon carbide N+substrate 101 It is cleaned and is dried with silicon carbide N-epitaxial layer 102；
S2, as shown in figure 3, by trench etch process, using Trench mask plate on silicon carbide N-epitaxial layer 102 table Face etches the source electrode groove 104 and gate trench 103 of specified size, is formed between source electrode groove 104 and gate trench 103 Mesa structure；
S21, photoetching is carried out in 102 upper surface of silicon carbide N-epitaxial layer, grid and source electrode trench openings is formed, so that being located at 102 region partial denudation of silicon carbide N-epitaxial layer at gate trench window and source electrode trench openings；
S22, silicon carbide N-epitaxial layer 102 is performed etching to form grid ditch using sense coupling technology Slot 103 and source electrode groove 104, etching pressure are 0.3~0.5Pa, and temperature is room temperature, and source power is 700~800W, substrate bias power For 100~200W；Etching gas includes sulfur hexafluoride, oxygen and argon gas, wherein the gas flow ratio of sulfur hexafluoride and argon gas For 2:1, the variation range of oxygen content is 45%~50%, and etching depth is 0.8 μm；
S3, as shown in figure 4, by photoetching, energetic ion injection technology, using mask plate in silicon carbide N-epitaxial layer 102 On the mesa structure on surface and 104 bottom of source electrode groove carries out Al ion implantation, forms silicon carbide P-doped zone 105；
S31, by low pressure hot wall chemical vapor sedimentation on the mesa structure on 102 surface of silicon carbide N-epitaxial layer and Gate trench 103 and 104 bottom of source electrode groove deposit the Al that a layer thickness is 1.5 μm as 105 ion of silicon carbide P-doped zone The barrier layer of injection forms 105 injection region of silicon carbide P-doped zone by lithography and etching；
S32,650 DEG C at a temperature of multiple Al ion implanting is carried out to the front of silicon carbide N-epitaxial layer 102, in silicon carbide It is 0.6 μm that 105 injection region of P-doped zone, which forms depth, and doping concentration is 3 × 1018cm-3Silicon carbide P-doped zone 105；
S33, the Al that 102 surface of silicon carbide N-epitaxial layer and 104 bottom of source electrode groove are removed using phosphoric acid, and clean It is dry；
S4, as shown in figure 5, by photoetching, energetic ion injection technology, using mask plate in 104 bottom of source electrode groove It carries out Al ion implantation in silicon carbide P-doped zone 105, forms the carbonization apart from 0.2 μm of 105 edge of silicon carbide P-doped zone Silicon P+ doped region 106；
S41, by low pressure hot wall chemical vapor sedimentation on the mesa structure on 102 surface of silicon carbide N-epitaxial layer and Gate trench 103 and 104 bottom of source electrode groove deposit the Al that a layer thickness is 1.5 μm as 106 ion of silicon carbide P+ doped region The barrier layer of injection forms 106 injection region of silicon carbide P+ doped region by lithography and etching；
S42,650 DEG C at a temperature of multiple Al ion implanting is carried out to the front of silicon carbide N-epitaxial layer 102, in silicon carbide It is 0.3 μm that 106 injection region of P+ doped region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide P+ doped region 106；
S43, the positive Al of silicon carbide N-epitaxial layer 102 is removed using phosphoric acid, and be cleaned and dried；
S5, as shown in fig. 6, by photoetching, energetic ion injection technology, utilize silicon carbide of the mask plate on mesa structure 105 surface of P-doped zone carries out N~+ implantation, forms silicon carbide N+source region 107；
S51, a layer thickness is deposited in 102 front of silicon carbide N-epitaxial layer as 1 μ by low pressure hot wall chemical vapor sedimentation Barrier layer of the Al of m as 107 ion implanting of silicon carbide N+source region forms 107 note of silicon carbide N+source region by lithography and etching Enter area；
S52,500 DEG C at a temperature of multiple N~+ implantation is carried out to the front of silicon carbide N-epitaxial layer 102, in silicon carbide It is 0.3 μm that 107 injection region of N+ source region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide N+source region 107；
S53, the positive Al of silicon carbide N-epitaxial layer 102 is removed using phosphoric acid, and be cleaned and dried；
S6, high annealing carry out activated to the ion of injection；
S61, silicon carbide N+substrate 101 and 102 surface of silicon carbide N-epitaxial layer are cleaned using RCA cleaning standard, Carbon film protection is made after drying, and ion-activated annealing 10min is then carried out in 1700 DEG C of argon atmospheres；
S62, carbon film is removed by oxygen plasma, using RCA cleaning standard to silicon carbide N+substrate 101 and silicon carbide N- 102 surface of epitaxial layer is cleaned, drying；
S7, as shown in fig. 7, aoxidized to 103 surface of gate trench, form the SiO with a thickness of 50nm2Insulate gate medium Layer 108；
S8, as shown in fig. 7, by low pressure hot wall chemical vapor sedimentation in SiO2Shape is deposited on insulation gate dielectric layer 108 It is 1 × 10 at phosphonium ion doping concentration20cm-3, with a thickness of the polysilicon gate 109 of 800nm, low pressure hot wall chemical vapor sedimentation Process conditions are: deposition temperature is 600 DEG C, and deposit pressure is 60Pa, and reaction gas uses silane and hydrogen phosphide, and carrier gas is adopted Use helium；
S9, to SiO2Insulation gate dielectric layer 108 and polysilicon gate 109 carry out photoetching, etching, only retain gate trench 103 Internal SiO2Insulate gate dielectric layer 108 and polysilicon gate 109, and is ground, so that the polysilicon in gate trench 103 109 upper surface of grid is flushed with mesa structure；
S10, as shown in figure 8, by deposit and photoetching, etching technics gate metal 110 is formed on polysilicon gate 109, And high annealing is carried out, good ohmic contact is formed, the metal material of gate metal 110 is Al, Pt, Au, TiN, TiNiAg In any one or a few；
S11, gold is deposited in 101 lower surface of silicon carbide N+substrate as shown in figure 8, passing through low pressure hot wall chemical vapor sedimentation Belong to drain electrode 111, and carry out high annealing, so that gate metal 110 is formed good ohmic with metal-drain 111 and contact, metal leakage The overall thickness of pole 111 is greater than 1 μm, and the metal material of metal-drain 111 is appointing in TiNiAg, VNiAg, TiNiAu, VNiAu Meaning is one or more of；
S12, one layer is deposited in 104 bottom of source electrode groove as shown in figure 9, passing through lift-off technique sputtering deposit W metal Schottky contact metal 112 removes extra W metal by etching, and rapid thermal treatment is handled, heat treatment temperature 850 DEG C, the processing time is 5min under N2 protection, forms good Schottky contacts；
S13, as shown in Figure 10, by deposit, photoetching and etching technics formed boron-phosphorosilicate glass insulating medium layer 113, And high temperature reflux forms arc boundary；
S14, as shown in figure 11, pass through deposit, photoetching and etching technics formed source metal 114 and grid connection gold Belong to, completes preparation.
In conclusion the present invention is by the way that on the basis of Conventional silicon carbide UMOSFET structure, source area uses groove knot Structure, and silicon carbide depth P injection is done in channel bottom, schottky metal, and schottky metal and carbonization are used in source electrode groove Silicon N- epitaxial layer directly contacts the Schottky diode for being formed and having rectification characteristic in source electrode trenched side-wall bottom.By changing gold Belong to material, technology controlling and process and silicon carbide N-epitaxial layer concentration, schottky barrier height can be regulated and controled, to form lower conducting pressure The Schottky contacts of (Von) drop, and usual contact Von is in the range of 0.8V~2V, to realize that positive working performance is better than The Schottky diode of parasitic diode it is internal integrated, since the diode is how sub- device, in reversely restoring process due to There is no few sub- storages, have faster reverse recovery time, lower reverse recovery loss and more preferably Reverse recovery can There is more preferably Reverse recovery performance, the side relative to external one diode of inverse parallel compared with parasitic diode by property Formula significantly reduces power electronic system volume, reduces encapsulation and spends.Simultaneously because not having the metal between diode Lead avoids metal lead wire bring ghost effect, to improve system application reliability.Meanwhile relative to numerous bodies The mode of interior single-chip integration diode, structure of the invention have more compact cell density.Meanwhile it is double deep designed by the present invention Silicon carbide P-doped zone helps to promote device pressure resistance level, and reduces device gate dielectric layer electric field, thus to tradition The basic performance of UMOSFET device and permanent application reliability are also substantially improved.Simultaneously as double depth silicon carbide p-type doping Area is for the promotion of device pressure resistance, so that the doping of the area JFET can effectively improve, therefore SiC-MOS device obtained by the present invention has Have it is lower than conducting resistance, in addition, integrate how sub- rectifying device have the characteristics that electric leakage it is low.
Finally, it should be noted that the foregoing is only a preferred embodiment of the present invention, it is not intended to restrict the invention, Although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art, still may be used To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features, All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in of the invention Within protection scope.

Claims (9)

1. a kind of preparation method of SiC-MOS device, which comprises the steps of:
S1, silicon carbide N+substrate and silicon carbide N-epitaxial layer are chosen, silicon carbide N+substrate and silicon carbide N-epitaxial layer is carried out clear It washes and dries；
S2, pass through trench etch process, etch specified size in silicon carbide N-epitaxial layer upper surface using Trench mask plate Source electrode groove and gate trench, form mesa structure between source electrode groove and gate trench；
S3, by photoetching, energetic ion injection technology, using mask plate on silicon carbide N-epi-layer surface mesa structure and Source electrode channel bottom carries out Al ion implantation, forms silicon carbide P-doped zone；
S4, pass through photoetching, energetic ion injection technology, using mask plate in the silicon carbide P-doped zone of source electrode channel bottom Al ion implantation is carried out, the silicon carbide P+ doped region apart from 0.2 μm of silicon carbide P-doped zone edge is formed；
S5, pass through photoetching, energetic ion injection technology, utilize silicon carbide P-doped zone surface of the mask plate on mesa structure N~+ implantation is carried out, silicon carbide N+source region is formed；
S6, high annealing carry out activated to the ion of injection；
S7, gate trench surface is aoxidized, forms the SiO with a thickness of 50nm2Insulate gate dielectric layer；
S8, pass through low pressure hot wall chemical vapor sedimentation in SiO2It is dense to form phosphonium ion doping for deposit in insulation gate dielectric layer (108) Degree is 1 × 1020cm-3, with a thickness of the polysilicon gate of 800nm；
S9, to SiO2Insulation gate dielectric layer and polysilicon gate carry out photoetching, etching, only retain gate trench (103) internal SiO2 Insulate gate dielectric layer and polysilicon gate, and is ground, so that polysilicon gate upper surface and mesa structure in gate trench It flushes；
S10, gate metal is formed on polysilicon gate by deposit and photoetching, etching technics, and carries out high annealing, formed Good ohmic contact；
S11, metal-drain is deposited in silicon carbide N+substrate lower surface by low pressure hot wall chemical vapor sedimentation, and carries out height Temperature annealing makes gate metal form good ohmic with metal-drain and contacts；
S12, one layer of Schottky contact metal is deposited in source electrode channel bottom by lift-off technique sputtering deposit W metal, led to Over etching removes extra W metal, and rapid thermal treatment is handled, and forms good Schottky contacts；
S13, boron-phosphorosilicate glass insulating medium layer, and high temperature reflux are formed by deposit, photoetching and etching technics, form arc Shape boundary；
S14, source metal and grid connection metal are formed by deposit, photoetching and etching technics, complete preparation.
2. a kind of preparation method of SiC-MOS device according to claim 1, which is characterized in that the step S2 includes:
S21, photoetching is carried out in silicon carbide N-epitaxial layer upper surface, forms grid and source electrode trench openings, so that being located at grid ditch Silicon carbide N-epitaxial layer region partial denudation at slot window and source electrode trench openings；
S22, silicon carbide N-epitaxial layer is performed etching to form gate trench and source using sense coupling technology Pole groove, etching pressure are 0.3~0.5Pa, and temperature is room temperature, and source power is 700~800W, and substrate bias power is 100~200W, Etching gas includes sulfur hexafluoride, oxygen and argon gas, wherein the gas flow ratio of sulfur hexafluoride and argon gas is 2:1, and oxygen contains The variation range of amount is 45%~50%, and etching depth is 0.8 μm.
3. a kind of preparation method of SiC-MOS device according to claim 1, which is characterized in that the step S3 includes:
S31, by low pressure hot wall chemical vapor sedimentation on silicon carbide N-epi-layer surface mesa structure and grid ditch Slot and source electrode channel bottom deposit barrier layer of the Al that a layer thickness is 1.5 μm as silicon carbide P-doped zone ion implanting, lead to It crosses lithography and etching and forms silicon carbide P-doped zone injection region；
S32,650 DEG C at a temperature of multiple Al ion implanting is carried out to silicon carbide N-epitaxial layer front, adulterated in silicon carbide p-type It is 0.6 μm that area injection region, which forms depth, and doping concentration is 3 × 1018cm-3Silicon carbide P-doped zone；
S33, the Al that silicon carbide N-epi-layer surface and source electrode channel bottom are removed using phosphoric acid, and be cleaned and dried.
4. a kind of preparation method of SiC-MOS device according to claim 1, which is characterized in that the step S4 includes:
S41, by low pressure hot wall chemical vapor sedimentation on silicon carbide N-epi-layer surface mesa structure and grid ditch Slot and source electrode channel bottom deposit barrier layer of the Al that a layer thickness is 1.5 μm as silicon carbide P+ doped region ion implanting, lead to It crosses lithography and etching and forms silicon carbide P+ doped region injection region；
S42,650 DEG C at a temperature of multiple Al ion implanting is carried out to silicon carbide N-epitaxial layer front, adulterated in silicon carbide P+ It is 0.3 μm that area injection region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide P+ doped region；
S43, the positive Al of silicon carbide N-epitaxial layer is removed using phosphoric acid, and be cleaned and dried.
5. a kind of preparation method of SiC-MOS device according to claim 1, which is characterized in that the step S5 includes:
S51, the Al work that a layer thickness is 1 μm is deposited in silicon carbide N-epitaxial layer front by low pressure hot wall chemical vapor sedimentation For silicon carbide N+source region ion implanting barrier layer, silicon carbide N+source region injection region is formed by lithography and etching；
S52,500 DEG C at a temperature of multiple N~+ implantation is carried out to silicon carbide N-epitaxial layer front, in silicon carbide N+source region It is 0.3 μm that injection region, which forms depth, and doping concentration is 1 × 1019cm-3Silicon carbide N+source region；
S53, the positive Al of silicon carbide N-epitaxial layer is removed using phosphoric acid, and be cleaned and dried.
6. a kind of preparation method of SiC-MOS device according to claim 1, which is characterized in that the step S6 includes:
S61, silicon carbide N+substrate and silicon carbide N-epi-layer surface are cleaned using RCA cleaning standard, is made after drying Carbon film protection, then carries out ion-activated annealing 10min in 1700 DEG C of argon atmospheres；
S62, carbon film is removed by oxygen plasma, using RCA cleaning standard to silicon carbide N+substrate and silicon carbide N-epitaxial layer Surface is cleaned, drying.
7. a kind of preparation method of SiC-MOS device according to claim 1, it is characterised in that: low in the step S8 Pressure hot wall chemical vapor sedimentation process conditions are: deposition temperature is 600 DEG C, and deposit pressure is 60Pa, and reaction gas uses silicon Alkane and hydrogen phosphide, carrier gas use helium.
8. a kind of preparation method of SiC-MOS device according to claim 1, it is characterised in that: grid in the step S10 The metal material of pole metal is any one or a few in Al, Pt, Au, TiN, TiNiAg；The overall thickness of the metal-drain Greater than 1 μm, and the metal material of the metal-drain be TiNiAg, VNiAg, TiNiAu, VNiAu in any one or it is several Kind.
9. a kind of preparation method of SiC-MOS device according to claim 1, it is characterised in that: hot in the step S12 Treatment temperature is 850 DEG C, and the processing time is 5min under N2 protection.
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