CN116525681B - Silicon carbide trench gate MOSFET device integrating channel diode and manufacturing method - Google Patents
Silicon carbide trench gate MOSFET device integrating channel diode and manufacturing method Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 59
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 29
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- 238000000034 method Methods 0.000 claims description 18
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- 239000000463 material Substances 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000003892 spreading Methods 0.000 description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
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- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
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- 239000002210 silicon-based material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a silicon carbide trench gate MOSFET device integrating a channel diode and a manufacturing method thereof. The invention forms the grid electrode in the first groove, forms the channel diode control grid in the first groove and the second groove, and integrates the channel diode in the cell on the premise of not increasing the size of the cell. Under the third quadrant working condition, the channel diode serves as a freewheeling diode of the device, so that the conduction of the body diode is restrained, the bipolar degradation effect is avoided, and the power loss is effectively reduced. Meanwhile, the gate capacitance of the device is obviously reduced by introducing the channel diode, and the switching characteristic of the device is effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a silicon carbide trench gate MOSFET device integrated with a channel diode and a manufacturing method thereof.
Background
The development of power electronics systems has placed higher demands on the performance of semiconductor devices in terms of high temperature, high frequency, radiation resistance, high voltage, etc. The traditional silicon material device manufacturing process is mature, but the performance of the material itself limits the application of the silicon device in extreme working environments. Compared with silicon materials, silicon carbide (SiC) materials become one of the most important semiconductor materials for manufacturing high-power devices which can adapt to extreme environments due to the advantages of higher heat conductivity, larger forbidden bandwidth, higher critical breakdown electric field strength and the like.
In SiC power devices, metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are widely used because of their advantages of simple gate drive, fast switching speed, etc. Conventional planar gate SiC MOSFET devices have parasitic junction field effect transistor structures and lower channel mobility, which both result in a greater on-resistance of the device. The trench type SiC MOSFET device not only improves the mobility of the channel, but also eliminates the JFET effect by forming the channel on the side wall of the trench, so that the on-resistance of the device is greatly reduced, the cell size is reduced, and the power density is increased. However, trench SiC MOSFET devices have the following two problems in practical fabrication and application: under high voltage, the electric field concentration effect at the bottom of the groove can influence the reliability of the gate dielectric, so that the device breaks down in advance; and the second is that the gate capacitance of the trench type SiC MOSFET device is large, resulting in poor switching characteristics.
In addition, siC MOSFET devices are typically required to be used in anti-parallel with a diode in applications, and currently there are generally two schemes. First, a parasitic diode inside the SiC MOSFET device is used, but the turn-on voltage of the parasitic diode is high, the reverse recovery characteristic is poor, and the power loss is large. Secondly, siC MOSFET devices are used in anti-parallel with external diodes, but this approach increases cost and metal wiring reduces device reliability.
Disclosure of Invention
The technical purpose is that: aiming at the defects in the prior art, the invention provides a silicon carbide trench gate MOSFET device integrating a channel diode and a manufacturing method thereof, and the channel diode is integrated in a cell on the premise of not increasing the size of the cell, so that the reliability of a gate medium of the trench type SiC MOSFET device is improved, the gate capacitance is reduced, and the bipolar degradation problem caused by the conduction of a body diode is avoided.
The technical scheme is as follows: in order to achieve the technical purpose, the invention adopts the following technical scheme.
A silicon carbide trench gate MOSFET device incorporating a channel diode, comprising,
a drain electrode;
a first conductivity type substrate over the drain electrode;
a first conductivity type epitaxial layer over the first conductivity type substrate;
a second conductivity type channel diode well region located in the first conductivity type epitaxial layer;
a first conductivity type channel diode source region located in the second conductivity type channel diode well region;
a second trench over the first conductivity type channel diode source region and the second conductivity type channel diode well region;
a first trench located above the second trench;
a second conductivity type well region located in the first conductivity type epitaxial layer;
a first conductivity type source region located in the second conductivity type well region;
the first grid electrode and the second grid electrode are respectively positioned at the left side and the right side of the first groove;
the channel diode control gate is positioned in the first groove and the second groove;
the first gate dielectric layer is positioned in the second groove, and the bottom of the channel diode control gate is provided with a first gate dielectric layer;
the second gate dielectric layer is positioned in the first groove, at one side of the first gate electrode far away from the channel diode control gate, and at one side of the second gate electrode far away from the channel diode control gate;
the third gate dielectric layer is positioned in the first groove and the second groove, between the first gate electrode and the channel diode control gate and between the second gate electrode and the channel diode control gate;
the isolation medium layer is positioned on the first conductive type epitaxial layer and is divided into a left part and a right part to completely cover the gate electrode;
and the source electrode is positioned on the first conductive type epitaxial layer, and two sides and on the isolation dielectric layer.
A preparation method of a silicon carbide trench gate MOSFET device integrating a channel diode comprises the following steps:
step 1, epitaxially growing a first conductive type epitaxial layer on a first conductive type substrate;
step 2, forming a second conductive type well region and a first conductive type source region in the first conductive type epitaxial layer;
step 3, etching the epitaxial layer of the first conductivity type to form a first groove;
step 4, etching the bottom of the first groove to form a second groove communicated with the first groove;
step 5, forming a first conduction type channel diode source region and a second conduction type channel diode well region at the bottom of the second groove;
step 6, forming a first gate dielectric layer and a second gate dielectric layer on the side walls of the first groove and the second groove and the bottom of the second groove, and forming channel diode control gate materials filling the first groove and the second groove between the first gate dielectric layer and the second gate dielectric layer;
step 7, removing part of channel diode control gate material to form a channel diode control gate, forming a third gate dielectric layer on two sides of the channel diode control gate, and forming a first gate electrode and a second gate electrode between the second gate dielectric layer and the third gate dielectric layer;
step 8, forming an isolation medium layer on the surface of the first conductive type epitaxial layer;
and 9, forming a source ohmic contact on the surface of the first conductive type epitaxial layer, forming a drain ohmic contact on the bottom layer of the first conductive type substrate, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the semiconductor material adopted by the device, i.e. the material adopted by the first conductivity type substrate 2 and the first conductivity type epitaxial layer 3, may be 3C-SiC, 4H-SiC or 6H-SiC.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, when the silicon carbide trench gate MOSFET device of the integrated channel diode is used as a cell, the arrangement mode of the cell can be strip-shaped, hexagonal, square or atomic lattice.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the depth of the first trench is 0.6 mu m-2.5 mu m, the width of the first trench is 0.6 mu m-1.5 mu m, the depth of the first trench is larger than the depth of the second conductive type well region, and the difference between the depth of the first trench and the depth of the second trench is not smaller than 0.2 mu m.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the depth of the second trench is 0.2 mu m-1.0 mu m, the width of the second trench is 1.0 mu m-2.5 mu m, the width of the second trench is larger than that of the first trench, and the difference between the second trench and the first trench is not smaller than 0.2 mu m.
Further optimization scheme of silicon carbide trench gate MOSFET device as integrated channel diode, doping concentration of epitaxial layer of first conductivity type is 1e15cm -3 ~ 1e17cm -3 。
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the depth of the source region of the channel diode of the first conductivity type is 0.1-0.5 mu m, the width is 0.5-2.5 mu m, and the doping concentration is 5e18cm -3 ~ 5e19cm -3 。
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the depth of the second conduction type channel diode well region is 0.3 mu m-1.5 mu m, the depth of the second conduction type channel diode well region is larger than that of the first conduction type channel diode source region, and the difference of the depth of the second conduction type channel diode well region and the first conduction type channel diode well region is not smaller than 0.2 mu m.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the width of the second conduction type channel diode well region is 0.8-3.5 mu m, the width of the second conduction type channel diode well region is larger than that of the first conduction type channel diode source region, and the difference of the two is not smaller than 1.0 mu m.
As a further optimization scheme of the silicon carbide trench gate MOSFET device of the integrated channel diode, the doping concentration of the well region of the channel diode of the second conductivity type is 8e16cm -3 ~ 1e17cm -3 。
As a further optimization of the silicon carbide trench gate MOSFET device of the integrated channel diode, the isolation dielectric layer may be silicon dioxide, nitride, or a composite of silicon dioxide and nitride.
The beneficial effects are that:
(1) The silicon carbide trench gate MOSFET device integrating the channel diode provided by the invention has the advantages that the gate electrode is formed in the first trench, the channel diode control gate is formed in the first trench and the second trench, the first conduction type channel diode source region and the second conduction type channel diode well region are formed at the bottom of the second trench, the gate electrode is used for controlling the longitudinal conduction channel, and the channel diode control gate is used for controlling the conduction of the channel diode under the third quadrant working condition.
(2) The silicon carbide trench gate MOSFET device integrating the channel diode is characterized in that the channel diode is integrated in a cell on the premise of not increasing the size of the cell by forming the second trench communicated with the first trench. Under the third quadrant working condition, the integrated channel diode is conducted before the body diode, so that bipolar degradation effect is eliminated, starting voltage is reduced, and switching loss is reduced.
(3) The silicon carbide trench gate MOSFET device of the integrated channel diode provided by the invention forms the second conduction type trench diode well region at the bottom of the second trench, and in the off state, the second conduction type trench diode well region effectively protects the gate dielectric layer, thereby improving the reliability of the device, and the integrated trench diode structure greatly reduces the gate capacitance of the device, so that the switching characteristic of the device is improved.
Drawings
Fig. 1 is a schematic structural diagram of a silicon carbide trench gate MOSFET device of example 1 integrated with a channel diode;
fig. 2 is a schematic structural diagram of a silicon carbide trench gate MOSFET device of example 2 integrated with a channel diode;
fig. 3 is a schematic structural diagram of a silicon carbide trench gate MOSFET device of example 3 integrated with a channel diode;
fig. 4 is a schematic structural diagram of a silicon carbide trench gate MOSFET device of example 4 integrated with a channel diode;
fig. 5 to 13 are schematic views of a process flow of manufacturing a silicon carbide trench gate MOSFET device of example 1 integrated with a channel diode;
reference numerals illustrate: 1. a drain electrode; 2. a first conductivity type substrate; 3. an epitaxial layer of the first conductivity type; 4. a second conductivity type channel diode well region; 5. A first conductivity type channel diode source region; 6-1, a first groove; 6-2, a second groove; 7. a second conductive-type well region; 8. a first conductivity type source region; 9-1, a first gate electrode; 9-2, a second gate electrode; 9-3, a channel diode control gate; 10-1, a first gate dielectric layer; 10-2, a second gate dielectric layer; 10-3, a third gate dielectric layer; 11-1, a first isolation medium layer; 11-2, a second isolation medium layer; 12. a source electrode; 13. a first conductivity type current spreading layer; 14. a lightly doped region of the first conductivity type; 15. and a second conductive type deep well region.
Description of the embodiments
The following description and examples are given for the further explanation and illustration of a silicon carbide trench-gate MOSFET device incorporating a trench diode and a method of manufacturing the same, and it should be understood that the examples are given only for the purpose of illustration and are not to be construed as limiting the scope of the claims, as other alternatives will occur to those skilled in the art and are within the scope of the claims.
Furthermore, in the description of the present invention, the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
A silicon carbide trench gate MOSFET device incorporating a channel diode, as shown in fig. 1, comprising a drain electrode 1; a first conductivity type substrate 2 located above the drain electrode 1, the first conductivity type substrate 2 being a first conductivity type SiC substrate; a first conductivity type epitaxial layer 3 on the first conductivity type substrate 2, the first conductivity type epitaxial layer 3 being a first conductivity type SiC epitaxial layer; the semiconductor material used for the first conductivity type substrate 2 and the first conductivity type epitaxial layer 3 is 3C-SiC, 4H-SiC or 6H-SiC. A second conductivity type channel diode well region 4 located in the first conductivity type epitaxial layer 3; a first conductivity type channel diode source region 5 located in the second conductivity type channel diode well region 4; a second trench 6-2 located over the first conductivity type channel diode source region 5 and the second conductivity type channel diode well region 4; a first trench 6-1 located above the second trench 6-2; a well region 7 of the second conductivity type located in the epitaxial layer 3 of the first conductivity type; a first conductivity type source region 8 located in the second conductivity type well region 7; first gate electrodes 9-1 and second gate electrodes 9-2 located on left and right sides of the first trench 6-1; a channel diode control gate 9-3 located in the first trench 6-1, the second trench 6-2; a first gate dielectric layer 10-1 located in the second trench 6-2 below the channel diode control gate 9-3; a second gate dielectric layer 10-2 located in the first trench 6-1, on a side of the first gate electrode 9-1 away from the channel diode control gate 9-3, and on a side of the second gate electrode 9-2 away from the channel diode control gate 9-3; a third gate dielectric layer 10-3 located in the first trench 6-1, in the second trench 6-2, between the first gate electrode 9-1 and the channel diode control gate 9-3, and between the second gate electrode 9-2 and the channel diode control gate 9-3; the isolation medium layer is positioned on the first conductive type epitaxial layer 3 and completely covers the first gate electrode 9-1 and the second gate electrode 9-2, and is divided into a left part and a right part, namely a first isolation medium layer 11-1 and a second isolation medium layer 11-2; source electrodes 12 located on the first conductivity type epitaxial layer 3 on both sides of the isolation dielectric layer and on the isolation dielectric layer. The material of the isolation dielectric layer can be silicon dioxide, nitride or a composite of silicon dioxide and nitride.
The invention integrates the channel diode, does not sacrifice the conduction performance of the device, and the first conduction type source regions 8 are arranged on two sides of the first groove, so that the first gate electrode 9-1 and the second gate electrode 9-2 can control the conduction channel on the side wall of the first groove, and the conduction performance is ensured.
In this embodiment, the channel diode control gate, the first conductivity type channel diode source region, the second conductivity type channel diode well region and the source electrode are shorted. The channel diode control gate is of an inverted T shape, and the bottom width of the channel diode control gate is larger than the width of the second conduction type channel diode well region.
The first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type.
The silicon carbide trench gate MOSFET device integrating the channel diode is provided in the embodiment, a gate electrode is formed in the first trench, channel diode control gates are formed in the first trench and the second trench, a first conduction type channel diode source region and a second conduction type channel diode well region are formed at the bottom of the second trench, the gate electrode is used for controlling a longitudinal conduction channel, and the channel diode control gates are used for controlling conduction of the channel diode under the third quadrant working condition.
In addition, the first groove and the second groove form a grid groove in the embodiment, the grid groove is in a convex shape, a first grid electrode 9-1 and a second grid electrode 9-2 are formed on two sides of the first groove, and the conduction performance of the device is guaranteed; the gate trench is divided into a first trench and a second trench, so that the requirement of the channel length of the channel diode can be met on the premise of not increasing the cell size, and the channel length of the channel diode is half of the difference between the widths of the second conductive type channel diode well region 4 and the first conductive type channel diode source region 5.
The preparation method of the silicon carbide trench gate MOSFET device integrating the channel diode, as shown in fig. 5-13, comprises the following steps:
step 1, as shown in FIGS. 5 and 6, a first conductivity type epitaxial layer 3 is formed on a first conductivity type substrate 2 by epitaxial growth, the doping concentration of the first conductivity type epitaxial layer 3 being 1e15cm -3 ~ 1e17cm -3 ；
Step 2, as shown in fig. 7, growing an ion implantation mask layer on the surface of the first conductive type epitaxial layer 3 prepared in step 1 through a chemical vapor deposition process, performing patterning treatment on the ion implantation mask layer through a photolithography process, and then forming a second conductive type well region 7 through the ion implantation process; after removing the mask layer, a first conductivity type source region 8 is formed in the same manner;
and 3, as shown in fig. 8, removing the ion implantation mask layer grown in the step 2, forming a patterned etching mask layer on the surface of the first conductive type epitaxial layer 3 of the device prepared in the step 2, performing ICP etching on the first conductive type epitaxial layer by using the patterned etching mask layer, forming a first groove 6-1 in the first conductive type epitaxial layer 3, and removing the etching mask layer. The depth of the first groove 6-1 is 0.6-2.5 mu m, the width of the first groove 6-1 is 0.6-1.5 mu m, the depth of the first groove 6-1 is larger than the depth of the second conductive type well region 7, and the difference between the depth and the depth is not smaller than 0.2 mu m;
step 4, as shown in fig. 9, forming a patterned etching mask layer on the surface of the SiC MOSFET device and the side wall of the first trench 6-1 prepared in step 3, and performing isotropic dry etching on the bottom of the first trench 6-1 by using the patterned etching mask layer, wherein the etching gas is SF 6 、HBr、Cl 2 、O 2 And one or more of Ar gases are combined to form a second groove 6-2 communicated with the first groove, and the etching mask layer is removed. The depth of the second groove 6-2 is 0.2 mu m-1.0 mu m, the width is 1.0 mu m-2.5 mu m, the width of the second groove 6-2 is larger than the width of the first groove 6-1, and two grooves are formedThe difference is not smaller than 0.2 mu m;
step 5, as shown in fig. 10, a patterned ion implantation mask layer is formed on the surface of the device manufactured in step 4, and the bottom of the second trench 6-2 is ion-implanted by using the patterned ion implantation mask layer to form a second conductive type channel diode well region 4, wherein the doping concentration of the second conductive type channel diode well region 4 is 5e16cm -3 ~ 2e17cm -3 Preferably with a doping concentration of 8e16cm -3 ~ 1e17cm -3 The depth is 0.3-1.5 mu m, and the width is 0.8-3.5 mu m; after removing the mask layer, a first conductivity type channel diode source region 5 is formed in the same manner, and then the ion implantation mask layer is removed. Depth of channel diode source region of first conductivity type is 0.1 mu m-0.5 mu m, width is 0.5 mu m-2.5 mu m, doping concentration is 5e18cm -3 ~ 5e19cm -3 The depth of the second conduction type channel diode well region is larger than that of the first conduction type channel diode source region, the difference between the depth and the depth is not smaller than 0.2 mu m, the width of the second conduction type channel diode well region is larger than that of the first conduction type channel diode source region, and the difference between the depth and the width is not smaller than 1.0 mu m;
step 6, as shown in fig. 11, a second gate dielectric layer 10-2 is formed on the sidewall of the first trench 6-1 through an oxidation process, a first gate dielectric layer 10-1 is formed at the bottom of the second trench 6-2, the thickness of the first gate dielectric layer 10-1 is 5 nm-30 nm, the thickness of the second gate dielectric layer 10-2 is 20 nm-90 nm, and the thickness of the second gate dielectric layer 10-2 is about 3-4 times that of the first gate dielectric layer 10-1. The channel diode control gate 9-3 is formed to completely fill the first trench 6-1 and the second trench 6-2 by a chemical vapor deposition process.
Step 7, as shown in fig. 12, a patterned etching mask layer is formed on the surface of the device prepared in step 6, and a part of the channel diode control gate 9-3 in the first trench 6-1 is removed through an etching process. And forming a third gate dielectric layer 10-3 through an oxidation process, wherein the thickness of the third gate dielectric layer is larger than that of the second gate dielectric layer, and the thickness of the third gate dielectric layer 10-3 is 90 nm-300 nm. And forming a first gate electrode 9-1 and a second gate electrode 9-2 between the second gate dielectric layer 10-2 and the third gate dielectric layer 10-3 through a chemical vapor deposition process.
Step 8, as shown in fig. 13, an isolation dielectric layer is deposited on the surface of the device prepared in step 6, a patterned etching mask layer is formed on the surface of the isolation dielectric layer, and a first isolation dielectric layer 11-1 and a second isolation dielectric layer 11-2 are formed through an etching process, wherein the distance between the first isolation dielectric layer 11-1 and the second isolation dielectric layer 11-2 is not smaller than 0.1 mu m. And depositing source metal through the opened source metal window and annealing to form a source ohmic contact. A drain ohmic contact is formed at the bottom layer of the first conductive type substrate 2. A source electrode 12 is formed on the surface of the source ohmic contact layer, and a drain electrode 1 is formed on the surface of the drain ohmic contact layer.
According to the silicon carbide trench gate MOSFET device integrating the channel diode, the second groove communicated with the first groove is formed, the second conduction type channel diode well region 4, the first conduction type channel diode source region 5, the first gate dielectric layer 10-1 and the channel diode control gate 9-3 are arranged, the channel diode control gate 9-3 is communicated with the source electrode 12, and when the thickness of the first gate dielectric layer 10-1 is smaller, the channel diode is integrated in a cell on the premise of not increasing the size of the cell. Under the third quadrant working condition, only a small |V is needed due to the small thickness of the first gate dielectric layer 10-1 DS The value of I, the channel diode control gate 9-3 can control the conduction channel of the channel diode structure to be opened, the first conduction type channel diode source region 5 can collect electrons, the channel diode realizes the freewheel effect, and the body diode is inhibited from being opened; the channel diode integrated by the invention is conducted before the body diode, so that bipolar degradation effect is eliminated, starting voltage is reduced, and switching loss is reduced. In addition, the second conduction type channel diode well region is formed at the bottom of the second groove, and in the off state, the second conduction type channel diode well region effectively protects the gate dielectric layer, the reliability of the device is improved, and the integrated channel diode structure greatly reduces the gate capacitance of the device, so that the switching characteristic of the device is improved.
Example 2
Silicon carbide trench gate MOSFET device integrated with channel diode, as shown in FIG. 2, and in factEmbodiment 1 is substantially the same except that a first conductivity-type current spreading layer 13 is formed under the second conductivity-type well region 7, the first conductivity-type current spreading layer 13 may be formed by epitaxial growth or ion implantation, and the doping concentration is 1e16cm -3 ~1e17cm -3 The thickness range is 0.3 mu m-1.0 mu m; the bottom of the first conductivity type current spreading layer 13 has no specific requirement, and may exceed the bottom of the second trench 6-2 or may not exceed the bottom; the first conductive-type current spreading layer 13 may further reduce the on-resistance of the device.
Example 3
A silicon carbide trench gate MOSFET device integrated with a channel diode, as shown in fig. 3, is different from embodiment 1 in that first conductivity type lightly doped regions 14 are formed at both sides of a first conductivity type channel diode source region 5, and the thickness of the first conductivity type lightly doped regions 14 is the same as the thickness of the first conductivity type channel diode source region 5; the lightly doped region 14 of the first conductivity type can be formed by ion implantation process to a depth equal to the depth of the source region of the channel diode of the first conductivity type, and a doping concentration of 1e11cm -3 ~1e15cm -3 The width of the first conductivity type channel diode source region 5 in this embodiment is smaller than that of the first conductivity type channel diode source region 5 in embodiment 1. The first conductive type lightly doped region 14, the first conductive type channel diode source region 5, the second conductive type channel diode well region 4, the first gate dielectric layer 10-1 and the channel diode control gate 9-3 form a low barrier diode, and under the third quadrant working condition, the parasitic diode conduction of the SiC MOSFET can be restrained, and the bipolar degradation effect is avoided.
Example 4
As shown in fig. 4, the silicon carbide trench gate MOSFET device of the integrated channel diode is different from embodiment 1 in that a second conductivity type deep well region 15 is formed inside the first conductivity type epitaxial layer 3, and the second conductivity type deep well region 15 may be formed by an ion implantation process after the second conductivity type well region 7 is formed. The doping concentration of the second conductive type deep well region 15 is larger than that of the second conductive type well region 7, the width of the second conductive type deep well region is 0.2-1.5 mu m, the thickness of the second conductive type deep well region is 0.6-3.5 mu m, and the thickness of the second conductive type deep well region 15 is larger than that of the second conductive type well region 10. The second conductive deep well region 15 has higher doping concentration and larger thickness, so that in the off state, the PN junction interface formed by the second conductive deep well region 15 and the first conductive epitaxial layer 3 bears larger electric field intensity, plays a role in modulating electric field distribution, further reduces the electric field intensity born by the gate dielectric layer, effectively protects the gate dielectric layer, namely the second conductive deep well region 15 can more effectively protect the first gate dielectric layer 10-1 and the second gate dielectric layer 10-2, and improves the reliability of the device.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (9)
1. A silicon carbide trench gate MOSFET device incorporating a channel diode, comprising,
a drain electrode;
a first conductivity type substrate over the drain electrode;
a first conductivity type epitaxial layer over the first conductivity type substrate;
a second conductivity type channel diode well region located in the first conductivity type epitaxial layer;
a first conductivity type channel diode source region located in the second conductivity type channel diode well region;
a second trench over the first conductivity type channel diode source region and the second conductivity type channel diode well region;
a first trench located above the second trench; the second trench width is greater than the first trench;
a second conductivity type well region located in the first conductivity type epitaxial layer;
a first conductivity type source region located in the second conductivity type well region;
the first grid electrode and the second grid electrode are respectively positioned at the left side and the right side of the first groove;
the channel diode control gate is positioned in the first groove and the second groove; the channel diode control gate is of an inverted T shape, and the bottom width of the channel diode control gate is larger than the width of the second conduction type channel diode well region;
the first gate dielectric layer is positioned in the second groove and at the bottom of the channel diode control gate;
the second gate dielectric layer is positioned in the first groove, at one side of the first gate electrode far away from the channel diode control gate, and at one side of the second gate electrode far away from the channel diode control gate;
the third gate dielectric layer is positioned in the first groove and the second groove, between the first gate electrode and the channel diode control gate and between the second gate electrode and the channel diode control gate;
the isolation medium layer is positioned on the first conductive type epitaxial layer and is divided into a left part and a right part to completely cover the gate electrode;
and the source electrode is positioned on the first conductive type epitaxial layer, two sides of the isolation medium layer and on the isolation medium layer.
2. A silicon carbide trench-gate MOSFET device incorporating a channel diode according to claim 1, wherein the channel diode control gate, the first conductivity type channel diode source region, the second conductivity type channel diode well region are shorted to the source electrode.
3. The silicon carbide trench-gate MOSFET device of claim 1, wherein the second conductivity type channel diode well region has a width greater than a width of the first conductivity type channel diode source region by a factor of two equal to the channel length of the channel diode, and a factor of two different than 1.0 μm.
4. A silicon carbide trench-gate MOSFET device incorporating a channel diode according to claim 1, whichCharacterized in that the thickness of the first gate dielectric layer is 5-30 nm, the thickness of the second gate dielectric layer is 20-90 nm, the thickness of the third gate dielectric layer is 90-300 nm, and the doping concentration of the second conduction type channel diode well region is 5e16cm -3 ~ 2e17cm -3 The isolation medium layer comprises a first isolation medium layer and a second isolation medium layer, the distance between the first isolation medium layer and the second isolation medium layer is not smaller than 0.1 mu m, the width of the second groove is larger than that of the first groove, and the difference between the first isolation medium layer and the second isolation medium layer is not smaller than 0.2 mu m.
5. A method of fabricating a channel diode integrated silicon carbide trench gate MOSFET device according to any of claims 1-4, comprising the steps of:
step 1, epitaxially growing a first conductive type epitaxial layer on a first conductive type substrate;
step 2, forming a second conductive type well region and a first conductive type source region in the first conductive type epitaxial layer;
step 3, etching the epitaxial layer of the first conductivity type to form a first groove;
step 4, etching the bottom of the first groove to form a second groove communicated with the first groove; the second trench width is greater than the first trench;
step 5, forming a first conduction type channel diode source region and a second conduction type channel diode well region at the bottom of the second groove;
step 6, forming a first gate dielectric layer and a second gate dielectric layer on the side walls of the first groove and the second groove and the bottom of the second groove, and forming channel diode control gate materials filling the first groove and the second groove between the first gate dielectric layer and the second gate dielectric layer;
step 7, removing part of channel diode control gate material to form a channel diode control gate, forming a third gate dielectric layer on two sides of the channel diode control gate, and forming a first gate electrode and a second gate electrode between the second gate dielectric layer and the third gate dielectric layer; the channel diode control gate is of an inverted T shape, and the bottom width of the channel diode control gate is larger than the width of the second conduction type channel diode well region;
step 8, forming an isolation medium layer on the surface of the first conductive type epitaxial layer;
and 9, forming a source ohmic contact on the surface of the first conductive type epitaxial layer, forming a drain ohmic contact on the bottom layer of the first conductive type substrate, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
6. The method of manufacturing a trench-gate-diode-integrated silicon carbide MOSFET device as defined in claim 5, wherein the isotropic etching process is performed in step 4, and the etching gas used is SF 6 、HBr、Cl 2 、O 2 One or more of Ar gases.
7. The method of fabricating a trench-gate MOSFET device of claim 5 wherein step 5 forms the first conductivity type trench diode source region and the second conductivity type trench diode well region using an ion implantation process.
8. The method for manufacturing the silicon carbide trench gate MOSFET device of the integrated channel diode according to claim 5, wherein the first gate dielectric layer and the second gate dielectric layer are formed in the step 6 by an oxidation process, and the thickness of the formed second gate dielectric layer is 3-4 times that of the first gate dielectric layer.
9. The method of claim 5, wherein the third gate dielectric layer is formed in step 7 by an oxidation process, and the thickness of the formed third gate dielectric layer is greater than the thickness of the second gate dielectric layer.
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