CN116072698A - Conical gate MOSFET device structure and manufacturing method thereof - Google Patents
Conical gate MOSFET device structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a conical gate MOSFET device structure and a manufacturing method thereof. The device structure comprises a device structure layer arranged on a substrate, a source electrode, a drain electrode and a grid electrode which are matched with the device structure layer, and a groove matched with the grid electrode is formed on the device structure layer; the groove comprises a first part and a second part, the first part and the second part are sequentially arranged along the direction away from the surface of the device structure layer, the side wall of the first part is perpendicular to the surface of the device structure layer, the side wall of the second part forms an included angle which is more than 30 degrees and less than 60 degrees with the surface of the device structure layer, the bottom surface of the second part is a groove bottom wall, and the groove bottom wall is parallel to the surface of the device structure layer. The tapered gate MOSFET device structure has high reverse breakdown voltage and good forward conduction performance.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a tapered gate MOSFET device structure and a manufacturing method thereof.
Background
Silicon carbide (SiC) is one of the third generation wide bandgap semiconductors, and has many superior and unique electrical, mechanical and chemical properties, such as large bandgap, high electron and hole mobility, extremely high hardness, high wear resistance, high quality factor Q, high thermal conductivity, high chemical resistance, etc., which makes it have a wide application prospect in the fields of high power, high temperature and high frequency power electronics.
The SiC UMOSFET (U Metal-Oxide-Semiconductor Field-Effect Transistor) device structure is characterized by a "U" trench gate, and the trench is perpendicular to the device surface, effectively eliminating the JFET (Junction Field-Effect Transistor) resistance inside the device. Under the same conditions, the on-resistance of the UMOSFET structure device can be significantly reduced. In addition, the channel region and the source region of the UMOSFET structure can be formed in an epitaxial growth mode, adverse effects caused by an ion implantation method can be avoided, and the SiC UMOSFET structure is more advantageous and can obtain smaller on-resistance.
However, the SiC UMOSFET structure also has a very important self-problem that in the device blocking state, the electric field intensity of the gate dielectric layer at the bottom of the trench of the UMOSFET is very high, which is about 2.5 times of the peak electric field intensity of the PN junction, and the electric field is more concentrated at the corner of the bottom of the trench due to the two-dimensional effect, so that the electric field intensity of the SiC UMOSFET device is higher, which makes the gate dielectric layer of the SiC UMOSFET device at the corner of the trench gate break down more easily, thereby causing the reliability of the device to be reduced. Most solutions are to place the electric field shielding structure at the bottom of the trench and to bring the electric field shielding structure close to the bottom of the trench. However, when the device is in forward conduction, the depletion regions of the two PN junctions formed between the base region and the drift region and between the electric field shielding structure and the drift region of the device are enlarged, forming JFET regions. The presence of JFETs narrows the conduction path of the current, thereby reducing the current conduction capability.
Therefore, how to provide a method for preventing the gate dielectric layer at the bottom of the groove from breakdown without introducing a new JFET region or enlarging the JFET region is an urgent problem to be solved.
Disclosure of Invention
The invention mainly aims to provide a tapered gate MOSFET device structure and a manufacturing method thereof, which are used for overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a tapered gate MOSFET device structure, which comprises:
device structure layer disposed on a substrate
The source electrode, the drain electrode and the grid electrode are matched with the device structure layer, and a groove matched with the grid electrode is formed on the device structure layer;
the groove comprises a first part and a second part, the first part and the second part are sequentially arranged along the direction away from the surface of the device structure layer, the side wall of the first part is perpendicular to the surface of the device structure layer, the side wall of the second part forms an included angle which is more than 30 degrees and less than 60 degrees with the surface of the device structure layer, the bottom surface of the second part is a groove bottom wall, and the groove bottom wall is parallel to the surface of the device structure layer.
The embodiment of the invention also provides a manufacturing method of the tapered gate MOSFET device structure, which comprises the following steps:
forming a device structure layer on a first surface of the substrate;
forming a groove in the device structure layer, enabling the side wall of a first part of the groove to be perpendicular to the surface of the device structure layer, enabling the side wall of a second part to form an included angle which is larger than 30 degrees and smaller than 60 degrees with the surface of the device structure layer, and enabling the bottom wall of the second part to be parallel to the surface of the device structure layer;
manufacturing a grid electrode, a source electrode and a drain electrode; and
and forming a shielding layer in the drift region of the device structure layer, and enabling the shielding layer to be distributed on two sides of the groove.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the tapered gate MOSFET device structure and the manufacturing method thereof, the groove is designed into two parts, the side wall of the first part is perpendicular to the surface of the device, the side wall of the second part and the surface of the device are arranged at a certain angle, the bottom surface of the second part and the surface of the device are arranged in parallel, meanwhile, the electric field shielding structures are arranged on two sides of the side wall of the second part of the groove, the forward current density of the device is greatly improved, the reverse breakdown voltage of 1345V is achieved, the electric field strength of gate dielectric is 3.05MV/cm under the reverse blocking voltage of 1200V, and the device has higher reliability.
(2) The tapered gate MOSFET device structure and the manufacturing method thereof have the advantages that the tapered gate MOSFET device structure has higher current density, and the same current output capacity can be obtained by using fewer cells in actual device preparation. The reduction of the cell density relatively reduces the gate area and reduces the gate-drain capacitance C D The driving loss is reduced, and the switching speed is increased.
(3) According to the conical gate MOSFET device structure and the manufacturing method thereof, the current spreading layer is arranged between the drift region and the base region of the device, so that electrons are laterally spread when exiting a channel, and the influence of PN junctions formed by direct contact between the base region and the drift region on a current channel is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a schematic diagram of a tapered gate MOSFET device in an exemplary embodiment of the invention;
fig. 2 a-2 k are schematic flow diagrams illustrating a fabrication process of a tapered gate MOSFET device structure according to an exemplary embodiment of the invention.
Detailed Description
In view of the defects of the prior art, the inventor of the present invention has made long-term researches and a great deal of practices to propose the technical scheme of the present invention, and aiming at the fact that the existing trench gate MOSFET device can introduce a new JFET region while reducing the electric field intensity of a gate dielectric layer at the bottom of a trench, and reduce the forward conduction capability of the device. Meanwhile, the electric field shielding structures are arranged on two sides of the bottom of the groove to reduce the electric field intensity of the gate dielectric in the groove, so that the reverse blocking capacity and the forward conduction capacity of the device reach a compromise level, the reverse breakdown voltage of the device is improved as much as possible, and meanwhile, the width of the JFET region is increased, so that the forward conduction resistance of the device can be reduced, and the output current of the device is improved.
The technical scheme of the invention will be further clearly and in detail described below.
One aspect of an embodiment of the present invention provides a tapered gate MOSFET device structure comprising:
device structure layer disposed on a substrate
The source electrode, the drain electrode and the grid electrode are matched with the device structure layer, and a groove matched with the grid electrode is formed on the device structure layer;
the groove comprises a first part and a second part, the first part and the second part are sequentially arranged along the direction away from the surface of the device structure layer, the side wall of the first part is perpendicular to the surface of the device structure layer, the side wall of the second part forms an included angle which is more than 30 degrees and less than 60 degrees with the surface of the device structure layer, the bottom surface of the second part is a groove bottom wall, and the groove bottom wall is parallel to the surface of the device structure layer.
Because the first part of the groove is of a vertical structure, the second part of the groove is of an inclined structure, and the conducting channel of the device is formed at the side wall of the first part, when the MOSFET device is conducted in the forward direction, current flows downwards out of the vertical channel, and can flow downwards and rapidly to the inside of the drift region along an inclined plane, so that the phenomenon of aggregation at the corner of the groove bottom can be avoided.
Further, the device structure layer comprises a drift region and a base region which are sequentially arranged on the first surface of the substrate, and a first ohmic contact region and a second ohmic contact region are arranged on the base region; the substrate, the drift region and the first ohmic contact region are all of a first conductivity type, and the base region and the second ohmic contact region are all of a second conductivity type.
Further, either one of the first conductivity type and the second conductivity type is P-type, the other is N-type, and the corresponding MOSFET device is a P-channel MOSFET device or an N-channel MOSFET device.
Further, the device structure layer further comprises a current expansion layer of the first conductivity type, and the current expansion layer is arranged between the drift region and the base region.
Further, a second portion of the recess is disposed within the drift region.
Further, a shielding layer is further arranged in the drift region, and the shielding layer is arranged between the groove and the substrate.
Further, the shielding layer is located at two sides of the groove and is close to the side wall of the second portion of the groove, when the MOSFET device is turned on in the forward direction, a stronger electric field is formed between the shielding layer and the inclined side wall of the groove, and electrons can obtain a higher drift velocity.
Furthermore, the base region, the first ohmic contact region, the second ohmic contact region, the current expansion layer and the shielding layer are formed by converting a local area of the drift region.
Further, the side surfaces of the first ohmic contact region and the second ohmic contact region are contacted, and the source electrode is arranged on the surfaces of the first ohmic contact region and the second ohmic contact region.
Furthermore, polysilicon is filled in the grooves, the grid electrode is arranged on the polysilicon, and a grid dielectric layer is arranged between the polysilicon and the grooves.
Further, the drain electrode is disposed on the second surface of the substrate.
Further, the substrate comprises a silicon carbide substrate.
The embodiment of the invention also provides a manufacturing method of the tapered gate MOSFET device structure, which comprises the following steps:
forming a device structure layer on a first surface of the substrate;
forming a groove in the device structure layer, enabling the side wall of a first part of the groove to be perpendicular to the surface of the device structure layer, enabling the side wall of a second part to form an included angle which is larger than 30 degrees and smaller than 60 degrees with the surface of the device structure layer, and enabling the bottom wall of the second part to be parallel to the surface of the device structure layer; and
and manufacturing a grid electrode, a source electrode and a drain electrode.
Further, the manufacturing method further comprises the following steps: and forming a shielding layer in the drift region of the device structure layer, and enabling the shielding layer to be distributed on two sides of the groove.
Further, the manufacturing method specifically includes:
forming a first part of drift region on a first surface of a substrate in an epitaxial manner;
forming shielding layers on two sides of the first part of drift region in an ion implantation mode;
epitaxially growing a second partial drift region on the first partial drift region;
sequentially forming a current expansion layer, a base region and a first ohmic contact region from bottom to top in the second part drift region in an ion implantation mode, and forming a second ohmic contact region in the first ohmic contact region, wherein the upper surfaces of the first ohmic contact region and the second ohmic contact region are leveled with the upper surface of the second part drift region;
covering a mask on the upper surface of the second part drift region, performing first etching to form a second part of the groove, and removing the mask;
covering a mask on the upper surface of the second part drift region again, and performing second etching to enable the second part of the groove to move downwards synchronously so as to form a first part of the groove;
forming a gate dielectric layer on the inner wall of the groove in a high-temperature dry-oxygen oxidation mode, carrying out high-temperature annealing, depositing polysilicon in the groove, and carrying out high-temperature activation annealing to enable the polysilicon to have conductivity;
and forming a grid source electrode and a grid drain electrode by a magnetron sputtering mode.
The following describes the technical solution in the embodiments of the present invention in detail with reference to the drawings, and the materials and the processing techniques of the MOSFET device related in the embodiments of the present invention are known to those skilled in the art unless specifically described otherwise.
Referring to fig. 1, a tapered gate MOSFET device structure includes a silicon carbide n+ substrate 11 and a device structure layer sequentially formed on the silicon carbide n+ substrate 11, where the device structure layer includes an N-type drift region 10, an n+ type current spreading layer 6 and a p+ type base region 5 sequentially stacked on a first surface of the silicon carbide n+ substrate 11, an n+ type ohmic contact region 4 formed on the p+ type base region 5, and p+ type ohmic contact regions 3 distributed on two sides of the n+ type ohmic contact region 4, where the n+ type ohmic contact region 4 contacts with a side surface of the p+ type ohmic contact region 3. The above-mentioned device structure layer is further formed with a groove 13, where the groove 13 includes a first portion 131 and a second portion 132, the sidewall of the first portion 131 is perpendicular to the surface of the device structure layer, the sidewall of the second portion 132 has an included angle of 45 degrees with the surface of the device, and the bottom surface of the second portion 132 is a bottom wall of the groove and is parallel to the surface of the device.
Specifically, the first portion 131 of the recess 13 sequentially penetrates through the n+ type ohmic contact region 4 and the p+ type base region 5 along the thickness direction of the device structure layer and extends to the N-type drift region 10, and the first portion 132 of the recess 13 is completely disposed in the N-type drift region 10.
Specifically, a p+ shielding layer 9 is further formed in the N-type drift region 10, wherein the p+ shielding layer 9 is distributed on two sides of the sidewall of the second portion 132 of the recess 13.
Specifically, the channel region of the MOSFET device structure in this embodiment is formed in the p+ type base region 5 and near the side wall of the first portion 131 of the recess 13, where the channel is a vertical channel, and when the device is turned on in the forward direction, current flows downward out of the vertical channel, the current can flow downward and quickly into the drift region 10 along the inclined plane of the second portion 132 of the recess 13, so that the phenomenon that electrons gather at the bottom of the flat bottom trench in the conventional device structure does not occur. In addition, when the device is turned on in the forward direction, a stronger electric field is formed between the p+ shielding layer 9 and the gate bottom of the inclined plane, and electrons can obtain higher drift velocity. In addition, when the device is blocked in the reverse direction, the P+ shielding layer 9 can shield the electric field, and has a good protection effect on the grid medium.
Specifically, an n+ current spreading layer 6 is further distributed between the p+ base region 5 and the N-type drift region 10, so that electrons can be laterally spread when exiting the channel, and the influence of a PN junction formed by direct contact between the p+ base region 5 and the N-type drift region 10 on a current channel is avoided.
Specifically, the inside of the groove 11 is filled with polysilicon 7, a gate dielectric layer 8 is formed between the polysilicon 7 and the entire inner wall of the groove 11, and a gate electrode 1 is formed on the polysilicon 7.
Specifically, a source electrode 2 is formed on the surface of the p+ -type ohmic contact region 3 and the n+ -type ohmic contact region 4 on both sides of the gate electrode 1, and a drain electrode 12 is formed on the second surface of the silicon carbide n+ -type substrate 11.
In the MOSFET device of this embodiment, only one PN junction between the p+ -type shield layer 9 and the N-type drift region 10 is provided between the p+ -type shield layer 9 and the sidewall of the second portion 132 of the recess 13, and no JEFT region is formed. The JFET is formed only between two P+ shield layers 9, and thisThe JFET is wide and has little effect on-resistance. And a high electric field is formed between the p+ type shielding layer 9 and the side wall of the second portion 132 of the groove 13, which increases the drift velocity of electrons during forward conduction of the device and improves the forward conduction performance of the device. Compared with the conventional silicon carbide UMOSFET, the current channel of the device in the embodiment is wider, and the inventor simulates by simulation software that the on-resistance of the device can be reduced by 12.1 percent (from 1.82mΩ cm) compared with the conventional P+ UMOFET 2 Down to 1.60mΩ & cm 2 ) The current density can be increased by 46.6% in forward conduction (from 3.20 e-4A/mu m) 2 Lifting to 4.69 e-4A/. Mu.m 2 )。
Specifically, the manufacturing method of the tapered gate MOSFET device structure comprises the following steps:
1) A first portion of the N-type drift region 10 is epitaxially formed on a first surface of a silicon carbide n+ substrate 11. Wherein the N-doping concentration is 8×10 15 cm -3 As shown in fig. 2 a;
2) A patterned silicon dioxide mask 14 is covered on the upper surface of the first part of N-type drift region 10, a P+ type shielding layer 9 is formed by injecting aluminum ions 15, and then the silicon dioxide mask 14 is removed, wherein the doping concentration of the aluminum ions is 1 multiplied by 10 19 cm -3 As shown in fig. 2 b;
3) Continuing to form a second portion of the N-type drift region 10 having the same doping concentration as the first portion of the N-type drift region 10 by means of epitaxy on the first portion of the N-type drift region 10, as shown in fig. 2 c;
4) An N + type current spreading layer 6 is formed in the second portion of the N-type drift region 10 by implanting nitrogen ions 16. Wherein the doping concentration of nitrogen ions is 1 multiplied by 10 17 cm -3 As shown in fig. 2 d;
5) A p+ -type base region 5 is formed by implanting aluminum ions 15 in the second portion of the N-type drift region 10 above the p+ -type current spreading layer 6. Wherein the doping concentration of aluminum ions is 2X 10 17 cm -3 As shown in fig. 2 e;
6) An N+ type ohmic contact region 4 is formed in the second part of the N-type drift region 10 above the P+ type base region 5 by injecting nitrogen ions 16 so that the upper surface of the N+ type ohmic contact region 4 is connected with the first partThe upper surface of the two-part N-type drift region 10 is leveled. Wherein the doping concentration of nitrogen ions is 1 multiplied by 10 19 cm -3 As shown in fig. 2 f;
7) A patterned silicon dioxide mask 17 is covered on the upper surface of the second part of N-type drift region 10, and P+ type ohmic contact regions 3 are formed on two sides of the N+ type ohmic contact region 4 by injecting aluminum ions 15, and then the silicon dioxide mask 142 is removed, wherein the doping concentration of the aluminum ions is 1×10 19 cm -3 As shown in fig. 2 g;
8) A patterned mask (not shown in fig. 2 g) is provided on the upper surface of the second portion N-type drift region 10, exposing the corresponding region of the notch of the recess 13, and performing a first etching to form a second portion 132 of the recess 13, where the etching depth is 1 μm, and the sidewall of the second portion 132 forms an angle of 45 degrees with the plane of the device, and then removing the mask. The masking may be a photoresist or other masking with a lower etch selectivity to the silicon carbide material that helps form sloped sidewalls of the second portion 132, as shown in fig. 2 h.
9) A patterned mask (not shown in fig. 2 h) is again provided on the upper surface of the second portion N-type drift region 10, exposing the corresponding region of the notch of the recess 13, and performing a second etching with an etching depth of 1.7 μm, during which the side wall of the formed second portion 132 moves downward synchronously, and finally the first portion 131 of the recess 13 is formed. The mask may be a silicon dioxide mask or other mask having a high etch selectivity to silicon carbide material to facilitate formation of vertical sidewalls of the first portion 131, as shown in fig. 2 i.
10 A gate dielectric layer 8 is formed on the inner wall of the formed groove 13 by a high-temperature dry-oxygen oxidation mode, wherein the thickness of the gate dielectric layer 8 on the vertical surface part is 50nm, the gate dielectric layer 8 can be made of silicon dioxide, and then the interface state density of the interface between silicon carbide and silicon dioxide is reduced by adopting a high-temperature nitric oxide annealing mode, as shown in fig. 2 j.
11 Polysilicon 7 is deposited in the grooves 13, the required polysilicon structure is obtained by etching, P-type heavy doping is carried out on the deposited polysilicon 7, and high-temperature activation annealing is carried out, so that the polysilicon 7 has conductivity, as shown in fig. 2 k.
12 Forming a grid electrode 1, a source electrode 2 and a drain electrode 12 by means of magnetron sputtering metal, and performing high-temperature annealing to form ohmic alloy so as to finish the manufacture of the device. The ohmic contact metal of the source electrode 2 and the drain electrode 12 is Ni/Al alloy, and the Al metal is thickened, and the ohmic contact metal of the gate electrode 1 is Al, as shown in fig. 1.
In addition, the inventors have conducted experiments with other materials, process operations, and process conditions as described in this specification with reference to the foregoing examples, and have all obtained desirable results.
It should be understood that the technical solution of the present invention is not limited to the above specific embodiments, and all technical modifications made according to the technical solution of the present invention without departing from the spirit of the present invention and the scope of the claims are within the scope of the present invention.
Claims (13)
1. A tapered gate MOSFET device structure comprising:
a device structure layer arranged on the substrate (11), and
the source electrode (2), the drain electrode (12) and the grid electrode (1) are matched with the device structure layer, and a groove (13) matched with the grid electrode (1) is formed on the device structure layer;
the method is characterized in that: the groove (13) comprises a first part and a second part, the first part and the second part are sequentially arranged along the direction away from the surface of the device structure layer, the side wall (131) of the first part is perpendicular to the surface of the device structure layer, the side wall (132) of the second part and the surface of the device structure layer form an included angle which is larger than 30 degrees and smaller than 60 degrees, the bottom surface of the second part is a groove bottom wall, and the groove bottom wall is parallel to the surface of the device structure layer.
2. The tapered gate MOSFET device structure of claim 1, wherein: the device structure layer comprises a drift region (10) and a base region (5) which are sequentially arranged on the first surface of a substrate (11), and a first ohmic contact region (4) and a second ohmic contact region (3) are arranged on the base region (5); the substrate (11), the drift region (10) and the first ohmic contact region (4) are of a first conductivity type, and the base region (5) and the second ohmic contact region (3) are of a second conductivity type.
3. The tapered gate MOSFET device structure of claim 2, wherein: either one of the first conductivity type and the second conductivity type is P type, and the other is N type.
4. The tapered gate MOSFET device structure of any of claims 2, wherein: the device structure layer further comprises a current spreading layer (6) of the first conductivity type, the current spreading layer (6) being arranged between the drift region (10) and the base region (5).
5. The tapered gate MOSFET device structure of claim 2, wherein: a second portion of the recess (13) is arranged in the drift region (10).
6. The tapered gate MOSFET device structure of claim 5, wherein: a shielding layer (9) is further arranged in the drift region (10), and the shielding layer (9) is arranged between the groove (13) and the substrate (11); and/or the shielding layer (9) is positioned at two sides of the groove (13).
7. The tapered gate MOSFET device structure of any one of claims 2-5, wherein: the base region (5), the first ohmic contact region (4), the second ohmic contact region (3), the current expansion layer (6) and the shielding layer (9) are formed by converting a local area of the drift region (10).
8. The tapered gate MOSFET device structure of claim 2, wherein: the first ohmic contact region (4) and the second ohmic contact region (3) are in contact on the side surfaces, and the source electrode is arranged on the surfaces of the first ohmic contact region (4) and the second ohmic contact region (3).
9. The tapered gate MOSFET device structure of claim 1, wherein: the grooves (13) are filled with polysilicon (7), and the grid (1) is arranged on the polysilicon (7); and/or a gate dielectric layer (8) is also arranged between the polysilicon (7) and the groove (13).
10. The tapered gate MOSFET device structure of claim 1, wherein: the drain electrode (12) is arranged on the second surface of the substrate (11); and/or the substrate (11) comprises a silicon carbide substrate.
11. A method of fabricating a tapered gate MOSFET device structure as recited in any one of claims 1-10, comprising:
forming a device structure layer on a first surface of the substrate (11);
forming a groove (13) in the device structure layer, and arranging a side wall (131) of a first part of the groove (13) perpendicular to the surface of the device structure layer, forming an included angle of more than 30 degrees and less than 60 degrees with the surface of the device structure layer by a side wall (132) of a second part, and arranging a bottom wall of the second part parallel to the surface of the device structure layer; and
and manufacturing a grid electrode (1), a source electrode (2) and a drain electrode (12).
12. The method of manufacturing according to claim 11, further comprising: a shielding layer (9) is formed in the drift region (10) of the device structure layer, and the shielding layer (9) is distributed on two sides of the groove (13).
13. The manufacturing method according to claim 11, characterized by comprising the following steps:
epitaxially forming a first portion of a drift region (10) on a first surface of a substrate (11);
forming shielding layers (9) on two sides of the first part of drift region (10) in an ion implantation mode;
epitaxially growing a second portion of the drift region (10) on the first portion of the drift region (10);
forming a current expansion layer (6), a base region (5) and a first ohmic contact region (4) in the second part drift region (10) from bottom to top in sequence by means of ion implantation, and forming a second ohmic contact region (3) in the first ohmic contact region (4), wherein the upper surfaces of the first ohmic contact region (4) and the second ohmic contact region (3) are leveled with the upper surface of the second part drift region (10);
covering a mask on the upper surface of the second part drift region (10), performing first etching to form a second part of the groove (13), and removing the mask;
covering a mask on the upper surface of the second part drift region (10) again, and performing second etching to synchronously move down the second part of the groove (13) so as to form a first part of the groove (13);
forming a gate dielectric layer (8) on the inner wall of the groove (13) by high-temperature dry-oxygen oxidation, performing high-temperature annealing, then depositing polycrystalline silicon (7) in the groove (8), and performing high-temperature activation annealing to enable the polycrystalline silicon (7) to have conductivity;
the grid electrode (1), the source electrode (2) and the drain electrode (12) are formed by means of magnetron sputtering metal.
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| CN116454116B (en) * | 2023-06-01 | 2023-09-12 | 苏州华太电子技术股份有限公司 | Trench MOSFET device and manufacturing method thereof |
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